From nobody Sat Oct 4 01:47:31 2025 Received: from mta-65-226.siemens.flowmailer.net (mta-65-226.siemens.flowmailer.net [185.136.65.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B3B3D28C869 for ; Thu, 21 Aug 2025 12:01:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.136.65.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755777688; cv=none; b=UViyQGuWwKcN5wmk1USA9L21pePgJMtbRlS1fR5e3y9wesSD1Gm7o0+4/7qYxIldyQ5vBzdrWFPkZv1BdWPQ4b0EaNeo8j7YVtri7CExeQoc4GF5H9fS2hl72lGCZFC8ctvGd+8awzQqgzw08/RA5iUxsE4v6ILoPEQxNkjtKE0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755777688; c=relaxed/simple; bh=AZqPOIs8oTppgZY6LZx0VdFQyYDMm9MLTjA6k0xXVeM=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=PH/qAE8zSQx6jtBtUH2rOgS8dn1pOOOmx4ea3U5RfKcSOQNBNhe32Yq0RsROazJNkEizewLixreImYwVzeWbph5rvCerImhzhu5vP2wMZUQxVcfckDNRDzSlYcyiaz439AqPueRxo90OeOWigiQVl/GK0L5ueeWdIdaSCaig7yw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b=FANoF1CS; arc=none smtp.client-ip=185.136.65.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=siemens.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rts-flowmailer.siemens.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=siemens.com header.i=alexander.sverdlin@siemens.com header.b="FANoF1CS" Received: by mta-65-226.siemens.flowmailer.net with ESMTPSA id 202508211201150eea1a82f96fed1571 for ; Thu, 21 Aug 2025 14:01:15 +0200 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; s=fm2; d=siemens.com; i=alexander.sverdlin@siemens.com; h=Date:From:Subject:To:Message-ID:MIME-Version:Content-Type:Content-Transfer-Encoding:Cc; bh=uFziv+Xoqi8s1O750PzRShk/r5lOsnFwo6no1Ndpf4A=; b=FANoF1CSNcNhr0AzulgktsCv51sdgu0zyLNmYj8uo+YgW5H+jcFgTEBccktzoVBc0cXQqz WZxAe1J/kqCmDXahSLd0oi//0StCM16PlOty2c9HNjqo71J6+dTuX1xgCG/1Aj6pakw2thA/ RYHKTD3gGvm0zZ0d+dngae0QJm40XFUVUER0jtG41a7XMMuvBLMqwHF6mhG8SaWMpdKggF7/ soaC1OgPgeedpFJghTnbrTLjH2Xyny5SZAZoVdbmJpwBucU1OejrhxmRA386vL2ywecXGz5+ /NkOrAmXc/He6Bki0O2CQJj6dtLU7aCGNdD0WrAOBgIKIRO5b8Z2w9ow==; From: "A. Sverdlin" To: Boris Brezillon , linux-mtd@lists.infradead.org Cc: Alexander Sverdlin , Balamanikandan.Gunasundar@microchip.com, Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Nicolas Ferre , Alexandre Belloni , Claudiu Beznea , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Subject: [PATCH v2] mtd: nand: raw: atmel: Respect tAR, tCLR in read setup timing Date: Thu, 21 Aug 2025 14:00:57 +0200 Message-ID: <20250821120106.346869-1-alexander.sverdlin@siemens.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Flowmailer-Platform: Siemens Feedback-ID: 519:519-456497:519-21489:flowmailer Content-Type: text/plain; charset="utf-8" From: Alexander Sverdlin Having setup time 0 violates tAR, tCLR of some chips, for instance TOSHIBA TC58NVG2S3ETAI0 cannot be detected successfully (first ID byte being read duplicated, i.e. 98 98 dc 90 15 76 14 03 instead of 98 dc 90 15 76 ...). Atmel Application Notes postulated 1 cycle NRD_SETUP without explanation [1], but it looks more appropriate to just calculate setup time properly. [1] Link: https://ww1.microchip.com/downloads/aemDocuments/documents/MPU32/= ApplicationNotes/ApplicationNotes/doc6255.pdf Cc: stable@vger.kernel.org Fixes: f9ce2eddf176 ("mtd: nand: atmel: Add ->setup_data_interface() hooks") Signed-off-by: Alexander Sverdlin Tested-by: Alexander Dahl --- v2: - Cc'ed stable - reformatted atmel_smc_cs_conf_set_setup() call - rebased onto mtd/fixes drivers/mtd/nand/raw/atmel/nand-controller.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/mtd/nand/raw/atmel/nand-controller.c b/drivers/mtd/nan= d/raw/atmel/nand-controller.c index dedcca87defc7..ad0eff385e123 100644 --- a/drivers/mtd/nand/raw/atmel/nand-controller.c +++ b/drivers/mtd/nand/raw/atmel/nand-controller.c @@ -1377,14 +1377,24 @@ static int atmel_smc_nand_prepare_smcconf(struct at= mel_nand *nand, if (ret) return ret; =20 + /* + * Read setup timing depends on the operation done on the NAND: + * + * NRD_SETUP =3D max(tAR, tCLR) + */ + timeps =3D max(conf->timings.sdr.tAR_min, conf->timings.sdr.tCLR_min); + ncycles =3D DIV_ROUND_UP(timeps, mckperiodps); + totalcycles +=3D ncycles; + ret =3D atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NRD_SHIFT, ncycles= ); + if (ret) + return ret; + /* * The read cycle timing is directly matching tRC, but is also * dependent on the setup and hold timings we calculated earlier, * which gives: * - * NRD_CYCLE =3D max(tRC, NRD_PULSE + NRD_HOLD) - * - * NRD_SETUP is always 0. + * NRD_CYCLE =3D max(tRC, NRD_SETUP + NRD_PULSE + NRD_HOLD) */ ncycles =3D DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps); ncycles =3D max(totalcycles, ncycles); --=20 2.50.1