From nobody Sat Oct 4 03:14:06 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B35D6311586 for ; Thu, 21 Aug 2025 11:47:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755776823; cv=none; b=S+ANVgBvdcCDFSmZX/UxynA+fCNYQNSSqk+k0QOhR8ve5R4ZhcvUEnFh9GXEYOYB//AHzTW20u9W98rH2kFTT3ubp9hQEivR1FR+uiNyE4QebHFu9KdQlH32V6ODJenSPvWERIEqhcYiPd0EhtCXebdearLQ/QP1o2oSe+kF5Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755776823; c=relaxed/simple; bh=b5ab1jehet9PqnPbvotgit7EJJsXSBgrqjKQ7KkFEIE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bos2qoDdz06LJsm6zQXDrLNyUyFQNGEjyOM+9nOiMwbw5TN5sFUYHWB+uWVWqop7quFx4cDSEs1Rnompk92fBixHuISor1sRP/W7AD6v4Wbap+X87qcjVcoOpbkDmU9rg8miOrZfp8ixSMJDduOYvf5qiYYxQPzDstAajKv7Yso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L7wrt5sr; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L7wrt5sr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755776822; x=1787312822; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b5ab1jehet9PqnPbvotgit7EJJsXSBgrqjKQ7KkFEIE=; b=L7wrt5sr6b/bHcxOmrt7pwBremYt31DvaqekO4ixcc3Ei12+IVdcAH/c 7NDACTRY6TIXGET+iRcti1WXPQeK62IK/m4m+FL5WobgvUTGNQdFalZOo 6bCEuJ6gbPVus1X9qhd3iRJ1RK74QFmPECEb2NKc2DSp1+/k0s/lJ0xfG KT8E7syM1ZkpBi/Dy7Afe7iNV2Z5yaglo/sKsuymH2+DXzswXGc2iBDB9 jDKFNmGWeXRw1yvAYf25mQ5r6qNradhnYSSpKepTbRRJ7nV5pR5wpAMyx qD3smpJeID4hhJap94dOLIiVTB8WH7EvjMhDMh/OnXRQLt0Q3Sec2ouds g==; X-CSE-ConnectionGUID: 5QErnEj4RWyCJujW7tttcw== X-CSE-MsgGUID: zd26CInDRViwK5x8tYm0Gg== X-IronPort-AV: E=McAfee;i="6800,10657,11527"; a="57989480" X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="57989480" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:47:02 -0700 X-CSE-ConnectionGUID: AaqxK5ZJQPyRqsxSV8Xfrw== X-CSE-MsgGUID: BLaTMDyWSleG0Ef1CVW2QA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="172613652" Received: from johunt-mobl9.ger.corp.intel.com (HELO fedora) ([10.245.245.201]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:46:59 -0700 From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= To: intel-xe@lists.freedesktop.org Cc: Matthew Brost , =?UTF-8?q?Christian=20K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , Alistair Popple , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] drm/xe: Add fences argument to xe_vm_range_tilemask_tlb_invalidation Date: Thu, 21 Aug 2025 13:46:25 +0200 Message-ID: <20250821114626.89818-6-thomas.hellstrom@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> References: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Brost Introduce a fences argument to xe_vm_range_tilemask_tlb_invalidation, allowing callers to provide fences and defer waiting to a later point. Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_svm.c | 3 ++- drivers/gpu/drm/xe/xe_vm.c | 26 +++++++++++++++++--------- drivers/gpu/drm/xe/xe_vm.h | 6 ++++-- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c index 309bcf8a50dd..5ef673b70575 100644 --- a/drivers/gpu/drm/xe/xe_svm.c +++ b/drivers/gpu/drm/xe/xe_svm.c @@ -226,7 +226,8 @@ static void xe_svm_invalidate_start(struct drm_gpusvm *= gpusvm, =20 xe_device_wmb(xe); =20 - err =3D xe_vm_range_tilemask_tlb_invalidation(vm, adj_start, adj_end, til= e_mask); + err =3D xe_vm_range_tilemask_tlb_invalidation(vm, NULL, adj_start, + adj_end, tile_mask); WARN_ON_ONCE(err); =20 range_notifier_event_end: diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index c86337e08a55..a594be545d81 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -3871,6 +3871,7 @@ void xe_vm_unlock(struct xe_vm *vm) * xe_vm_range_tilemask_tlb_invalidation - Issue a TLB invalidation on thi= s tilemask for an * address range * @vm: The VM + * @fences: Caller provided fences, caller owns waiting if non-NULL * @start: start address * @end: end address * @tile_mask: mask for which gt's issue tlb invalidation @@ -3879,10 +3880,12 @@ void xe_vm_unlock(struct xe_vm *vm) * * Returns 0 for success, negative error code otherwise. */ -int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, u64 start, - u64 end, u8 tile_mask) +int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, + struct xe_gt_tlb_invalidation_fence *fences, + u64 start, u64 end, u8 tile_mask) { struct xe_gt_tlb_invalidation_fence fence[XE_MAX_TILES_PER_DEVICE * XE_MA= X_GT_PER_TILE]; + struct xe_gt_tlb_invalidation_fence *__fence =3D fences ?: fence; struct xe_tile *tile; u32 fence_id =3D 0; u8 id; @@ -3894,37 +3897,41 @@ int xe_vm_range_tilemask_tlb_invalidation(struct xe= _vm *vm, u64 start, for_each_tile(tile, vm->xe, id) { if (tile_mask & BIT(id)) { xe_gt_tlb_invalidation_fence_init(tile->primary_gt, - &fence[fence_id], true); + __fence, true); =20 err =3D xe_gt_tlb_invalidation_range(tile->primary_gt, - &fence[fence_id], + __fence, start, end, vm->usm.asid); if (err) goto wait; ++fence_id; + ++__fence; =20 if (!tile->media_gt) continue; =20 xe_gt_tlb_invalidation_fence_init(tile->media_gt, - &fence[fence_id], true); + __fence, true); =20 err =3D xe_gt_tlb_invalidation_range(tile->media_gt, - &fence[fence_id], + __fence, start, end, vm->usm.asid); if (err) goto wait; ++fence_id; + ++__fence; } } =20 wait: - for (id =3D 0; id < fence_id; ++id) - xe_gt_tlb_invalidation_fence_wait(&fence[id]); + if (!fences) { + for (id =3D 0; id < fence_id; ++id) + xe_gt_tlb_invalidation_fence_wait(&fence[id]); + } =20 return err; } @@ -3983,7 +3990,8 @@ int xe_vm_invalidate_vma(struct xe_vma *vma) =20 xe_device_wmb(xe); =20 - ret =3D xe_vm_range_tilemask_tlb_invalidation(xe_vma_vm(vma), xe_vma_star= t(vma), + ret =3D xe_vm_range_tilemask_tlb_invalidation(xe_vma_vm(vma), NULL, + xe_vma_start(vma), xe_vma_end(vma), tile_mask); =20 /* WRITE_ONCE pairs with READ_ONCE in xe_vm_has_valid_gpu_mapping() */ diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h index 2f213737c7e5..0b08b22e3bb3 100644 --- a/drivers/gpu/drm/xe/xe_vm.h +++ b/drivers/gpu/drm/xe/xe_vm.h @@ -22,6 +22,7 @@ struct dma_fence; =20 struct xe_exec_queue; struct xe_file; +struct xe_gt_tlb_invalidation_fence; struct xe_sync_entry; struct xe_svm_range; struct drm_exec; @@ -228,8 +229,9 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm, struct dma_fence *xe_vm_range_unbind(struct xe_vm *vm, struct xe_svm_range *range); =20 -int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, u64 start, - u64 end, u8 tile_mask); +int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, + struct xe_gt_tlb_invalidation_fence *fences, + u64 start, u64 end, u8 tile_mask); =20 int xe_vm_invalidate_vma(struct xe_vma *vma); =20 --=20 2.50.1