From nobody Sat Oct 4 01:39:03 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 82C2A23D7D1 for ; Thu, 21 Aug 2025 11:46:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755776811; cv=none; b=rwzsUvof4K1U2bYjb3tf2C18l50W+YRJJds95yd1K8BaoL83r3AOdGuhWYICpbkSQxX7v2IzpCrCYcyQ2TuJJ62Q45KLrFxorrSaVZ23QwHIsyRCzc0LKnCMPBBQfH+haiVWfAN2xNtipR5s0v1pB8SJC35jUEt826BGTxWRi98= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755776811; c=relaxed/simple; bh=ul9zx6zgdYUSqlYBtzIUybb4bVdjZ5vOSGPRmGr83Q0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dXmqNgKbmLZZE0WunSf++vF4+Ak/X3eJs7PhcMoZPCLx2yIXzUm5+lcgJ/YmY/ngEFp88p1cL6u0rsLcPH/f2Yu0rcHeHYo3RmvJa12kt/Djqx1szPvSfetFRyUXwC+ZMrZiCjAte6ZHdWvqtT2spUX/hBVdhMNMMzRx4onjNVM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=kUCDk1TB; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="kUCDk1TB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755776810; x=1787312810; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ul9zx6zgdYUSqlYBtzIUybb4bVdjZ5vOSGPRmGr83Q0=; b=kUCDk1TBTUT2QTNqdd55ZvQ8gWH7rljEUhAMV9upLPYiZ//cA6FBTv0o jxyB4/xcKQTGGrLcbPK+hSxWmCo/efQszUhNbFKvG8H0UJEPMFTH5aJme ukJ+nT7xpcgISJoYPt/6LHuajQa3M3NdSsXlLbbhWu5XwaR5Hm0n6yc+i AlaRw3T3Wt+ZpVW3/IR4uiixOK4fvtjj04E3XNqPKPVdGnI14g3PHnVWc bAUvS70GWZOpUG048UMNBydtuyUgBZ4EHv0khct946Ii8YMTtD1hosZAe dPUbG4HSEfnkKYbQUQEocHSSM6Stt2d0M3LEIKjCVIz2dr6W9vX59whcn Q==; X-CSE-ConnectionGUID: FGMPpLk0QDCqm1WJiwCL8Q== X-CSE-MsgGUID: X5unKrJPSw+uJr064R0b1Q== X-IronPort-AV: E=McAfee;i="6800,10657,11527"; a="57989436" X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="57989436" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:46:49 -0700 X-CSE-ConnectionGUID: zuMx8QyhR1eNklrQdYSkXA== X-CSE-MsgGUID: QE3AVlLpR16TWlYwIvGUvg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="172613627" Received: from johunt-mobl9.ger.corp.intel.com (HELO fedora) ([10.245.245.201]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:46:46 -0700 From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= To: intel-xe@lists.freedesktop.org Cc: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , Alistair Popple , dri-devel@lists.freedesktop.org, linux-mm@kvack.org, linux-kernel@vger.kernel.org, Matthew Brost , =?UTF-8?q?Christian=20K=C3=B6nig?= Subject: [PATCH 1/6] mm/mmu_notifier: Allow two-pass struct mmu_interval_notifiers Date: Thu, 21 Aug 2025 13:46:21 +0200 Message-ID: <20250821114626.89818-2-thomas.hellstrom@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> References: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable GPU use-cases for mmu_interval_notifiers with hmm often involve starting a gpu operation and then waiting for it to complete. These operations are typically context preemption or TLB flushing. With single-pass notifiers per GPU this doesn't scale in multi-gpu scenarios. In those scenarios we'd want to first start preemption- or TLB flushing on all GPUs and as a second pass wait for them to complete. One can do this on per-driver basis multiplexing per-driver notifiers but that would mean sharing the notifier "user" lock across all GPUs and that doesn't scale well either, so adding support for multi-pass in the core appears to be the right choice. Implement two-pass capability in the mmu_interval_notifier. Use a linked list for the final passes to minimize the impact for use-cases that don't need the multi-pass functionality by avoiding a second interval tree walk, and to be able to easily pass data between the two passes. v1: - Restrict to two passes (Jason Gunthorpe) - Improve on documentation (Jason Gunthorpe) - Improve on function naming (Alistair Popple) Cc: Jason Gunthorpe Cc: Andrew Morton Cc: Simona Vetter Cc: Dave Airlie Cc: Alistair Popple Cc: Cc: Cc: Signed-off-by: Thomas Hellstr=C3=B6m Reviewed-by: Jason Gunthorpe --- include/linux/mmu_notifier.h | 42 ++++++++++++++++++++++++ mm/mmu_notifier.c | 63 ++++++++++++++++++++++++++++++------ 2 files changed, 96 insertions(+), 9 deletions(-) diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h index d1094c2d5fb6..14cfb3735699 100644 --- a/include/linux/mmu_notifier.h +++ b/include/linux/mmu_notifier.h @@ -233,16 +233,58 @@ struct mmu_notifier { unsigned int users; }; =20 +/** + * struct mmu_interval_notifier_finish - mmu_interval_notifier two-pass ab= straction + * @link: List link for the notifiers pending pass list + * + * Allocate, typically using GFP_NOWAIT in the interval notifier's first p= ass. + * If allocation fails (which is not unlikely under memory pressure), fall= back + * to single-pass operation. Note that with a large number of notifiers + * implementing two passes, allocation with GFP_NOWAIT will become increas= ingly + * likely to fail, so consider implementing a small pool instead of using + * kmalloc() allocations. + * + * If the implementation needs to pass data between the two passes, + * the recommended way is to embed strct mmu_interval_notifier_finish into= a larger + * structure that also contains the data needed to be shared. Keep in mind= that + * a notifier callback can be invoked in parallel, and each invocation nee= ds its + * own struct mmu_interval_notifier_finish. + */ +struct mmu_interval_notifier_finish { + struct list_head link; + /** + * @finish: Driver callback for the finish pass. + * @final: Pointer to the mmu_interval_notifier_finish structure. + * @range: The mmu_notifier_range. + * @cur_seq: The current sequence set by the first pass. + * + * Note that there is no error reporting for additional passes. + */ + void (*finish)(struct mmu_interval_notifier_finish *final, + const struct mmu_notifier_range *range, + unsigned long cur_seq); +}; + /** * struct mmu_interval_notifier_ops * @invalidate: Upon return the caller must stop using any SPTEs within th= is * range. This function can sleep. Return false only if sleep= ing * was required but mmu_notifier_range_blockable(range) is fa= lse. + * @invalidate_start: Similar to @invalidate, but intended for two-pass no= tifier + * callbacks where the callto @invalidate_start is the = first + * pass and any struct mmu_interval_notifier_finish poi= nter + * returned in the @fini parameter describes the final = pass. + * If @fini is %NULL on return, then no final pass will= be + * called. */ struct mmu_interval_notifier_ops { bool (*invalidate)(struct mmu_interval_notifier *interval_sub, const struct mmu_notifier_range *range, unsigned long cur_seq); + bool (*invalidate_start)(struct mmu_interval_notifier *interval_sub, + const struct mmu_notifier_range *range, + unsigned long cur_seq, + struct mmu_interval_notifier_finish **final); }; =20 struct mmu_interval_notifier { diff --git a/mm/mmu_notifier.c b/mm/mmu_notifier.c index 8e0125dc0522..fceadcd8ca24 100644 --- a/mm/mmu_notifier.c +++ b/mm/mmu_notifier.c @@ -260,6 +260,18 @@ mmu_interval_read_begin(struct mmu_interval_notifier *= interval_sub) } EXPORT_SYMBOL_GPL(mmu_interval_read_begin); =20 +static void mn_itree_final_pass(struct list_head *final_passes, + const struct mmu_notifier_range *range, + unsigned long cur_seq) +{ + struct mmu_interval_notifier_finish *f, *next; + + list_for_each_entry_safe(f, next, final_passes, link) { + list_del(&f->link); + f->finish(f, range, cur_seq); + } +} + static void mn_itree_release(struct mmu_notifier_subscriptions *subscripti= ons, struct mm_struct *mm) { @@ -271,6 +283,7 @@ static void mn_itree_release(struct mmu_notifier_subscr= iptions *subscriptions, .end =3D ULONG_MAX, }; struct mmu_interval_notifier *interval_sub; + LIST_HEAD(final_passes); unsigned long cur_seq; bool ret; =20 @@ -278,11 +291,25 @@ static void mn_itree_release(struct mmu_notifier_subs= criptions *subscriptions, mn_itree_inv_start_range(subscriptions, &range, &cur_seq); interval_sub; interval_sub =3D mn_itree_inv_next(interval_sub, &range)) { - ret =3D interval_sub->ops->invalidate(interval_sub, &range, - cur_seq); + if (interval_sub->ops->invalidate_start) { + struct mmu_interval_notifier_finish *final =3D NULL; + + ret =3D interval_sub->ops->invalidate_start(interval_sub, + &range, + cur_seq, + &final); + if (ret && final) + list_add_tail(&final->link, &final_passes); + + } else { + ret =3D interval_sub->ops->invalidate(interval_sub, + &range, + cur_seq); + } WARN_ON(!ret); } =20 + mn_itree_final_pass(&final_passes, &range, cur_seq); mn_itree_inv_end(subscriptions); } =20 @@ -430,7 +457,9 @@ static int mn_itree_invalidate(struct mmu_notifier_subs= criptions *subscriptions, const struct mmu_notifier_range *range) { struct mmu_interval_notifier *interval_sub; + LIST_HEAD(final_passes); unsigned long cur_seq; + int err =3D 0; =20 for (interval_sub =3D mn_itree_inv_start_range(subscriptions, range, &cur_seq); @@ -438,23 +467,39 @@ static int mn_itree_invalidate(struct mmu_notifier_su= bscriptions *subscriptions, interval_sub =3D mn_itree_inv_next(interval_sub, range)) { bool ret; =20 - ret =3D interval_sub->ops->invalidate(interval_sub, range, - cur_seq); + if (interval_sub->ops->invalidate_start) { + struct mmu_interval_notifier_finish *final =3D NULL; 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X-CSE-ConnectionGUID: j1cQZwY+QemP8oV7AuJpag== X-CSE-MsgGUID: p9+VvM/4SqWU9SUEVuqH2Q== X-IronPort-AV: E=McAfee;i="6800,10657,11527"; a="57989447" X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="57989447" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:46:53 -0700 X-CSE-ConnectionGUID: kf1KpAspTQWu/4QcTxvEiA== X-CSE-MsgGUID: eqUmgzk0RWyZZNS4TzRRwQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="172613632" Received: from johunt-mobl9.ger.corp.intel.com (HELO fedora) ([10.245.245.201]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:46:50 -0700 From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= To: intel-xe@lists.freedesktop.org Cc: Matthew Brost , =?UTF-8?q?Christian=20K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , Alistair Popple , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/6] drm/gpusvm, drm/xe: Update GPU SVM / Xe to twopass MMU notifier Date: Thu, 21 Aug 2025 13:46:22 +0200 Message-ID: <20250821114626.89818-3-thomas.hellstrom@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> References: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Brost Update GPU SVM and Xe to use two-pass MMU notifiers, enabling pipelined TLB invalidations across VMs or multiple devices. The driver-side (Xe) implementation is not yet implemented. v1: - Update function naming and comments. Signed-off-by: Matthew Brost --- drivers/gpu/drm/drm_gpusvm.c | 18 +++++++++++------- drivers/gpu/drm/xe/xe_svm.c | 9 +++++---- include/drm/drm_gpusvm.h | 11 +++++++---- 3 files changed, 23 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/drm_gpusvm.c b/drivers/gpu/drm/drm_gpusvm.c index 661306da6b2d..c8d74c728cdd 100644 --- a/drivers/gpu/drm/drm_gpusvm.c +++ b/drivers/gpu/drm/drm_gpusvm.c @@ -374,10 +374,13 @@ notifier_iter_first(struct rb_root_cached *root, unsi= gned long start, (notifier__) =3D (next__), (next__) =3D __drm_gpusvm_notifier_next(n= otifier__)) =20 /** - * drm_gpusvm_notifier_invalidate() - Invalidate a GPU SVM notifier. + * drm_gpusvm_notifier_invalidate_start() - Invalidate a GPU SVM notifier, + * fist pass. + * * @mni: Pointer to the mmu_interval_notifier structure. * @mmu_range: Pointer to the mmu_notifier_range structure. * @cur_seq: Current sequence number. + * @final: First pass of MMU notifier * * This function serves as a generic MMU notifier for GPU SVM. It sets the= MMU * notifier sequence number and calls the driver invalidate vfunc under @@ -386,9 +389,10 @@ notifier_iter_first(struct rb_root_cached *root, unsig= ned long start, * Return: true if the operation succeeds, false otherwise. */ static bool -drm_gpusvm_notifier_invalidate(struct mmu_interval_notifier *mni, - const struct mmu_notifier_range *mmu_range, - unsigned long cur_seq) +drm_gpusvm_notifier_invalidate_start(struct mmu_interval_notifier *mni, + const struct mmu_notifier_range *mmu_range, + unsigned long cur_seq, + struct mmu_interval_notifier_finish **final) { struct drm_gpusvm_notifier *notifier =3D container_of(mni, typeof(*notifier), notifier); @@ -399,7 +403,7 @@ drm_gpusvm_notifier_invalidate(struct mmu_interval_noti= fier *mni, =20 down_write(&gpusvm->notifier_lock); mmu_interval_set_seq(mni, cur_seq); - gpusvm->ops->invalidate(gpusvm, notifier, mmu_range); + gpusvm->ops->invalidate_start(gpusvm, notifier, mmu_range, final); up_write(&gpusvm->notifier_lock); =20 return true; @@ -409,7 +413,7 @@ drm_gpusvm_notifier_invalidate(struct mmu_interval_noti= fier *mni, * drm_gpusvm_notifier_ops - MMU interval notifier operations for GPU SVM */ static const struct mmu_interval_notifier_ops drm_gpusvm_notifier_ops =3D { - .invalidate =3D drm_gpusvm_notifier_invalidate, + .invalidate_start =3D drm_gpusvm_notifier_invalidate_start, }; =20 /** @@ -440,7 +444,7 @@ int drm_gpusvm_init(struct drm_gpusvm *gpusvm, const struct drm_gpusvm_ops *ops, const unsigned long *chunk_sizes, int num_chunks) { - if (!ops->invalidate || !num_chunks) + if (!ops->invalidate_start || !num_chunks) return -EINVAL; =20 gpusvm->name =3D name; diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c index e35c6d4def20..309bcf8a50dd 100644 --- a/drivers/gpu/drm/xe/xe_svm.c +++ b/drivers/gpu/drm/xe/xe_svm.c @@ -171,9 +171,10 @@ xe_svm_range_notifier_event_end(struct xe_vm *vm, stru= ct drm_gpusvm_range *r, mmu_range); } =20 -static void xe_svm_invalidate(struct drm_gpusvm *gpusvm, - struct drm_gpusvm_notifier *notifier, - const struct mmu_notifier_range *mmu_range) +static void xe_svm_invalidate_start(struct drm_gpusvm *gpusvm, + struct drm_gpusvm_notifier *notifier, + const struct mmu_notifier_range *mmu_range, + struct mmu_interval_notifier_finish **final) { struct xe_vm *vm =3D gpusvm_to_vm(gpusvm); struct xe_device *xe =3D vm->xe; @@ -553,7 +554,7 @@ static const struct drm_pagemap_devmem_ops dpagemap_dev= mem_ops =3D { static const struct drm_gpusvm_ops gpusvm_ops =3D { .range_alloc =3D xe_svm_range_alloc, .range_free =3D xe_svm_range_free, - .invalidate =3D xe_svm_invalidate, + .invalidate_start =3D xe_svm_invalidate_start, }; =20 static const unsigned long fault_chunk_sizes[] =3D { diff --git a/include/drm/drm_gpusvm.h b/include/drm/drm_gpusvm.h index 8d613e9b2690..48b90c44849b 100644 --- a/include/drm/drm_gpusvm.h +++ b/include/drm/drm_gpusvm.h @@ -63,17 +63,20 @@ struct drm_gpusvm_ops { void (*range_free)(struct drm_gpusvm_range *range); =20 /** - * @invalidate: Invalidate GPU SVM notifier (required) + * @invalidate_start: Invalidate first pass GPU SVM notifier (required) * @gpusvm: Pointer to the GPU SVM * @notifier: Pointer to the GPU SVM notifier * @mmu_range: Pointer to the mmu_notifier_range structure + * @final: Final pass of MMU notifier, optionally populated by the driver= side + * if a final pass of MMU notifier is desired * * Invalidate the GPU page tables. It can safely walk the notifier range * RB tree/list in this function. Called while holding the notifier lock. */ - void (*invalidate)(struct drm_gpusvm *gpusvm, - struct drm_gpusvm_notifier *notifier, - const struct mmu_notifier_range *mmu_range); + void (*invalidate_start)(struct drm_gpusvm *gpusvm, + struct drm_gpusvm_notifier *notifier, + const struct mmu_notifier_range *mmu_range, + struct mmu_interval_notifier_finish **final); }; =20 /** --=20 2.50.1 From nobody Sat Oct 4 01:39:03 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6F9C286D4C for ; Thu, 21 Aug 2025 11:46:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755776817; cv=none; b=TAHYIZZEZLFa3wz+2GVnb+OUBeIGHMAXn3+A3nwqLA4xYKNDTZrAOuXChQDGtKbZL90y6Mh3gowzuO4OHJx8yq6TeVpscdoPzsH1OYH/NxhPd1I45L5w6ZbRdHAQEs0I+uyqF2MLOzncQ0QR34Yx0mhLCg+JcRALLgbFds1DPKQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755776817; c=relaxed/simple; bh=zG9D5IJGziXZh5X5/ZDBlNBPklZZ3+iRqN2cmyda1XA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=r5zLXgJjPYbogEy2L0fMSoQivStNu03USy0KS+PtgNgdiN77t/EB5Siuwqt4DQWIcbPD7rtr9vuRfc7HggaAziozWtuikuqpaO+HXbHf1FCZf+ygbqf7mimkC4rs7TEcuT1SYkg/RSQ8auXrJEO8hLJJG1iknmhZJ5TQf+AE97s= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=P6p/ayHK; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="P6p/ayHK" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755776816; x=1787312816; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zG9D5IJGziXZh5X5/ZDBlNBPklZZ3+iRqN2cmyda1XA=; b=P6p/ayHKWIOsGsiiZs0/jFO2i9hCmWlVCsaeIntVpBXoa7S3o+a79Zmn 2mJjvtrl560bx2HKyxrFRB40lVhg95KMXQSIgwof4sbPkUG1M95OyujdR 67ltos0SwsFipaU5ysVHlv0eYafPSdpMqImT/JLrtr44NzICKx9G/xJRL v171mt1K+NH4+lKthwBaTgyXTwiT/H+MAKbxbS4grAulke83nTJXRWDAa 7Gw7cII3AUHQik6yNXN4QnE7ep/GcVmh0UAUEN6K4lDQaT4gh1OPrF3+m 27CHbTMYe+GzFVnrQ/r8molb6gAuFk6rQm7Aopuvlr8sJrDa/xgUeBGQl Q==; X-CSE-ConnectionGUID: kpg5WV6rS3iOlspduw2uCw== X-CSE-MsgGUID: CLnuz29XTAWUTXIqPa14Ag== X-IronPort-AV: E=McAfee;i="6800,10657,11527"; a="57989458" X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="57989458" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:46:56 -0700 X-CSE-ConnectionGUID: qdZ++VWhTXucPh8rN3toAg== X-CSE-MsgGUID: 4lMvbybTQVaYaBlBGfqb/w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="172613641" Received: from johunt-mobl9.ger.corp.intel.com (HELO fedora) ([10.245.245.201]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:46:53 -0700 From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= To: intel-xe@lists.freedesktop.org Cc: Matthew Brost , =?UTF-8?q?Christian=20K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , Alistair Popple , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/6] drm/gpusvm: Add drm_gpusvm_in_notifier_* helpers Date: Thu, 21 Aug 2025 13:46:23 +0200 Message-ID: <20250821114626.89818-4-thomas.hellstrom@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> References: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Brost Abstract drm_gpusvm_in_notifier_lock/unlock with helpers. Intended usage is a client side 2nd pass of a MMU notifier. Signed-off-by: Matthew Brost --- include/drm/drm_gpusvm.h | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/include/drm/drm_gpusvm.h b/include/drm/drm_gpusvm.h index 48b90c44849b..eb3f5f9396e2 100644 --- a/include/drm/drm_gpusvm.h +++ b/include/drm/drm_gpusvm.h @@ -313,7 +313,7 @@ void drm_gpusvm_range_set_unmapped(struct drm_gpusvm_ra= nge *range, #endif =20 /** - * drm_gpusvm_notifier_lock() - Lock GPU SVM notifier + * drm_gpusvm_notifier_lock() - Lock GPU SVM notifier, client side * @gpusvm__: Pointer to the GPU SVM structure. * * Abstract client usage GPU SVM notifier lock, take lock @@ -322,7 +322,7 @@ void drm_gpusvm_range_set_unmapped(struct drm_gpusvm_ra= nge *range, down_read(&(gpusvm__)->notifier_lock) =20 /** - * drm_gpusvm_notifier_unlock() - Unlock GPU SVM notifier + * drm_gpusvm_notifier_unlock() - Unlock GPU SVM notifier, client side * @gpusvm__: Pointer to the GPU SVM structure. * * Abstract client usage GPU SVM notifier lock, drop lock @@ -330,6 +330,24 @@ void drm_gpusvm_range_set_unmapped(struct drm_gpusvm_r= ange *range, #define drm_gpusvm_notifier_unlock(gpusvm__) \ up_read(&(gpusvm__)->notifier_lock) =20 +/** + * drm_gpusvm_in_notifier_lock() - Lock GPU SVM notifier, in notifier + * @gpusvm__: Pointer to the GPU SVM structure. + * + * Abstract in notifier (2nd pass) usage GPU SVM notifier lock, take lock + */ +#define drm_gpusvm_in_notifier_lock(gpusvm__) \ + down_write(&(gpusvm__)->notifier_lock) + +/** + * drm_gpusvm_in_notifier_unlock() - Unlock GPU SVM notifier, in notifier + * @gpusvm__: Pointer to the GPU SVM structure. + * + * Abstract in notifier (2nd pass) GPU SVM notifier lock, drop lock + */ +#define drm_gpusvm_in_notifier_unlock(gpusvm__) \ + up_write(&(gpusvm__)->notifier_lock) + /** * drm_gpusvm_range_start() - GPU SVM range start address * @range: Pointer to the GPU SVM range --=20 2.50.1 From nobody Sat Oct 4 01:39:03 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD94A30F53E for ; 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charset="utf-8" From: Matthew Brost Avoids unnecessary waits when the TLB invalidation fence has not been armed, simplifying caller logic in cases where the fence status is uncertain. Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h b/drivers/gpu/drm/= xe/xe_gt_tlb_invalidation.h index f7f0f2eaf4b5..c6d4398d3429 100644 --- a/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h +++ b/drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h @@ -34,7 +34,8 @@ void xe_gt_tlb_invalidation_fence_signal(struct xe_gt_tlb= _invalidation_fence *fe static inline void xe_gt_tlb_invalidation_fence_wait(struct xe_gt_tlb_invalidation_fence *fen= ce) { - dma_fence_wait(&fence->base, false); + if (fence->seqno) + dma_fence_wait(&fence->base, false); } =20 #endif /* _XE_GT_TLB_INVALIDATION_ */ --=20 2.50.1 From nobody Sat Oct 4 01:39:03 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B35D6311586 for ; Thu, 21 Aug 2025 11:47:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.17 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755776823; cv=none; b=S+ANVgBvdcCDFSmZX/UxynA+fCNYQNSSqk+k0QOhR8ve5R4ZhcvUEnFh9GXEYOYB//AHzTW20u9W98rH2kFTT3ubp9hQEivR1FR+uiNyE4QebHFu9KdQlH32V6ODJenSPvWERIEqhcYiPd0EhtCXebdearLQ/QP1o2oSe+kF5Sg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755776823; c=relaxed/simple; bh=b5ab1jehet9PqnPbvotgit7EJJsXSBgrqjKQ7KkFEIE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bos2qoDdz06LJsm6zQXDrLNyUyFQNGEjyOM+9nOiMwbw5TN5sFUYHWB+uWVWqop7quFx4cDSEs1Rnompk92fBixHuISor1sRP/W7AD6v4Wbap+X87qcjVcoOpbkDmU9rg8miOrZfp8ixSMJDduOYvf5qiYYxQPzDstAajKv7Yso= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=L7wrt5sr; arc=none smtp.client-ip=192.198.163.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="L7wrt5sr" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755776822; x=1787312822; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=b5ab1jehet9PqnPbvotgit7EJJsXSBgrqjKQ7KkFEIE=; b=L7wrt5sr6b/bHcxOmrt7pwBremYt31DvaqekO4ixcc3Ei12+IVdcAH/c 7NDACTRY6TIXGET+iRcti1WXPQeK62IK/m4m+FL5WobgvUTGNQdFalZOo 6bCEuJ6gbPVus1X9qhd3iRJ1RK74QFmPECEb2NKc2DSp1+/k0s/lJ0xfG KT8E7syM1ZkpBi/Dy7Afe7iNV2Z5yaglo/sKsuymH2+DXzswXGc2iBDB9 jDKFNmGWeXRw1yvAYf25mQ5r6qNradhnYSSpKepTbRRJ7nV5pR5wpAMyx qD3smpJeID4hhJap94dOLIiVTB8WH7EvjMhDMh/OnXRQLt0Q3Sec2ouds g==; X-CSE-ConnectionGUID: 5QErnEj4RWyCJujW7tttcw== X-CSE-MsgGUID: zd26CInDRViwK5x8tYm0Gg== X-IronPort-AV: E=McAfee;i="6800,10657,11527"; a="57989480" X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="57989480" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa111.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:47:02 -0700 X-CSE-ConnectionGUID: AaqxK5ZJQPyRqsxSV8Xfrw== X-CSE-MsgGUID: BLaTMDyWSleG0Ef1CVW2QA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="172613652" Received: from johunt-mobl9.ger.corp.intel.com (HELO fedora) ([10.245.245.201]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:46:59 -0700 From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= To: intel-xe@lists.freedesktop.org Cc: Matthew Brost , =?UTF-8?q?Christian=20K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , Alistair Popple , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/6] drm/xe: Add fences argument to xe_vm_range_tilemask_tlb_invalidation Date: Thu, 21 Aug 2025 13:46:25 +0200 Message-ID: <20250821114626.89818-6-thomas.hellstrom@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> References: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Brost Introduce a fences argument to xe_vm_range_tilemask_tlb_invalidation, allowing callers to provide fences and defer waiting to a later point. Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_svm.c | 3 ++- drivers/gpu/drm/xe/xe_vm.c | 26 +++++++++++++++++--------- drivers/gpu/drm/xe/xe_vm.h | 6 ++++-- 3 files changed, 23 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c index 309bcf8a50dd..5ef673b70575 100644 --- a/drivers/gpu/drm/xe/xe_svm.c +++ b/drivers/gpu/drm/xe/xe_svm.c @@ -226,7 +226,8 @@ static void xe_svm_invalidate_start(struct drm_gpusvm *= gpusvm, =20 xe_device_wmb(xe); =20 - err =3D xe_vm_range_tilemask_tlb_invalidation(vm, adj_start, adj_end, til= e_mask); + err =3D xe_vm_range_tilemask_tlb_invalidation(vm, NULL, adj_start, + adj_end, tile_mask); WARN_ON_ONCE(err); =20 range_notifier_event_end: diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index c86337e08a55..a594be545d81 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -3871,6 +3871,7 @@ void xe_vm_unlock(struct xe_vm *vm) * xe_vm_range_tilemask_tlb_invalidation - Issue a TLB invalidation on thi= s tilemask for an * address range * @vm: The VM + * @fences: Caller provided fences, caller owns waiting if non-NULL * @start: start address * @end: end address * @tile_mask: mask for which gt's issue tlb invalidation @@ -3879,10 +3880,12 @@ void xe_vm_unlock(struct xe_vm *vm) * * Returns 0 for success, negative error code otherwise. */ -int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, u64 start, - u64 end, u8 tile_mask) +int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, + struct xe_gt_tlb_invalidation_fence *fences, + u64 start, u64 end, u8 tile_mask) { struct xe_gt_tlb_invalidation_fence fence[XE_MAX_TILES_PER_DEVICE * XE_MA= X_GT_PER_TILE]; + struct xe_gt_tlb_invalidation_fence *__fence =3D fences ?: fence; struct xe_tile *tile; u32 fence_id =3D 0; u8 id; @@ -3894,37 +3897,41 @@ int xe_vm_range_tilemask_tlb_invalidation(struct xe= _vm *vm, u64 start, for_each_tile(tile, vm->xe, id) { if (tile_mask & BIT(id)) { xe_gt_tlb_invalidation_fence_init(tile->primary_gt, - &fence[fence_id], true); + __fence, true); =20 err =3D xe_gt_tlb_invalidation_range(tile->primary_gt, - &fence[fence_id], + __fence, start, end, vm->usm.asid); if (err) goto wait; ++fence_id; + ++__fence; =20 if (!tile->media_gt) continue; =20 xe_gt_tlb_invalidation_fence_init(tile->media_gt, - &fence[fence_id], true); + __fence, true); =20 err =3D xe_gt_tlb_invalidation_range(tile->media_gt, - &fence[fence_id], + __fence, start, end, vm->usm.asid); if (err) goto wait; ++fence_id; + ++__fence; } } =20 wait: - for (id =3D 0; id < fence_id; ++id) - xe_gt_tlb_invalidation_fence_wait(&fence[id]); + if (!fences) { + for (id =3D 0; id < fence_id; ++id) + xe_gt_tlb_invalidation_fence_wait(&fence[id]); + } =20 return err; } @@ -3983,7 +3990,8 @@ int xe_vm_invalidate_vma(struct xe_vma *vma) =20 xe_device_wmb(xe); =20 - ret =3D xe_vm_range_tilemask_tlb_invalidation(xe_vma_vm(vma), xe_vma_star= t(vma), + ret =3D xe_vm_range_tilemask_tlb_invalidation(xe_vma_vm(vma), NULL, + xe_vma_start(vma), xe_vma_end(vma), tile_mask); =20 /* WRITE_ONCE pairs with READ_ONCE in xe_vm_has_valid_gpu_mapping() */ diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h index 2f213737c7e5..0b08b22e3bb3 100644 --- a/drivers/gpu/drm/xe/xe_vm.h +++ b/drivers/gpu/drm/xe/xe_vm.h @@ -22,6 +22,7 @@ struct dma_fence; =20 struct xe_exec_queue; struct xe_file; +struct xe_gt_tlb_invalidation_fence; struct xe_sync_entry; struct xe_svm_range; struct drm_exec; @@ -228,8 +229,9 @@ struct dma_fence *xe_vm_range_rebind(struct xe_vm *vm, struct dma_fence *xe_vm_range_unbind(struct xe_vm *vm, struct xe_svm_range *range); =20 -int xe_vm_range_tilemask_tlb_invalidation(struct xe_vm *vm, u64 start, - u64 end, u8 tile_mask); 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d="scan'208";a="172613664" Received: from johunt-mobl9.ger.corp.intel.com (HELO fedora) ([10.245.245.201]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 04:47:02 -0700 From: =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= To: intel-xe@lists.freedesktop.org Cc: Matthew Brost , =?UTF-8?q?Christian=20K=C3=B6nig?= , dri-devel@lists.freedesktop.org, Jason Gunthorpe , Andrew Morton , Simona Vetter , Dave Airlie , Alistair Popple , linux-mm@kvack.org, linux-kernel@vger.kernel.org Subject: [PATCH 6/6] drm/xe: Implement two pass MMU notifiers for SVM Date: Thu, 21 Aug 2025 13:46:26 +0200 Message-ID: <20250821114626.89818-7-thomas.hellstrom@linux.intel.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> References: <20250821114626.89818-1-thomas.hellstrom@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Matthew Brost Implement two-pass MMU notifiers for SVM, enabling multiple VMs or devices with GPU mappings to pipeline costly TLB invalidations by issuing them in the first pass and waiting for completion in the second. v1: - Adjust naming. Signed-off-by: Matthew Brost --- drivers/gpu/drm/xe/xe_svm.c | 73 +++++++++++++++++++++++++++++++------ 1 file changed, 61 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c index 5ef673b70575..a278c9dc5306 100644 --- a/drivers/gpu/drm/xe/xe_svm.c +++ b/drivers/gpu/drm/xe/xe_svm.c @@ -144,15 +144,8 @@ xe_svm_range_notifier_event_begin(struct xe_vm *vm, st= ruct drm_gpusvm_range *r, * invalidations spanning multiple ranges. */ for_each_tile(tile, xe, id) - if (xe_pt_zap_ptes_range(tile, vm, range)) { + if (xe_pt_zap_ptes_range(tile, vm, range)) tile_mask |=3D BIT(id); - /* - * WRITE_ONCE pairs with READ_ONCE in - * xe_vm_has_valid_gpu_mapping() - */ - WRITE_ONCE(range->tile_invalidated, - range->tile_invalidated | BIT(id)); - } =20 return tile_mask; } @@ -161,16 +154,59 @@ static void xe_svm_range_notifier_event_end(struct xe_vm *vm, struct drm_gpusvm_range = *r, const struct mmu_notifier_range *mmu_range) { + struct xe_svm_range *range =3D to_xe_range(r); struct drm_gpusvm_ctx ctx =3D { .in_notifier =3D true, }; =20 xe_svm_assert_in_notifier(vm); =20 + /* + * WRITE_ONCE pairs with READ_ONCE in xe_vm_has_valid_gpu_mapping() + */ + WRITE_ONCE(range->tile_invalidated, range->tile_present); + drm_gpusvm_range_unmap_pages(&vm->svm.gpusvm, r, &ctx); if (!xe_vm_is_closed(vm) && mmu_range->event =3D=3D MMU_NOTIFY_UNMAP) xe_svm_garbage_collector_add_range(vm, to_xe_range(r), mmu_range); } =20 +struct xe_svm_invalidate_finish { + struct drm_gpusvm *gpusvm; + struct drm_gpusvm_notifier *notifier; +#define XE_SVM_INVALIDATE_FENCE_COUNT \ + (XE_MAX_TILES_PER_DEVICE * XE_MAX_GT_PER_TILE) + struct xe_gt_tlb_invalidation_fence fences[XE_SVM_INVALIDATE_FENCE_COUNT]; + struct mmu_interval_notifier_finish f; +}; + +static void +xe_svm_invalidate_finish(struct mmu_interval_notifier_finish *final, + const struct mmu_notifier_range *mmu_range, + unsigned long cur_seq) +{ + struct xe_svm_invalidate_finish *xe_final =3D container_of(final, typeof(= *xe_final), f); + struct drm_gpusvm *gpusvm =3D xe_final->gpusvm; + struct drm_gpusvm_notifier *notifier =3D xe_final->notifier; + struct drm_gpusvm_range *r =3D NULL; + struct xe_vm *vm =3D gpusvm_to_vm(gpusvm); + u64 adj_start =3D mmu_range->start, adj_end =3D mmu_range->end; + int id; + + /* Adjust invalidation to notifier boundaries */ + adj_start =3D max(drm_gpusvm_notifier_start(notifier), adj_start); + adj_end =3D min(drm_gpusvm_notifier_end(notifier), adj_end); + + for (id =3D 0; id < XE_SVM_INVALIDATE_FENCE_COUNT; ++id) + xe_gt_tlb_invalidation_fence_wait(&xe_final->fences[id]); + + drm_gpusvm_in_notifier_lock(gpusvm); + drm_gpusvm_for_each_range(r, notifier, adj_start, adj_end) + xe_svm_range_notifier_event_end(vm, r, mmu_range); + drm_gpusvm_in_notifier_unlock(gpusvm); + + kfree(xe_final); +} + static void xe_svm_invalidate_start(struct drm_gpusvm *gpusvm, struct drm_gpusvm_notifier *notifier, const struct mmu_notifier_range *mmu_range, @@ -179,6 +215,8 @@ static void xe_svm_invalidate_start(struct drm_gpusvm *= gpusvm, struct xe_vm *vm =3D gpusvm_to_vm(gpusvm); struct xe_device *xe =3D vm->xe; struct drm_gpusvm_range *r, *first; + struct xe_svm_invalidate_finish *xe_final =3D NULL; + struct xe_gt_tlb_invalidation_fence *fences =3D NULL; u64 adj_start =3D mmu_range->start, adj_end =3D mmu_range->end; u8 tile_mask =3D 0; long err; @@ -226,14 +264,25 @@ static void xe_svm_invalidate_start(struct drm_gpusvm= *gpusvm, =20 xe_device_wmb(xe); =20 - err =3D xe_vm_range_tilemask_tlb_invalidation(vm, NULL, adj_start, + xe_final =3D kzalloc(sizeof(*xe_final), GFP_NOWAIT); + if (xe_final) { + xe_final->gpusvm =3D gpusvm; + xe_final->notifier =3D notifier; + xe_final->f.finish =3D xe_svm_invalidate_finish; + fences =3D xe_final->fences; + *final =3D &xe_final->f; + } + + err =3D xe_vm_range_tilemask_tlb_invalidation(vm, fences, adj_start, adj_end, tile_mask); WARN_ON_ONCE(err); =20 range_notifier_event_end: - r =3D first; - drm_gpusvm_for_each_range(r, notifier, adj_start, adj_end) - xe_svm_range_notifier_event_end(vm, r, mmu_range); + if (!xe_final) { + r =3D first; + drm_gpusvm_for_each_range(r, notifier, adj_start, adj_end) + xe_svm_range_notifier_event_end(vm, r, mmu_range); + } } =20 static int __xe_svm_garbage_collector(struct xe_vm *vm, --=20 2.50.1