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charset="utf-8" From: Nitin Rawat The current MCQ resource configuration involves multiple resource mappings and dynamic resource allocation. Simplify the resource mapping by directly mapping the single "mcq" resource from device tree to hba->mcq_base instead of mapping multiple separate resources (RES_UFS, RES_MCQ, RES_MCQ_SQD, RES_MCQ_VS). It also uses predefined offsets for MCQ doorbell registers (SQD, CQD, SQIS, CQIS) relative to the MCQ base,providing clearer memory layout clarity. Additionally update vendor-specific register offset UFS_MEM_CQIS_VS offset from 0x8 to 0x4008 to align with the hardware programming guide. The new approach assumes the device tree provides a single "mcq" resource that encompasses the entire MCQ configuration space, making the driver more maintainable and less prone to resource mapping errors. Co-developed-by: Ram Kumar Dwivedi Signed-off-by: Ram Kumar Dwivedi Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 146 +++++++++++++----------------------- drivers/ufs/host/ufs-qcom.h | 22 +++++- 2 files changed, 73 insertions(+), 95 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 9574fdc2bb0f..6c6a385543ef 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1910,116 +1910,73 @@ static void ufs_qcom_config_scaling_param(struct u= fs_hba *hba, hba->clk_scaling.suspend_on_no_request =3D true; } =20 -/* Resources */ -static const struct ufshcd_res_info ufs_res_info[RES_MAX] =3D { - {.name =3D "ufs_mem",}, - {.name =3D "mcq",}, - /* Submission Queue DAO */ - {.name =3D "mcq_sqd",}, - /* Submission Queue Interrupt Status */ - {.name =3D "mcq_sqis",}, - /* Completion Queue DAO */ - {.name =3D "mcq_cqd",}, - /* Completion Queue Interrupt Status */ - {.name =3D "mcq_cqis",}, - /* MCQ vendor specific */ - {.name =3D "mcq_vs",}, -}; - static int ufs_qcom_mcq_config_resource(struct ufs_hba *hba) { struct platform_device *pdev =3D to_platform_device(hba->dev); - struct ufshcd_res_info *res; - struct resource *res_mem, *res_mcq; - int i, ret; - - memcpy(hba->res, ufs_res_info, sizeof(ufs_res_info)); - - for (i =3D 0; i < RES_MAX; i++) { - res =3D &hba->res[i]; - res->resource =3D platform_get_resource_byname(pdev, - IORESOURCE_MEM, - res->name); - if (!res->resource) { - dev_info(hba->dev, "Resource %s not provided\n", res->name); - if (i =3D=3D RES_UFS) - return -ENODEV; - continue; - } else if (i =3D=3D RES_UFS) { - res_mem =3D res->resource; - res->base =3D hba->mmio_base; - continue; - } + struct resource *res; =20 - res->base =3D devm_ioremap_resource(hba->dev, res->resource); - if (IS_ERR(res->base)) { - dev_err(hba->dev, "Failed to map res %s, err=3D%d\n", - res->name, (int)PTR_ERR(res->base)); - ret =3D PTR_ERR(res->base); - res->base =3D NULL; - return ret; - } + /* Map the MCQ configuration region */ + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mcq"); + if (!res) { + dev_err(hba->dev, "MCQ resource not found in device tree\n"); + return -ENODEV; } =20 - /* MCQ resource provided in DT */ - res =3D &hba->res[RES_MCQ]; - /* Bail if MCQ resource is provided */ - if (res->base) - goto out; - - /* Explicitly allocate MCQ resource from ufs_mem */ - res_mcq =3D devm_kzalloc(hba->dev, sizeof(*res_mcq), GFP_KERNEL); - if (!res_mcq) - return -ENOMEM; - - res_mcq->start =3D res_mem->start + - MCQ_SQATTR_OFFSET(hba->mcq_capabilities); - res_mcq->end =3D res_mcq->start + hba->nr_hw_queues * MCQ_QCFG_SIZE - 1; - res_mcq->flags =3D res_mem->flags; - res_mcq->name =3D "mcq"; - - ret =3D insert_resource(&iomem_resource, res_mcq); - if (ret) { - dev_err(hba->dev, "Failed to insert MCQ resource, err=3D%d\n", - ret); - return ret; + hba->mcq_base =3D devm_ioremap_resource(hba->dev, res); + if (IS_ERR(hba->mcq_base)) { + dev_err(hba->dev, "Failed to map MCQ region: %ld\n", + PTR_ERR(hba->mcq_base)); + return PTR_ERR(hba->mcq_base); } =20 - res->base =3D devm_ioremap_resource(hba->dev, res_mcq); - if (IS_ERR(res->base)) { - dev_err(hba->dev, "MCQ registers mapping failed, err=3D%d\n", - (int)PTR_ERR(res->base)); - ret =3D PTR_ERR(res->base); - goto ioremap_err; - } - -out: - hba->mcq_base =3D res->base; return 0; -ioremap_err: - res->base =3D NULL; - remove_resource(res_mcq); - return ret; } =20 static int ufs_qcom_op_runtime_config(struct ufs_hba *hba) { - struct ufshcd_res_info *mem_res, *sqdao_res; struct ufshcd_mcq_opr_info_t *opr; int i; + u32 doorbell_offsets[OPR_MAX]; =20 - mem_res =3D &hba->res[RES_UFS]; - sqdao_res =3D &hba->res[RES_MCQ_SQD]; - - if (!mem_res->base || !sqdao_res->base) + if (!hba->mcq_base) { + dev_err(hba->dev, "MCQ base not mapped\n"); return -EINVAL; + } + + /* + * Configure doorbell address offsets in MCQ configuration registers. + * These values are offsets relative to mmio_base (UFS_HCI_BASE). + * + * Memory Layout: + * - mmio_base =3D UFS_HCI_BASE + * - mcq_base =3D MCQ_CONFIG_BASE =3D mmio_base + (UFS_QCOM_MCQCAP_QCFGP= TR * 0x200) + * - Doorbell registers are at: mmio_base + (UFS_QCOM_MCQCAP_QCFGPTR * 0x= 200) + + * - UFS_QCOM_MCQ_SQD_OFFSET + * - Which is also: mcq_base + UFS_QCOM_MCQ_SQD_OFFSET + */ + + doorbell_offsets[OPR_SQD] =3D UFS_QCOM_SQD_ADDR_OFFSET; + doorbell_offsets[OPR_SQIS] =3D UFS_QCOM_SQIS_ADDR_OFFSET; + doorbell_offsets[OPR_CQD] =3D UFS_QCOM_CQD_ADDR_OFFSET; + doorbell_offsets[OPR_CQIS] =3D UFS_QCOM_CQIS_ADDR_OFFSET; =20 + /* + * Configure MCQ operation registers. + * + * The doorbell registers are physically located within the MCQ region: + * - doorbell_physical_addr =3D mmio_base + doorbell_offset + * - doorbell_physical_addr =3D mcq_base + (doorbell_offset - MCQ_CONFIG_= OFFSET) + */ for (i =3D 0; i < OPR_MAX; i++) { opr =3D &hba->mcq_opr[i]; - opr->offset =3D sqdao_res->resource->start - - mem_res->resource->start + 0x40 * i; - opr->stride =3D 0x100; - opr->base =3D sqdao_res->base + 0x40 * i; + opr->offset =3D doorbell_offsets[i]; /* Offset relative to mmio_base */ + opr->stride =3D UFS_QCOM_MCQ_STRIDE; /* 256 bytes between queues */ + + /* + * Calculate the actual doorbell base address within MCQ region: + * base =3D mcq_base + (doorbell_offset - MCQ_CONFIG_OFFSET) + */ + opr->base =3D hba->mcq_base + (opr->offset - UFS_QCOM_MCQ_CONFIG_OFFSET); } =20 return 0; @@ -2034,12 +1991,13 @@ static int ufs_qcom_get_hba_mac(struct ufs_hba *hba) static int ufs_qcom_get_outstanding_cqs(struct ufs_hba *hba, unsigned long *ocqs) { - struct ufshcd_res_info *mcq_vs_res =3D &hba->res[RES_MCQ_VS]; - - if (!mcq_vs_res->base) + if (!hba->mcq_base) { + dev_err(hba->dev, "MCQ base not mapped\n"); return -EINVAL; + } =20 - *ocqs =3D readl(mcq_vs_res->base + UFS_MEM_CQIS_VS); + /* Read from MCQ vendor-specific register in MCQ region */ + *ocqs =3D readl(hba->mcq_base + UFS_MEM_CQIS_VS); =20 return 0; } diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h index e0e129af7c16..8c2c94390a50 100644 --- a/drivers/ufs/host/ufs-qcom.h +++ b/drivers/ufs/host/ufs-qcom.h @@ -33,6 +33,25 @@ #define DL_VS_CLK_CFG_MASK GENMASK(9, 0) #define DME_VS_CORE_CLK_CTRL_DME_HW_CGC_EN BIT(9) =20 +/* Qualcomm MCQ Configuration */ +#define UFS_QCOM_MCQCAP_QCFGPTR 224 /* 0xE0 in hex */ +#define UFS_QCOM_MCQ_CONFIG_OFFSET (UFS_QCOM_MCQCAP_QCFGPTR * 0x200) /* = 0x1C000 */ + +/* Doorbell offsets within MCQ region (relative to MCQ_CONFIG_BASE) */ +#define UFS_QCOM_MCQ_SQD_OFFSET 0x5000 +#define UFS_QCOM_MCQ_CQD_OFFSET 0x5080 +#define UFS_QCOM_MCQ_SQIS_OFFSET 0x5040 +#define UFS_QCOM_MCQ_CQIS_OFFSET 0x50C0 +#define UFS_QCOM_MCQ_STRIDE 0x100 + +/* Calculated doorbell address offsets (relative to mmio_base) */ +#define UFS_QCOM_SQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM= _MCQ_SQD_OFFSET) +#define UFS_QCOM_CQD_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM= _MCQ_CQD_OFFSET) +#define UFS_QCOM_SQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM= _MCQ_SQIS_OFFSET) +#define UFS_QCOM_CQIS_ADDR_OFFSET (UFS_QCOM_MCQ_CONFIG_OFFSET + UFS_QCOM= _MCQ_CQIS_OFFSET) + +#define REG_UFS_MCQ_STRIDE UFS_QCOM_MCQ_STRIDE + /* QCOM UFS host controller vendor specific registers */ enum { REG_UFS_SYS1CLK_1US =3D 0xC0, @@ -96,7 +115,8 @@ enum { }; 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charset="utf-8" From: Nitin Rawat Refactor MCQ register dump to align with the new resource mapping. As part of refactor, below changes are done: - Update ufs_qcom_dump_regs() function signature to accept direct base address instead of resource ID enum - Modify ufs_qcom_dump_mcq_hci_regs() to use hba->mcq_base and calculated addresses from MCQ operation info - Replace enum ufshcd_res with direct memory-mapped I/O addresses Signed-off-by: Nitin Rawat --- drivers/ufs/host/ufs-qcom.c | 34 +++++++++++++++++++--------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c index 6c6a385543ef..c1915f426ef8 100644 --- a/drivers/ufs/host/ufs-qcom.c +++ b/drivers/ufs/host/ufs-qcom.c @@ -1742,7 +1742,7 @@ static void ufs_qcom_dump_testbus(struct ufs_hba *hba) } =20 static int ufs_qcom_dump_regs(struct ufs_hba *hba, size_t offset, size_t l= en, - const char *prefix, enum ufshcd_res id) + const char *prefix, void __iomem *base) { u32 *regs __free(kfree) =3D NULL; size_t pos; @@ -1755,7 +1755,7 @@ static int ufs_qcom_dump_regs(struct ufs_hba *hba, si= ze_t offset, size_t len, return -ENOMEM; =20 for (pos =3D 0; pos < len; pos +=3D 4) - regs[pos / 4] =3D readl(hba->res[id].base + offset + pos); + regs[pos / 4] =3D readl(base + offset + pos); =20 print_hex_dump(KERN_ERR, prefix, len > 4 ? DUMP_PREFIX_OFFSET : DUMP_PREFIX_NONE, @@ -1766,30 +1766,34 @@ static int ufs_qcom_dump_regs(struct ufs_hba *hba, = size_t offset, size_t len, =20 static void ufs_qcom_dump_mcq_hci_regs(struct ufs_hba *hba) { + struct ufshcd_mcq_opr_info_t *opr =3D &hba->mcq_opr[0]; + void __iomem *mcq_vs_base =3D hba->mcq_base + UFS_MEM_VS_BASE; + struct dump_info { + void __iomem *base; size_t offset; size_t len; const char *prefix; - enum ufshcd_res id; }; =20 struct dump_info mcq_dumps[] =3D { - {0x0, 256 * 4, "MCQ HCI-0 ", RES_MCQ}, - {0x400, 256 * 4, "MCQ HCI-1 ", RES_MCQ}, - {0x0, 5 * 4, "MCQ VS-0 ", RES_MCQ_VS}, - {0x0, 256 * 4, "MCQ SQD-0 ", RES_MCQ_SQD}, - {0x400, 256 * 4, "MCQ SQD-1 ", RES_MCQ_SQD}, - {0x800, 256 * 4, "MCQ SQD-2 ", RES_MCQ_SQD}, - {0xc00, 256 * 4, "MCQ SQD-3 ", RES_MCQ_SQD}, - {0x1000, 256 * 4, "MCQ SQD-4 ", RES_MCQ_SQD}, - {0x1400, 256 * 4, "MCQ SQD-5 ", RES_MCQ_SQD}, - {0x1800, 256 * 4, "MCQ SQD-6 ", RES_MCQ_SQD}, - {0x1c00, 256 * 4, "MCQ SQD-7 ", RES_MCQ_SQD}, + {hba->mcq_base, 0x0, 256 * 4, "MCQ HCI-0 "}, + {hba->mcq_base, 0x400, 256 * 4, "MCQ HCI-1 "}, + {mcq_vs_base, 0x0, 5 * 4, "MCQ VS-0 "}, + {opr->base, 0x0, 256 * 4, "MCQ SQD-0 "}, + {opr->base, 0x400, 256 * 4, "MCQ SQD-1 "}, + {opr->base, 0x800, 256 * 4, "MCQ SQD-2 "}, + {opr->base, 0xc00, 256 * 4, "MCQ SQD-3 "}, + {opr->base, 0x1000, 256 * 4, "MCQ SQD-4 "}, + {opr->base, 0x1400, 256 * 4, "MCQ SQD-5 "}, + {opr->base, 0x1800, 256 * 4, "MCQ SQD-6 "}, + {opr->base, 0x1c00, 256 * 4, "MCQ SQD-7 "}, + }; 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charset="utf-8" From: Nitin Rawat Remove the ufshcd_res_info structure and associated enum ufshcd_res definitions from the UFS host controller header. These were previously used for MCQ resource mapping but are no longer needed following recent refactoring to use direct base addresses instead of multiple separate resource regions Signed-off-by: Nitin Rawat --- include/ufs/ufshcd.h | 25 ------------------------- 1 file changed, 25 deletions(-) diff --git a/include/ufs/ufshcd.h b/include/ufs/ufshcd.h index 1d3943777584..a7bcf7c7a1af 100644 --- a/include/ufs/ufshcd.h +++ b/include/ufs/ufshcd.h @@ -794,30 +794,6 @@ struct ufs_hba_monitor { bool enabled; }; =20 -/** - * struct ufshcd_res_info_t - MCQ related resource regions - * - * @name: resource name - * @resource: pointer to resource region - * @base: register base address - */ -struct ufshcd_res_info { - const char *name; - struct resource *resource; - void __iomem *base; -}; - -enum ufshcd_res { - RES_UFS, - RES_MCQ, - RES_MCQ_SQD, - RES_MCQ_SQIS, - RES_MCQ_CQD, - RES_MCQ_CQIS, - RES_MCQ_VS, - RES_MAX, -}; - /** * struct ufshcd_mcq_opr_info_t - Operation and Runtime registers * @@ -1127,7 +1103,6 @@ struct ufs_hba { bool lsdb_sup; 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charset="utf-8" Enable Multi-Circular Queue (MCQ) support for the UFS host controller on the Qualcomm SM8650 platform by updating the device tree node. This includes adding new register region for MCQ and specifying the MSI parent required for MCQ operation. Signed-off-by: Ram Kumar Dwivedi --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qco= m/sm8650.dtsi index d6794901f06b..18c4ebf3c1a6 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -3950,7 +3950,10 @@ ufs_mem_phy: phy@1d80000 { =20 ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0 0x01d84000 0 0x3000>; + reg =3D <0 0x01d84000 0 0x3000>, + <0 0x1da0000 0 0x15000>; + reg-names =3D "std", + "mcq"; =20 interrupts =3D ; =20 @@ -3988,6 +3991,8 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, =20 iommus =3D <&apps_smmu 0x60 0>; =20 + msi-parent =3D <&gic_its 0x60>; + lanes-per-direction =3D <2>; qcom,ice =3D <&ice>; =20 --=20 2.50.1 From nobody Sat Oct 4 01:47:31 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4E2C431985A; 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charset="utf-8" From: Palash Kambar Enable Multi-Circular Queue (MCQ) support for the UFS host controller on the Qualcomm SM8750 platform by updating the device tree node. This includes adding new register region for MCQ and specifying the MSI parent required for MCQ operation. Signed-off-by: Palash Kambar Signed-off-by: Ram Kumar Dwivedi --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qco= m/sm8750.dtsi index 79ca262f5811..e55edc0a6e6e 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -3329,7 +3329,10 @@ ufs_mem_phy: phy@1d80000 { =20 ufs_mem_hc: ufs@1d84000 { compatible =3D "qcom,sm8750-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; - reg =3D <0x0 0x01d84000 0x0 0x3000>; + reg =3D <0x0 0x01d84000 0x0 0x3000>, + <0x0 0x1da0000 0x0 0x15000>; + reg-names =3D "std", + "mcq"; =20 interrupts =3D ; =20 @@ -3363,11 +3366,12 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, "cpu-ufs"; =20 power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; + required-opps =3D <&rpmhpd_opp_nom>; =20 iommus =3D <&apps_smmu 0x60 0>; dma-coherent; - + msi-parent =3D <&gic_its 0x60>; lanes-per-direction =3D <2>; =20 phys =3D <&ufs_mem_phy>; --=20 2.50.1