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[127.0.0.1]) by director2.derp.mail-out.ovh.net (inspect_sender_mail_agent) with SMTP for ; Thu, 21 Aug 2025 10:19:39 +0000 (UTC) Received: from mta7.priv.ovhmail-u1.ea.mail.ovh.net (unknown [10.110.0.122]) by director2.derp.mail-out.ovh.net (Postfix) with ESMTPS id 4c6zp34tgwz1xnd; Thu, 21 Aug 2025 10:19:39 +0000 (UTC) Received: from orca.pet (unknown [10.1.6.9]) by mta7.priv.ovhmail-u1.ea.mail.ovh.net (Postfix) with ESMTPSA id 8DBF7B832CC; Thu, 21 Aug 2025 10:19:38 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-97G00287c6276b-4378-4784-bda3-8ba47990026a, 684E78C7C579463DAB27E2CA1F9C4E28A39E1181) smtp.auth=marcos@orca.pet X-OVh-ClientIp: 147.156.42.5 From: Marcos Del Sol Vives To: linux-kernel@vger.kernel.org Cc: Marcos Del Sol Vives , Linus Walleij , Bartosz Golaszewski , Michael Walle , Lee Jones , Bjorn Helgaas , linux-gpio@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 1/3] gpio: gpio-regmap: add flags to control some behaviour Date: Thu, 21 Aug 2025 12:18:57 +0200 Message-Id: <20250821101902.626329-2-marcos@orca.pet> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821101902.626329-1-marcos@orca.pet> References: <20250821101902.626329-1-marcos@orca.pet> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 17490573581666178662 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdduiedtleekucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepofgrrhgtohhsucffvghlucfuohhlucggihhvvghsuceomhgrrhgtohhssehorhgtrgdrphgvtheqnecuggftrfgrthhtvghrnhepudffudeutdejudeffeeugeehveevgfefiefgueejueejheevtefgtdffvddukeelnecukfhppeduvdejrddtrddtrddupddugeejrdduheeirdegvddrheenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeduvdejrddtrddtrddupdhmrghilhhfrhhomhepmhgrrhgtohhssehorhgtrgdrphgvthdpnhgspghrtghpthhtohepledprhgtphhtthhopegsrhhglhessghguggvvhdrphhlpdhrtghpthhtohepsghhvghlghgrrghssehgohhoghhlvgdrtghomhdprhgtphhtthhopehlvggvsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehmfigrlhhlvgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhushdrfigrlhhlvghijheslhhinhgrrhhordhorhhgpdhrtghpthhtohepmhgrrhgtohhssehorhgtrgdrphgvthdprhgtphhtthhopehlihhnuhigqdhgphhiohesvhhgvghrrdhkvghrnhgvlhdroh hrghdprhgtphhtthhopehlihhnuhigqdhkvghrnhgvlhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehlihhnuhigqdhptghisehvghgvrhdrkhgvrhhnvghlrdhorhhg DKIM-Signature: a=rsa-sha256; bh=mrCfxy0L2trdWCO+bWDn7qiJXiD9r/vRTGQ9erRpGx0=; c=relaxed/relaxed; d=orca.pet; h=From; s=ovhmo-selector-1; t=1755771580; v=1; b=WR8ZMqS1qLZJ9GzYPWVVG9JGmuEQamJCqa2dJGhKATv0yh/Xd6ilLFcnkE4JLWeYsKiL5D5/ tNln0DbY/EvWmg6gFOOtxUtlp5MfRDEH5j7lFUsjmbnSP3oyAiPv/TLSIe7CnnY/y1QWAihGot6 XqIeS8SuEv1VXJ9Ax2hInfFjFhEXt2Hr63jUZkK//EG/qdOHMw+Eh9Tb8hTgAQp+nDmiepkjnei Bv5+NGEjwFWIZdvWSwnFtpz5V7iYmo7yIGMNtbdvcJbGZZ6z3KKSFTZTMhXVbpId1JTU+nwqBi2 6Hr6ncXPjql0lNqDiyhkDThD9CcFfOY8JfTJS94EG2aXw== Content-Type: text/plain; charset="utf-8" The Vortex86 family of SoCs need the direction set before the value, else writes to the DATA ports are ignored. This commit adds a new "flags" field plus a flag to change the default behaviour, which is to set first the direction and then the value. Signed-off-by: Marcos Del Sol Vives Reviewed-by: Linus Walleij Reviewed-by: Michael Walle --- drivers/gpio/gpio-regmap.c | 17 ++++++++++++++++- include/linux/gpio/regmap.h | 17 +++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c index e8a32dfebdcb..24cefbd57637 100644 --- a/drivers/gpio/gpio-regmap.c +++ b/drivers/gpio/gpio-regmap.c @@ -31,6 +31,7 @@ struct gpio_regmap { unsigned int reg_clr_base; unsigned int reg_dir_in_base; unsigned int reg_dir_out_base; + unsigned int flags; =20 int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, unsigned int offset, unsigned int *reg, @@ -196,7 +197,20 @@ static int gpio_regmap_direction_input(struct gpio_chi= p *chip, static int gpio_regmap_direction_output(struct gpio_chip *chip, unsigned int offset, int value) { - gpio_regmap_set(chip, offset, value); + struct gpio_regmap *gpio =3D gpiochip_get_data(chip); + int ret; + + if (gpio->flags & GPIO_REGMAP_DIR_BEFORE_SET) { + ret =3D gpio_regmap_set_direction(chip, offset, true); + if (ret) + return ret; + + return gpio_regmap_set(chip, offset, value); + } + + ret =3D gpio_regmap_set(chip, offset, value); + if (ret) + return ret; =20 return gpio_regmap_set_direction(chip, offset, true); } @@ -247,6 +261,7 @@ struct gpio_regmap *gpio_regmap_register(const struct g= pio_regmap_config *config gpio->reg_clr_base =3D config->reg_clr_base; gpio->reg_dir_in_base =3D config->reg_dir_in_base; gpio->reg_dir_out_base =3D config->reg_dir_out_base; + gpio->flags =3D config->flags; =20 chip =3D &gpio->gpio_chip; chip->parent =3D config->parent; diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h index c722c67668c6..aea107e71fec 100644 --- a/include/linux/gpio/regmap.h +++ b/include/linux/gpio/regmap.h @@ -12,6 +12,20 @@ struct regmap; #define GPIO_REGMAP_ADDR_ZERO ((unsigned int)(-1)) #define GPIO_REGMAP_ADDR(addr) ((addr) ? : GPIO_REGMAP_ADDR_ZERO) =20 + +/** + * enum gpio_regmap_flags - flags to control GPIO operation + */ +enum gpio_regmap_flags { + /** + * @GPIO_REGMAP_DIR_BEFORE_SET: when setting a pin as an output, set + * its direction before the value. The output value will be undefined + * for a short time which may have unwanted side effects, but some + * hardware requires this. + */ + GPIO_REGMAP_DIR_BEFORE_SET =3D BIT(0), +}; + /** * struct gpio_regmap_config - Description of a generic regmap gpio_chip. * @parent: The parent device @@ -23,6 +37,8 @@ struct regmap; * If not given, the name of the device is used. * @ngpio: (Optional) Number of GPIOs * @names: (Optional) Array of names for gpios + * @flags: (Optional) A bitmask of flags from + * &enum gpio_regmap_flags * @reg_dat_base: (Optional) (in) register base address * @reg_set_base: (Optional) set register base address * @reg_clr_base: (Optional) clear register base address @@ -68,6 +84,7 @@ struct gpio_regmap_config { const char *label; int ngpio; const char *const *names; + unsigned int flags; =20 unsigned int reg_dat_base; unsigned int reg_set_base; --=20 2.34.1 From nobody Sat Oct 4 01:48:19 2025 Received: from smtpout3.mo534.mail-out.ovh.net (smtpout3.mo534.mail-out.ovh.net [51.210.94.142]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C46017263A for ; Thu, 21 Aug 2025 10:19:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=51.210.94.142 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755771589; cv=none; b=WkzSH07NdqwcqJqcf02Dz4I3+G1BvqaXPF7q2quvoeBVGi+wA6eVizWtae0cuP5sTlFELqm6C2AL5y216oVsiKFuOKGBmRM5Q2iu8cAqtKSlRLmK3kFgcij6/6CW93lF5YrX9s7rznyNMhm7lon0ta8B2jwhZiQ6L4aGxAqXLuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755771589; c=relaxed/simple; bh=NqQf9Jc+3SbRrfRkJ4AYKg+XmoSQqCNl3ADyalX/KvQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=lYp6QKsqIHi99MNezb4odmPyBV0KeQHMMUTeS7c2GNazysYXfDWDcfTTLZz83RzQohRbENzBPayi6roAvLEwo+L2PcGGXr13Odwo8VYsosyJhsQWf8WB9QVCXH6Dzq+3Se0bBG2fBrEsCqrJwkRLCF/lGnex0V7SZbJeAAQVL/E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=orca.pet; spf=pass smtp.mailfrom=orca.pet; dkim=pass (2048-bit key) header.d=orca.pet header.i=@orca.pet header.b=BultrdNB; arc=none smtp.client-ip=51.210.94.142 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=orca.pet Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=orca.pet Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=orca.pet header.i=@orca.pet header.b="BultrdNB" Received: from director2.derp.mail-out.ovh.net (director2.derp.mail-out.ovh.net [79.137.60.36]) by mo534.mail-out.ovh.net (Postfix) with ESMTPS id 4c6zp91RMjz6BJy; Thu, 21 Aug 2025 10:19:45 +0000 (UTC) Received: from director2.derp.mail-out.ovh.net (director2.derp.mail-out.ovh.net. [127.0.0.1]) by director2.derp.mail-out.ovh.net (inspect_sender_mail_agent) with SMTP for ; Thu, 21 Aug 2025 10:19:45 +0000 (UTC) Received: from mta7.priv.ovhmail-u1.ea.mail.ovh.net (unknown [10.110.37.222]) by director2.derp.mail-out.ovh.net (Postfix) with ESMTPS id 4c6zp90Qbkz1xnh; Thu, 21 Aug 2025 10:19:45 +0000 (UTC) Received: from orca.pet (unknown [10.1.6.9]) by mta7.priv.ovhmail-u1.ea.mail.ovh.net (Postfix) with ESMTPSA id 07D81B832BF; Thu, 21 Aug 2025 10:19:43 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-97G002b6cf9774-3ea7-46e3-8327-10b8b50bb1ac, 684E78C7C579463DAB27E2CA1F9C4E28A39E1181) smtp.auth=marcos@orca.pet X-OVh-ClientIp: 147.156.42.5 From: Marcos Del Sol Vives To: linux-kernel@vger.kernel.org Cc: Marcos Del Sol Vives , Linus Walleij , Bartosz Golaszewski , Michael Walle , Lee Jones , Bjorn Helgaas , linux-gpio@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 2/3] gpio: vortex: add new GPIO device driver Date: Thu, 21 Aug 2025 12:18:58 +0200 Message-Id: <20250821101902.626329-3-marcos@orca.pet> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821101902.626329-1-marcos@orca.pet> References: <20250821101902.626329-1-marcos@orca.pet> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 17492262431657055846 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdduiedtleekucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepofgrrhgtohhsucffvghlucfuohhlucggihhvvghsuceomhgrrhgtohhssehorhgtrgdrphgvtheqnecuggftrfgrthhtvghrnhepkeevudelhfdvvdekjeehgffhheetjeefhfevgffhfefhgfdvlefgtefhgeduhefgnecuffhomhgrihhnpegumhhprdgtohhmrdhtfienucfkphepuddvjedrtddrtddruddpudegjedrudehiedrgedvrdehnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehinhgvthepuddvjedrtddrtddruddpmhgrihhlfhhrohhmpehmrghrtghoshesohhrtggrrdhpvghtpdhnsggprhgtphhtthhopeelpdhrtghpthhtohepsghrghhlsegsghguvghvrdhplhdprhgtphhtthhopegshhgvlhhgrggrshesghhoohhglhgvrdgtohhmpdhrtghpthhtoheplhgvvgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepmhifrghllhgvsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehlihhnuhhsrdifrghllhgvihhjsehlihhnrghrohdrohhrghdprhgtphhtthhopehmrghrtghoshesohhrtggrrdhpvghtpdhrtghpthhtoheplhhinhhugi dqghhpihhosehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhugidqkhgvrhhnvghlsehvghgvrhdrkhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhugidqphgtihesvhhgvghrrdhkvghrnhgvlhdrohhrgh DKIM-Signature: a=rsa-sha256; bh=JiNSSypzdmcdGwO4MzvY7/7N/cIlsyO551KqNqoZdhU=; c=relaxed/relaxed; d=orca.pet; h=From; s=ovhmo-selector-1; t=1755771585; v=1; b=BultrdNBYhvdi669Qga+DOJa1f8TR4W8fJUcJgoICU0Nozw7GoaGy8p9djdfFhDzInV+Y0bS p777+2mquBuaFC1UUBNeawhFUhaRMOz1Qw/GrWkWqbMhIUp9oELzf1Bfkge92Qrbk3JgfJ5RQNE WwM8p8TaI0qSmsWH58UcbjjYwi8ingC5v+ZxvffJTxWeHTYNW+7VljM/a9MMMNX8jDdwNYQtJKO YUEv/J0k2qTlVtWVCxuSxDwlSEJWJZykMp3RIIbcyC1TF9qxuwDO3DC946Qoeu6C8AeozTNfIRj WAQddxr+dQuijWHywzx7soBj2HmWSnMttaQTA+D/phMkA== Content-Type: text/plain; charset="utf-8" Add a new simple GPIO device driver for Vortex86 lines of SoCs, implemented according to their programming reference manual [1]. This is required for detecting the status of the poweroff button and performing the poweroff sequence on ICOP eBox computers. IRQs are not implemented, as they are only available for ports 0 and 1, none which are accessible on my test machine (an EBOX-3352-GLW). [1]: http://www.dmp.com.tw/tech/DMP_Vortex86_Series_Software_Programming_Referen= ce_091216.pdf Signed-off-by: Marcos Del Sol Vives Reviewed-by: Linus Walleij --- MAINTAINERS | 5 ++ drivers/gpio/Kconfig | 11 ++++ drivers/gpio/Makefile | 1 + drivers/gpio/gpio-vortex.c | 110 +++++++++++++++++++++++++++++++++++++ 4 files changed, 127 insertions(+) create mode 100644 drivers/gpio/gpio-vortex.c diff --git a/MAINTAINERS b/MAINTAINERS index daf520a13bdf..8c3098a39411 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26953,6 +26953,11 @@ VOLTAGE AND CURRENT REGULATOR IRQ HELPERS R: Matti Vaittinen F: drivers/regulator/irq_helpers.c =20 +VORTEX HARDWARE SUPPORT +R: Marcos Del Sol Vives +S: Maintained +F: drivers/gpio/gpio-vortex.c + VRF M: David Ahern L: netdev@vger.kernel.org diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index e43abb322fa6..cd2b1e105908 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -1077,6 +1077,17 @@ config GPIO_TS5500 blocks of the TS-5500: DIO1, DIO2 and the LCD port, and the TS-5600 LCD port. =20 +config GPIO_VORTEX + tristate "Vortex SoC GPIO support" + select REGMAP_MMIO + select GPIO_REGMAP + help + Driver to access the five 8-bit bidirectional GPIO ports present on + all DM&P Vortex SoCs. + + To compile this driver as a module, choose M here: the module will + be called gpio-vortex. + config GPIO_WINBOND tristate "Winbond Super I/O GPIO support" select ISA_BUS_API diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 379f55e9ed1e..7b8626c9bd75 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile @@ -197,6 +197,7 @@ obj-$(CONFIG_GPIO_VIPERBOARD) +=3D gpio-viperboard.o obj-$(CONFIG_GPIO_VIRTUSER) +=3D gpio-virtuser.o obj-$(CONFIG_GPIO_VIRTIO) +=3D gpio-virtio.o obj-$(CONFIG_GPIO_VISCONTI) +=3D gpio-visconti.o +obj-$(CONFIG_GPIO_VORTEX) +=3D gpio-vortex.o obj-$(CONFIG_GPIO_VX855) +=3D gpio-vx855.o obj-$(CONFIG_GPIO_WCD934X) +=3D gpio-wcd934x.o obj-$(CONFIG_GPIO_WHISKEY_COVE) +=3D gpio-wcove.o diff --git a/drivers/gpio/gpio-vortex.c b/drivers/gpio/gpio-vortex.c new file mode 100644 index 000000000000..6fc184942e7f --- /dev/null +++ b/drivers/gpio/gpio-vortex.c @@ -0,0 +1,110 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * GPIO driver for Vortex86 SoCs + * + * Author: Marcos Del Sol Vives + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DAT_RANGE 0 +#define DIR_RANGE 1 + +struct vortex_gpio { + struct regmap_range ranges[2]; + struct regmap_access_table access_table; +}; + +static int vortex_gpio_probe(struct platform_device *pdev) +{ + struct gpio_regmap_config gpiocfg =3D {}; + struct resource *dat_res, *dir_res; + struct device *dev =3D &pdev->dev; + struct regmap_config rmcfg =3D {}; + unsigned long io_start, io_end; + struct vortex_gpio *priv; + struct regmap *map; + void __iomem *regs; + + dat_res =3D platform_get_resource_byname(pdev, IORESOURCE_IO, "dat"); + if (unlikely(!dat_res)) { + dev_err(dev, "failed to get data register\n"); + return -ENODEV; + } + + dir_res =3D platform_get_resource_byname(pdev, IORESOURCE_IO, "dir"); + if (unlikely(!dir_res)) { + dev_err(dev, "failed to get direction register\n"); + return -ENODEV; + } + + if (unlikely(resource_size(dat_res) !=3D resource_size(dir_res))) { + dev_err(dev, "data and direction size mismatch\n"); + return -EINVAL; + } + + priv =3D devm_kzalloc(&pdev->dev, sizeof(struct vortex_gpio), + GFP_KERNEL); + if (unlikely(!priv)) + return -ENOMEM; + pdev->dev.driver_data =3D priv; + + /* Map an I/O window that covers both data and direction */ + io_start =3D min(dat_res->start, dir_res->start); + io_end =3D max(dat_res->end, dir_res->end); + regs =3D devm_ioport_map(dev, io_start, io_end - io_start + 1); + if (unlikely(!regs)) + return -ENOMEM; + + /* Dynamically build access table from gpiocfg */ + priv->ranges[DAT_RANGE].range_min =3D dat_res->start - io_start; + priv->ranges[DAT_RANGE].range_max =3D dat_res->end - io_start; + priv->ranges[DIR_RANGE].range_min =3D dir_res->start - io_start; + priv->ranges[DIR_RANGE].range_max =3D dir_res->end - io_start; + priv->access_table.n_yes_ranges =3D ARRAY_SIZE(priv->ranges); + priv->access_table.yes_ranges =3D priv->ranges; + + rmcfg.reg_bits =3D 8; + rmcfg.val_bits =3D 8; + rmcfg.io_port =3D true; + rmcfg.wr_table =3D &priv->access_table; + rmcfg.rd_table =3D &priv->access_table; + + map =3D devm_regmap_init_mmio(dev, regs, &rmcfg); + if (unlikely(IS_ERR(map))) + return dev_err_probe(dev, PTR_ERR(map), + "Unable to initialize register map\n"); + + gpiocfg.parent =3D dev; + gpiocfg.regmap =3D map; + gpiocfg.ngpio =3D 8 * resource_size(dat_res); + gpiocfg.ngpio_per_reg =3D 8; + gpiocfg.reg_dat_base =3D GPIO_REGMAP_ADDR(priv->ranges[DAT_RANGE].range_m= in); + gpiocfg.reg_set_base =3D GPIO_REGMAP_ADDR(priv->ranges[DAT_RANGE].range_m= in); + gpiocfg.reg_dir_out_base =3D GPIO_REGMAP_ADDR(priv->ranges[DIR_RANGE].ran= ge_min); + gpiocfg.flags =3D GPIO_REGMAP_DIR_BEFORE_SET; + + return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(dev, &gpiocfg)); +} + +static struct platform_driver vortex_gpio_driver =3D { + .driver.name =3D "vortex-gpio", + .probe =3D vortex_gpio_probe, +}; + +module_platform_driver(vortex_gpio_driver); + +MODULE_AUTHOR("Marcos Del Sol Vives "); +MODULE_DESCRIPTION("GPIO driver for Vortex86 SoCs"); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:vortex-gpio"); --=20 2.34.1 From nobody Sat Oct 4 01:48:19 2025 Received: from 9.mo533.mail-out.ovh.net (9.mo533.mail-out.ovh.net [188.165.47.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7F012472B5 for ; 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[127.0.0.1]) by director2.derp.mail-out.ovh.net (inspect_sender_mail_agent) with SMTP for ; Thu, 21 Aug 2025 10:19:50 +0000 (UTC) Received: from mta7.priv.ovhmail-u1.ea.mail.ovh.net (unknown [10.109.254.198]) by director2.derp.mail-out.ovh.net (Postfix) with ESMTPS id 4c6zpG1Z2nz1xnd; Thu, 21 Aug 2025 10:19:50 +0000 (UTC) Received: from orca.pet (unknown [10.1.6.9]) by mta7.priv.ovhmail-u1.ea.mail.ovh.net (Postfix) with ESMTPSA id 23DE0B832BF; Thu, 21 Aug 2025 10:19:49 +0000 (UTC) Authentication-Results: garm.ovh; auth=pass (GARM-97G0025494fe06-fc45-4a28-81e9-f834ace860e6, 684E78C7C579463DAB27E2CA1F9C4E28A39E1181) smtp.auth=marcos@orca.pet X-OVh-ClientIp: 147.156.42.5 From: Marcos Del Sol Vives To: linux-kernel@vger.kernel.org Cc: Marcos Del Sol Vives , Linus Walleij , Bartosz Golaszewski , Michael Walle , Lee Jones , Bjorn Helgaas , linux-gpio@vger.kernel.org, linux-pci@vger.kernel.org Subject: [PATCH v3 3/3] mfd: vortex: implement new driver for Vortex southbridges Date: Thu, 21 Aug 2025 12:18:59 +0200 Message-Id: <20250821101902.626329-4-marcos@orca.pet> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821101902.626329-1-marcos@orca.pet> References: <20250821101902.626329-1-marcos@orca.pet> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Ovh-Tracer-Id: 17493669805666293350 X-VR-SPAMSTATE: OK X-VR-SPAMSCORE: -100 X-VR-SPAMCAUSE: gggruggvucftvghtrhhoucdtuddrgeeffedrtdefgdduiedtleekucetufdoteggodetrfdotffvucfrrhhofhhilhgvmecuqfggjfdpvefjgfevmfevgfenuceurghilhhouhhtmecuhedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujfgurhephffvvefufffkofgjfhgggfestdekredtredttdenucfhrhhomhepofgrrhgtohhsucffvghlucfuohhlucggihhvvghsuceomhgrrhgtohhssehorhgtrgdrphgvtheqnecuggftrfgrthhtvghrnhepudffudeutdejudeffeeugeehveevgfefiefgueejueejheevtefgtdffvddukeelnecukfhppeduvdejrddtrddtrddupddugeejrdduheeirdegvddrheenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepihhnvghtpeduvdejrddtrddtrddupdhmrghilhhfrhhomhepmhgrrhgtohhssehorhgtrgdrphgvthdpnhgspghrtghpthhtohepledprhgtphhtthhopegsrhhglhessghguggvvhdrphhlpdhrtghpthhtohepsghhvghlghgrrghssehgohhoghhlvgdrtghomhdprhgtphhtthhopehlvggvsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehmfigrlhhlvgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhushdrfigrlhhlvghijheslhhinhgrrhhordhorhhgpdhrtghpthhtohepmhgrrhgtohhssehorhgtrgdrphgvthdprhgtphhtthhopehlihhnuhigqdhgphhiohesvhhgvghrrdhkvghrnhgvlhdroh hrghdprhgtphhtthhopehlihhnuhigqdhkvghrnhgvlhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehlihhnuhigqdhptghisehvghgvrhdrkhgvrhhnvghlrdhorhhg DKIM-Signature: a=rsa-sha256; bh=X/42sBBdS5U7O2cvVD41aAwhluwIH1nuwQLgzreoPFM=; c=relaxed/relaxed; d=orca.pet; h=From; s=ovhmo-selector-1; t=1755771590; v=1; b=Xaev/zgvZj+ULtrtrlK/R/tTC2D6mgvOYWpZjKg5b5JK6xFzDWKLG7oR3Rd1GNcubedOEan7 HHVCVqJDniLBJwdte3hq66CsyHSvmFz1LKUfA3c0VKfhrhhIWUEZjFT+XiobJof9VtH4GhbVYnM 0gJGfB/K9NtSQD3DriVbiMfQy1rV4cnxgiHoZPW1/jo2kwcF7fhuZj0A4I+6otH+m/WQSu36Cie qAJmT5jjy/JVEh3Yf5doDe5BLx+oQSWzC92g4CnjYqubROTgyw9CVQADkf5YpC5RAIJcb68ufI4 ypLjuExxIYxw+Rkpgfdbd/vfJhjbmTDHHtfYOq1PHAT5Q== Content-Type: text/plain; charset="utf-8" This new driver loads resources related to southbridges available in DM&P Vortex devices, currently only the GPIO pins. Signed-off-by: Marcos Del Sol Vives --- MAINTAINERS | 1 + drivers/mfd/Kconfig | 9 +++++ drivers/mfd/Makefile | 1 + drivers/mfd/vortex-sb.c | 81 +++++++++++++++++++++++++++++++++++++++++ include/linux/pci_ids.h | 1 + 5 files changed, 93 insertions(+) create mode 100644 drivers/mfd/vortex-sb.c diff --git a/MAINTAINERS b/MAINTAINERS index 8c3098a39411..bc0c541309dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26957,6 +26957,7 @@ VORTEX HARDWARE SUPPORT R: Marcos Del Sol Vives S: Maintained F: drivers/gpio/gpio-vortex.c +F: drivers/mfd/vortex-sb.c =20 VRF M: David Ahern diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 425c5fba6cb1..fe54bb22687d 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -2008,6 +2008,15 @@ config MFD_VX855 VIA VX855/VX875 south bridge. You will need to enable the vx855_spi and/or vx855_gpio drivers for this to do anything useful. =20 +config MFD_VORTEX_SB + tristate "Vortex southbridge" + select MFD_CORE + depends on PCI + help + Say yes here if you want to have support for the southbridge + present on Vortex SoCs. You will need to enable the vortex-gpio + driver for this to do anything useful. + config MFD_ARIZONA select REGMAP select REGMAP_IRQ diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index f7bdedd5a66d..2504ba311f1a 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -202,6 +202,7 @@ obj-$(CONFIG_MFD_JANZ_CMODIO) +=3D janz-cmodio.o obj-$(CONFIG_MFD_TPS6586X) +=3D tps6586x.o obj-$(CONFIG_MFD_VX855) +=3D vx855.o obj-$(CONFIG_MFD_WL1273_CORE) +=3D wl1273-core.o +obj-$(CONFIG_MFD_VORTEX_SB) +=3D vortex-sb.o =20 si476x-core-y :=3D si476x-cmd.o si476x-prop.o si476x-i2c.o obj-$(CONFIG_MFD_SI476X_CORE) +=3D si476x-core.o diff --git a/drivers/mfd/vortex-sb.c b/drivers/mfd/vortex-sb.c new file mode 100644 index 000000000000..ef9bbe2d3870 --- /dev/null +++ b/drivers/mfd/vortex-sb.c @@ -0,0 +1,81 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * MFD southbridge driver for Vortex SoCs + * + * Author: Marcos Del Sol Vives + * + * Based on the RDC321x MFD driver by Florian Fainelli and Bernhard Loos + */ + +#include +#include +#include +#include +#include + +static const struct resource vortex_gpio_resources[] =3D { + { + .name =3D "dat", + .start =3D 0x78, + .end =3D 0x7C, + .flags =3D IORESOURCE_IO, + }, { + .name =3D "dir", + .start =3D 0x98, + .end =3D 0x9C, + .flags =3D IORESOURCE_IO, + } +}; + +static const struct mfd_cell vortex_sb_cells[] =3D { + { + .name =3D "vortex-gpio", + .resources =3D vortex_gpio_resources, + .num_resources =3D ARRAY_SIZE(vortex_gpio_resources), + }, +}; + +static int vortex_sb_probe(struct pci_dev *pdev, + const struct pci_device_id *ent) +{ + int err; + + /* + * In the Vortex86DX3, the southbridge appears twice (on both 00:07.0 + * and 00:07.1). Register only once for .0. + * + * Other Vortex boards (eg Vortex86MX+) have the southbridge exposed + * only once, also at 00:07.0. + */ + if (PCI_FUNC(pdev->devfn) !=3D 0) + return -ENODEV; + + err =3D pci_enable_device(pdev); + if (err) { + dev_err(&pdev->dev, "failed to enable device\n"); + return err; + } + + return devm_mfd_add_devices(&pdev->dev, -1, + vortex_sb_cells, + ARRAY_SIZE(vortex_sb_cells), + NULL, 0, NULL); +} + +static const struct pci_device_id vortex_sb_table[] =3D { + { PCI_DEVICE(PCI_VENDOR_ID_RDC, PCI_DEVICE_ID_RDC_R6035) }, + {} +}; +MODULE_DEVICE_TABLE(pci, vortex_sb_table); + +static struct pci_driver vortex_sb_driver =3D { + .name =3D "vortex-sb", + .id_table =3D vortex_sb_table, + .probe =3D vortex_sb_probe, +}; + +module_pci_driver(vortex_sb_driver); + +MODULE_AUTHOR("Marcos Del Sol Vives "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Vortex MFD southbridge driver"); diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 92ffc4373f6d..2ff8a593ef72 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2412,6 +2412,7 @@ #define PCI_VENDOR_ID_RDC 0x17f3 #define PCI_DEVICE_ID_RDC_R6020 0x6020 #define PCI_DEVICE_ID_RDC_R6030 0x6030 +#define PCI_DEVICE_ID_RDC_R6035 0x6035 #define PCI_DEVICE_ID_RDC_R6040 0x6040 #define PCI_DEVICE_ID_RDC_R6060 0x6060 #define PCI_DEVICE_ID_RDC_R6061 0x6061 --=20 2.34.1