From nobody Sat Oct 4 01:47:32 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0C332E9EA3 for ; Thu, 21 Aug 2025 07:28:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.34 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755761298; cv=none; b=js3GeuKXYbkWJpCQpQ7oouLrzkDFzg3FvbEYQoha8ELmu9Fdz1u/VEpWFoSmRFEeG7NcQELUozQGl6Pxmdy8rgwetjtKbAcCe938Dg2csSZZpQrOxu2UqnomEo1G1jgKauDB/NgK1jShCa3rfK6Y8aYIQmNRCNE6T2ATm03VkPI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755761298; c=relaxed/simple; bh=88Lt4aP+ewswjg17OSpE6y4lwdUPoRldgDkV/MhYvKY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:MIME-Version: Content-Type:References; b=rzGGHtMsxeFC/gt2zRMjo7YvEKGvyCl86YGtID2G846YN/J9iVvsFoPfRRTBHkgyHg+NVdq6JlQdr1v3aoo8z+Jy922Z+oW9/Ko/XdC19by9ti/JQM+O2+7lhSy/MFA7k/n4iba3ekowgp9S66CBeF4jn4NtwIfWmE5RALpVgqE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com; spf=pass smtp.mailfrom=samsung.com; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b=llwLGrfw; arc=none smtp.client-ip=203.254.224.34 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=samsung.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=samsung.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=samsung.com header.i=@samsung.com header.b="llwLGrfw" Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout4.samsung.com (KnoxPortal) with ESMTP id 20250821072807epoutp043279c7937ab8fcae61cec95a3b93c1b6~dt5aaNXZu1937419374epoutp043 for ; Thu, 21 Aug 2025 07:28:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout4.samsung.com 20250821072807epoutp043279c7937ab8fcae61cec95a3b93c1b6~dt5aaNXZu1937419374epoutp043 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1755761287; bh=/UZny0nmt2vMBkU2e/gpL3R9Mx0QIOy020xV8xd0zVI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=llwLGrfwDTxzOdI6xv87THuL6s+Ai4wIhJVXMcxuIgyvn0EebpKYTatCaiU9DadyG xoya5nNwPpLx9kOAlNItiWWJv+/SueYuQM2nqNKZ9thxf1YSDVEl+a2GLOvXUTqv8U EnQENjv7UVs8G1qWynk1Q/5Hx9cctospbohtiyk4= Received: from epsnrtp02.localdomain (unknown [182.195.42.154]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPS id 20250821072806epcas5p1d013b385ea49b1be2cf7989d44b02877~dt5ZhYmnr0117501175epcas5p18; Thu, 21 Aug 2025 07:28:06 +0000 (GMT) Received: from epcas5p4.samsung.com (unknown [182.195.38.93]) by epsnrtp02.localdomain (Postfix) with ESMTP id 4c6w051R5Sz2SSKf; Thu, 21 Aug 2025 07:28:05 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250821072804epcas5p20256917f2a714f4946139174f8fc20f5~dt5X2Ebhl0550705507epcas5p29; Thu, 21 Aug 2025 07:28:04 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250821072801epsmtip13370fcd9bc3653a3c56cfcf69abae89a~dt5UxkUol0593105931epsmtip1E; Thu, 21 Aug 2025 07:28:01 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, johan@kernel.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v6 1/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 HS phy compatible Date: Thu, 21 Aug 2025 13:06:58 +0530 Message-Id: <20250821073703.2498302-2-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821073703.2498302-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250821072804epcas5p20256917f2a714f4946139174f8fc20f5 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250821072804epcas5p20256917f2a714f4946139174f8fc20f5 References: <20250821073703.2498302-1-pritam.sutar@samsung.com> This SoC has USB2.0 phy and supports only UTMI+ interface. This phy requires two clocks, named as "phy" and "ref". The required supplies for this phy are vdd075_usb20(0.75v), vdd18_usb20(1.8v), vdd33_usb20(3.3v). Add a dedicated compatible string for USB HS phy found in this SoC. Signed-off-by: Pritam Manohar Sutar --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index e906403208c0..e238fd0c9f6c 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-phy =20 clocks: minItems: 1 @@ -110,6 +111,12 @@ properties: vddh-usbdp-supply: description: VDDh power supply for the USB DP phy. =20 + dvdd075-usb20-supply: + description: 0.75V power supply for the USB 2.0 phy. + + vdd18-usb20-supply: + description: 1.8V power supply for the USB 2.0 phy. + required: - compatible - clocks @@ -219,6 +226,7 @@ allOf: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-phy then: properties: clocks: @@ -235,6 +243,22 @@ allOf: =20 reg-names: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-usbdrd-phy + then: + required: + - dvdd075-usb20-supply + - vdd18-usb20-supply + - vdd33-usb20-supply + + else: + properties: + dvdd075-usb20-supply: false + vdd18-usb20-supply: false =20 unevaluatedProperties: false =20 --=20 2.34.1 From nobody Sat Oct 4 01:47:32 2025 Received: from mailout1.samsung.com (mailout1.samsung.com [203.254.224.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 32D1E2E92CF for ; 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Thu, 21 Aug 2025 07:28:09 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.90]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4c6w086fLJz3hhT4; Thu, 21 Aug 2025 07:28:08 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250821072807epcas5p2d8e2e2508cf2318b640a45cc54ee3afa~dt5bIDoZO0277302773epcas5p2m; Thu, 21 Aug 2025 07:28:07 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250821072804epsmtip192a00e93d94b944d2f98b0a9eca6c620~dt5YFaiiq0622006220epsmtip1X; Thu, 21 Aug 2025 07:28:04 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, johan@kernel.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v6 2/6] phy: exynos5-usbdrd: support HS phy for ExynosAutov920 Date: Thu, 21 Aug 2025 13:06:59 +0530 Message-Id: <20250821073703.2498302-3-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821073703.2498302-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250821072807epcas5p2d8e2e2508cf2318b640a45cc54ee3afa X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250821072807epcas5p2d8e2e2508cf2318b640a45cc54ee3afa References: <20250821073703.2498302-1-pritam.sutar@samsung.com> Enable UTMI+ phy support for this SoC which is very similar to what the existing Exynos850 supports. Add required change in phy driver to support HS phy for this SoC. Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 123 ++++++++++++++++++++ include/linux/soc/samsung/exynos-regs-pmu.h | 2 + 2 files changed, 125 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index a88ba95bdc8f..b238d14e2f4a 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -2054,6 +2054,126 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static int exynosautov920_usbdrd_phy_init(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + /* Bypass PHY isol */ + inst->phy_cfg->phy_isol(inst, false); + + /* UTMI or PIPE3 specific init */ + inst->phy_cfg->phy_init(phy_drd); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + exynos850_usbdrd_phy_exit(phy); + + /* enable PHY isol */ + inst->phy_cfg->phy_isol(inst, true); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + +static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret; + + dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + if (ret) + return ret; + + /* Enable supply */ + ret =3D regulator_bulk_enable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + if (ret) { + dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); + goto fail_supply; + } + + return 0; + +fail_supply: + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return ret; +} + +static int exynosautov920_usbdrd_phy_power_off(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + + dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); + + /* Disable supply */ + regulator_bulk_disable(phy_drd->drv_data->n_regulators, + phy_drd->regulators); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, + phy_drd->core_clks); + + return 0; +} + +static const char * const exynosautov920_usb20_regulators[] =3D { + "dvdd075-usb20", "vdd18-usb20", "vdd33-usb20", +}; + +static const struct phy_ops exynosautov920_usbdrd_phy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct exynos5_usbdrd_phy_config phy_cfg_exynosautov920[] =3D= { + { + .id =3D EXYNOS5_DRDPHY_UTMI, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynos850_usbdrd_utmi_init, + }, +}; + +static const struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_phy = =3D { + .phy_cfg =3D phy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usbdrd_phy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_usb20_regulators, + .n_regulators =3D ARRAY_SIZE(exynosautov920_usb20_regulators), +}; + static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] =3D { { .id =3D EXYNOS5_DRDPHY_UTMI, @@ -2260,6 +2380,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usbdrd-phy", + .data =3D &exynosautov920_usbdrd_phy }, { }, }; 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Thu, 21 Aug 2025 07:28:11 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250821072808epsmtip146a924be7482a7eabe6e861e42181b6e~dt5bXKxno0625606256epsmtip1c; Thu, 21 Aug 2025 07:28:08 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, johan@kernel.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v6 3/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo hsphy Date: Thu, 21 Aug 2025 13:07:00 +0530 Message-Id: <20250821073703.2498302-4-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821073703.2498302-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250821072811epcas5p39b60f480203e26e99dec09321951d4ea X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250821072811epcas5p39b60f480203e26e99dec09321951d4ea References: <20250821073703.2498302-1-pritam.sutar@samsung.com> This phy only supports USB2.0 HS(480Mbps), FS(12Mbps) and LS(1.5Mbps) data rates. It requires two clocks, named as "phy" and "ref". The required supplies for this phy, named as vdd075_usb20(0.75v), vdd18_usb20(1.8v), vdd33_usb20(3.3v). Add schema for combo hsphy found on this SoC. Signed-off-by: Pritam Manohar Sutar --- .../devicetree/bindings/phy/samsung,usb3-drd-phy.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index e238fd0c9f6c..f0cfca5736b8 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy =20 clocks: @@ -226,6 +227,7 @@ allOf: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: properties: @@ -248,6 +250,7 @@ allOf: compatible: contains: enum: + - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: required: --=20 2.34.1 From nobody Sat Oct 4 01:47:32 2025 Received: from mailout3.samsung.com (mailout3.samsung.com [203.254.224.33]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C95D22E9ED0 for ; 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Thu, 21 Aug 2025 07:28:16 +0000 (GMT) Received: from epcas5p1.samsung.com (unknown [182.195.38.95]) by epsnrtp03.localdomain (Postfix) with ESMTP id 4c6w0H3nGLz3hhTH; Thu, 21 Aug 2025 07:28:15 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20250821072814epcas5p2814d441d6ed81acc86f6c5b449bd0b4d~dt5hpBY_h0789307893epcas5p2y; Thu, 21 Aug 2025 07:28:14 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250821072811epsmtip13e31addd7ac1b0a0af7cd8eab691b0c8~dt5enId4W0622806228epsmtip1o; Thu, 21 Aug 2025 07:28:11 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, johan@kernel.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v6 4/6] phy: exynos5-usbdrd: support HS combo phy for ExynosAutov920 Date: Thu, 21 Aug 2025 13:07:01 +0530 Message-Id: <20250821073703.2498302-5-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821073703.2498302-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250821072814epcas5p2814d441d6ed81acc86f6c5b449bd0b4d X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250821072814epcas5p2814d441d6ed81acc86f6c5b449bd0b4d References: <20250821073703.2498302-1-pritam.sutar@samsung.com> Support UTMI+ combo phy for this SoC which is somewhat simmilar to what the existing Exynos850 support does. The difference is that some register offsets and bit fields are defferent from Exynos850. Add required change in phy driver to support combo HS phy for this SoC. Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 211 +++++++++++++++++++++++ 1 file changed, 211 insertions(+) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index b238d14e2f4a..32178c5c120d 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -41,6 +41,13 @@ #define EXYNOS2200_CLKRST_LINK_PCLK_SEL BIT(1) =20 #define EXYNOS2200_DRD_UTMI 0x10 + +/* ExynosAutov920 bits */ +#define UTMICTL_FORCE_UTMI_SUSPEND BIT(13) +#define UTMICTL_FORCE_UTMI_SLEEP BIT(12) +#define UTMICTL_FORCE_DPPULLDOWN BIT(9) +#define UTMICTL_FORCE_DMPULLDOWN BIT(8) + #define EXYNOS2200_UTMI_FORCE_VBUSVALID BIT(1) #define EXYNOS2200_UTMI_FORCE_BVALID BIT(0) =20 @@ -250,6 +257,22 @@ #define EXYNOS850_DRD_HSP_TEST 0x5c #define HSP_TEST_SIDDQ BIT(24) =20 +#define EXYNOSAUTOV920_DRD_HSP_CLKRST 0x100 +#define HSPCLKRST_PHY20_SW_PORTRESET BIT(3) +#define HSPCLKRST_PHY20_SW_POR BIT(1) +#define HSPCLKRST_PHY20_SW_POR_SEL BIT(0) + +#define EXYNOSAUTOV920_DRD_HSPCTL 0x104 +#define HSPCTRL_VBUSVLDEXTSEL BIT(13) +#define HSPCTRL_VBUSVLDEXT BIT(12) +#define HSPCTRL_EN_UTMISUSPEND BIT(9) +#define HSPCTRL_COMMONONN BIT(8) + +#define EXYNOSAUTOV920_DRD_HSP_TEST 0x10c + +#define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 +#define HSPPLLTUNE_FSEL GENMASK(18, 16) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2054,6 +2077,140 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static void +exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* + * Disable HWACG (hardware auto clock gating control). This + * forces QACTIVE signal in Q-Channel interface to HIGH level, + * to make sure the PHY clock is not gated by the hardware. + */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D LINKCTRL_FORCE_QACT; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* De-assert link reset */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg &=3D ~CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); + + /* Set PHY POR High */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + reg |=3D HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_POR_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + + /* Enable UTMI+ */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg &=3D ~(UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP | + UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN); + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + /* set phy clock & control HS phy */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + reg |=3D HSPCTRL_EN_UTMISUSPEND | HSPCTRL_COMMONONN; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + + fsleep(100); + + /* Set VBUS Valid and DP-Pull up control by VBUS pad usage */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D FIELD_PREP_CONST(LINKCTRL_BUS_FILTER_BYPASS, 0xf); + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg |=3D EXYNOS2200_UTMI_FORCE_VBUSVALID | EXYNOS2200_UTMI_FORCE_BVALID; + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + reg |=3D HSPCTRL_VBUSVLDEXTSEL | HSPCTRL_VBUSVLDEXT; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPCTL); + + /* Setting FSEL for refference clock */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE); + reg &=3D ~HSPPLLTUNE_FSEL; + + switch (phy_drd->extrefclk) { + case EXYNOS5_FSEL_50MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 7); + break; + case EXYNOS5_FSEL_26MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 6); + break; + case EXYNOS5_FSEL_24MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 2); + break; + case EXYNOS5_FSEL_20MHZ: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 1); + break; + case EXYNOS5_FSEL_19MHZ2: + reg |=3D FIELD_PREP(HSPPLLTUNE_FSEL, 0); + break; + default: + dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", + phy_drd->extrefclk); + break; + } + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSPPLLTUNE); + + /* Enable PHY Power Mode */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + reg &=3D ~HSP_TEST_SIDDQ; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + + /* before POR low, 10us delay is needed to Finish PHY reset */ + fsleep(10); + + /* Set PHY POR Low */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + reg |=3D HSPCLKRST_PHY20_SW_POR_SEL; + reg &=3D ~(HSPCLKRST_PHY20_SW_POR | HSPCLKRST_PHY20_SW_PORTRESET); + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_CLKRST); + + /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ + fsleep(75); + + /* force pipe3 signal for link */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg |=3D LINKCTRL_FORCE_PIPE_EN; + reg &=3D ~LINKCTRL_FORCE_PHYSTATUS; + reg |=3D LINKCTRL_FORCE_RXELECIDLE; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); +} + +static void +exynosautov920_usbdrd_hsphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + u32 reg; + void __iomem *reg_phy =3D phy_drd->reg_phy; + + /* set phy clock & control HS phy */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_UTMI); + reg |=3D UTMICTL_FORCE_UTMI_SUSPEND | UTMICTL_FORCE_UTMI_SLEEP; + reg &=3D ~(UTMICTL_FORCE_DPPULLDOWN | UTMICTL_FORCE_DMPULLDOWN); + writel(reg, reg_phy + EXYNOS2200_DRD_UTMI); + + /* Disable PHY Power Mode */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + reg |=3D HSP_TEST_SIDDQ; + writel(reg, reg_phy + EXYNOSAUTOV920_DRD_HSP_TEST); + + /* clear force q-channel */ + reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); + reg &=3D ~LINKCTRL_FORCE_QACT; + writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* link sw reset is need for USB_DP/DM high-z in host mode */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |=3D CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); + fsleep(10); + reg &=3D ~CLKRST_LINK_SW_RST; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); +} + static int exynosautov920_usbdrd_phy_init(struct phy *phy) { struct phy_usb_instance *inst =3D phy_get_drvdata(phy); @@ -2095,6 +2252,27 @@ static int exynosautov920_usbdrd_phy_exit(struct phy= *phy) return 0; } =20 +static int exynosautov920_usbdrd_combo_phy_exit(struct phy *phy) +{ + struct phy_usb_instance *inst =3D phy_get_drvdata(phy); + struct exynos5_usbdrd_phy *phy_drd =3D to_usbdrd_phy(inst); + int ret =3D 0; + + ret =3D clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); + if (ret) + return ret; + + if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) + exynosautov920_usbdrd_hsphy_disable(phy_drd); + + /* enable PHY isol */ + inst->phy_cfg->phy_isol(inst, true); + + clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); + + return 0; +} + static int exynosautov920_usbdrd_phy_power_on(struct phy *phy) { struct phy_usb_instance *inst =3D phy_get_drvdata(phy); @@ -2146,6 +2324,36 @@ static const char * const exynosautov920_usb20_regul= ators[] =3D { "dvdd075-usb20", "vdd18-usb20", "vdd33-usb20", }; =20 +static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_combo_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const struct +exynos5_usbdrd_phy_config usbdrd_hsphy_cfg_exynosautov920[] =3D { + { + .id =3D EXYNOS5_DRDPHY_UTMI, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynosautov920_usbdrd_utmi_init, + }, +}; + +static const +struct exynos5_usbdrd_phy_drvdata exynosautov920_usbdrd_combo_hsphy =3D { + .phy_cfg =3D usbdrd_hsphy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usbdrd_combo_hsphy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB20, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_usb20_regulators, + .n_regulators =3D ARRAY_SIZE(exynosautov920_usb20_regulators), +}; + static const struct phy_ops exynosautov920_usbdrd_phy_ops =3D { .init =3D exynosautov920_usbdrd_phy_init, .exit =3D exynosautov920_usbdrd_phy_exit, @@ -2380,6 +2588,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usbdrd-combo-hsphy", + .data =3D &exynosautov920_usbdrd_combo_hsphy }, { .compatible =3D "samsung,exynosautov920-usbdrd-phy", .data =3D &exynosautov920_usbdrd_phy --=20 2.34.1 From nobody Sat Oct 4 01:47:32 2025 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9EC1E2EA486 for ; Thu, 21 Aug 2025 07:28:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=203.254.224.25 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; 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Thu, 21 Aug 2025 07:28:20 +0000 (GMT) Received: from epcas5p3.samsung.com (unknown [182.195.38.94]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4c6w0M1SmBz6B9mF; Thu, 21 Aug 2025 07:28:19 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250821072818epcas5p1763afdfb7f0b4cf48a98d9c4e6eca055~dt5k5IxOg0472004720epcas5p1u; Thu, 21 Aug 2025 07:28:18 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250821072815epsmtip14ad9e3879f13ec088a32dcaab8c76f77~dt5h4Cuyt0624006240epsmtip1k; Thu, 21 Aug 2025 07:28:15 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, johan@kernel.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v6 5/6] dt-bindings: phy: samsung,usb3-drd-phy: add ExynosAutov920 combo ssphy Date: Thu, 21 Aug 2025 13:07:02 +0530 Message-Id: <20250821073703.2498302-6-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821073703.2498302-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250821072818epcas5p1763afdfb7f0b4cf48a98d9c4e6eca055 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250821072818epcas5p1763afdfb7f0b4cf48a98d9c4e6eca055 References: <20250821073703.2498302-1-pritam.sutar@samsung.com> This phy supports USB3.1 SSP+(10Gbps) protocol and is backwards compatible to the USB3.0 SS(5Gbps). It requires two clocks, named "phy" and "ref". The required supplies for USB3.1 are named as vdd075_usb30(0.75v), vdd18_usb30(1.8v). Add schemas for combo ssphy found on this SoC. Signed-off-by: Pritam Manohar Sutar --- .../bindings/phy/samsung,usb3-drd-phy.yaml | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yam= l b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml index f0cfca5736b8..96e5bbb2e42c 100644 --- a/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml +++ b/Documentation/devicetree/bindings/phy/samsung,usb3-drd-phy.yaml @@ -34,6 +34,7 @@ properties: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usb31drd-combo-ssphy - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy =20 @@ -118,6 +119,12 @@ properties: vdd18-usb20-supply: description: 1.8V power supply for the USB 2.0 phy. =20 + dvdd075-usb30-supply: + description: 0.75V power supply for the USB 3.0 phy. + + vdd18-usb30-supply: + description: 1.8V power supply for the USB 3.0 phy. + required: - compatible - clocks @@ -227,6 +234,7 @@ allOf: - samsung,exynos7870-usbdrd-phy - samsung,exynos850-usbdrd-phy - samsung,exynos990-usbdrd-phy + - samsung,exynosautov920-usb31drd-combo-ssphy - samsung,exynosautov920-usbdrd-combo-hsphy - samsung,exynosautov920-usbdrd-phy then: @@ -262,6 +270,21 @@ allOf: properties: dvdd075-usb20-supply: false vdd18-usb20-supply: false + - if: + properties: + compatible: + contains: + enum: + - samsung,exynosautov920-usb31drd-combo-ssphy + then: + required: + - dvdd075-usb30-supply + - vdd18-usb30-supply + + else: + properties: + dvdd075-usb30-supply: false + vdd18-usb30-supply: false =20 unevaluatedProperties: false =20 --=20 2.34.1 From nobody Sat Oct 4 01:47:32 2025 Received: from mailout4.samsung.com (mailout4.samsung.com [203.254.224.34]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9B382EA73E for ; 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Thu, 21 Aug 2025 07:28:23 +0000 (GMT) Received: from epcas5p2.samsung.com (unknown [182.195.38.86]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4c6w0Q4nDLz6B9m7; Thu, 21 Aug 2025 07:28:22 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p1.samsung.com (KnoxPortal) with ESMTPA id 20250821072821epcas5p10ab75c76b70687d7b13b6593b771fdad~dt5oKJtDV0472404724epcas5p1K; Thu, 21 Aug 2025 07:28:21 +0000 (GMT) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250821072818epsmtip1f6a47d58a64e70c415cabfd0d60e2976~dt5lIX5gr0547905479epsmtip1F; Thu, 21 Aug 2025 07:28:18 +0000 (GMT) From: Pritam Manohar Sutar To: vkoul@kernel.org, kishon@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, alim.akhtar@samsung.com, andre.draszik@linaro.org, peter.griffin@linaro.org, kauschluss@disroot.org, ivo.ivanov.ivanov1@gmail.com, igor.belwon@mentallysanemainliners.org, johan@kernel.org, m.szyprowski@samsung.com, s.nawrocki@samsung.com, pritam.sutar@samsung.com Cc: linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, rosa.pila@samsung.com, dev.tailor@samsung.com, faraz.ata@samsung.com, muhammed.ali@samsung.com, selvarasu.g@samsung.com Subject: [PATCH v6 6/6] phy: exynos5-usbdrd: support SS combo phy for ExynosAutov920 Date: Thu, 21 Aug 2025 13:07:03 +0530 Message-Id: <20250821073703.2498302-7-pritam.sutar@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821073703.2498302-1-pritam.sutar@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CMS-MailID: 20250821072821epcas5p10ab75c76b70687d7b13b6593b771fdad X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250821072821epcas5p10ab75c76b70687d7b13b6593b771fdad References: <20250821073703.2498302-1-pritam.sutar@samsung.com> Add required change in phy driver to support combo SS phy for this SoC. Signed-off-by: Pritam Manohar Sutar --- drivers/phy/samsung/phy-exynos5-usbdrd.c | 325 +++++++++++++++++++- include/linux/soc/samsung/exynos-regs-pmu.h | 1 + 2 files changed, 322 insertions(+), 4 deletions(-) diff --git a/drivers/phy/samsung/phy-exynos5-usbdrd.c b/drivers/phy/samsung= /phy-exynos5-usbdrd.c index 32178c5c120d..e0e90f614121 100644 --- a/drivers/phy/samsung/phy-exynos5-usbdrd.c +++ b/drivers/phy/samsung/phy-exynos5-usbdrd.c @@ -273,6 +273,36 @@ #define EXYNOSAUTOV920_DRD_HSPPLLTUNE 0x110 #define HSPPLLTUNE_FSEL GENMASK(18, 16) =20 +/* ExynosAutov920 phy usb31drd port reg */ +#define EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL 0x000 +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN BIT(5) +#define PHY_RST_CTRL_PIPE_LANE0_RESET_N BIT(4) +#define PHY_RST_CTRL_PHY_RESET_OVRD_EN BIT(1) +#define PHY_RST_CTRL_PHY_RESET BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0 0x0004 +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR GENMASK(31, 16) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK BIT(8) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK BIT(4) +#define PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL BIT(0) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1 0x0008 + +#define EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2 0x000c +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN BIT(0) +#define PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA GENMASK(31, 16) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0 0x100 +#define PHY_CONFIG0_PHY0_PMA_PWR_STABLE BIT(14) +#define PHY_CONFIG0_PHY0_PCS_PWR_STABLE BIT(13) +#define PHY_CONFIG0_PHY0_ANA_PWR_EN BIT(1) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7 0x11c +#define PHY_CONFIG7_PHY_TEST_POWERDOWN BIT(24) + +#define EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4 0x110 +#define PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN BIT(2) + /* Exynos9 - GS101 */ #define EXYNOS850_DRD_SECPMACTL 0x48 #define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) @@ -2077,6 +2107,251 @@ static const struct exynos5_usbdrd_phy_drvdata exyn= os990_usbdrd_phy =3D { .n_regulators =3D ARRAY_SIZE(exynos5_regulator_names), }; =20 +static void +exynosautov920_usb31drd_cr_clk(struct exynos5_usbdrd_phy *phy_drd, bool hi= gh) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if (high) + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + else + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + fsleep(1); +} + +static void +exynosautov920_usb31drd_port_phy_ready(struct exynos5_usbdrd_phy *phy_drd) +{ + struct device *dev =3D phy_drd->dev; + void __iomem *reg_phy =3D phy_drd->reg_phy; + static const unsigned int timeout_us =3D 20000; + static const unsigned int sleep_us =3D 40; + u32 reg; + int err; + + /* Clear cr_para_con */ + reg &=3D ~(PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR); + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON1); + writel(0x0, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * The maximum time from phy reset de-assertion to de-assertion of + * tx/rx_ack can be as high as 5ms in fast simulation mode. + * Time to phy ready is < 20ms + */ + err =3D readl_poll_timeout(reg_phy + + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0, + reg, !(reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK), + sleep_us, timeout_us); + if (err) + dev_err(dev, "timed out waiting for rx/tx_ack: %#.8x\n", reg); + + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); +} + +static void +exynosautov920_usb31drd_cr_write(struct exynos5_usbdrd_phy *phy_drd, + u16 addr, u16 data) +{ + struct device *dev =3D phy_drd->dev; + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 cnt =3D 0; + u32 reg; + + /* Pre Clocking */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg |=3D PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx clks must be available prior to assertion of tx req. + * tx pstate p2 to p0 transition directly is not permitted. + * tx clk ready must be asserted synchronously on tx clk prior + * to internal transmit clk alignment sequence in the phy + * when entering from p2 to p1 to p0. + */ + do { + exynosautov920_usb31drd_cr_clk(phy_drd, true); + exynosautov920_usb31drd_cr_clk(phy_drd, false); + cnt++; + } while (cnt < 15); + + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* + * tx data path is active when tx lane is in p0 state + * and tx data en asserted. enable cr_para_wr_en. + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + reg &=3D ~PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA; + reg |=3D FIELD_PREP(PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_DATA, data) | + PHY_CR_PARA_CON2_PHY0_CR_PARA_WR_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON2); + + /* write addr */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + reg &=3D ~PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR; + reg |=3D FIELD_PREP(PHY_CR_PARA_CON0_PHY0_CR_PARA_ADDR, addr) | + PHY_CR_PARA_CON0_PHY0_CR_PARA_CLK | + PHY_CR_PARA_CON0_PHY0_CR_PARA_SEL; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + + /* check cr_para_ack*/ + cnt =3D 0; + do { + /* + * data symbols are captured by phy on rising edge of the + * tx_clk when tx data enabled. + * completion of the write cycle is acknowledged by assertion + * of the cr_para_ack. + */ + exynosautov920_usb31drd_cr_clk(phy_drd, true); + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CR_PARA_CON0); + if ((reg & PHY_CR_PARA_CON0_PHY0_CR_PARA_ACK)) + break; + + exynosautov920_usb31drd_cr_clk(phy_drd, false); + + /* + * wait for minimum of 10 cr_para_clk cycles after phy reset + * is negated, before accessing control regs to allow for + * internal resets. + */ + cnt++; + } while (cnt < 10); + + if (cnt < 10) + exynosautov920_usb31drd_cr_clk(phy_drd, false); +} + +static void +exynosautov920_usb31drd_phy_reset(struct exynos5_usbdrd_phy *phy_drd, int = val) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg &=3D ~PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg |=3D PHY_RST_CTRL_PHY_RESET; + else + reg &=3D ~PHY_RST_CTRL_PHY_RESET; + + reg |=3D PHY_RST_CTRL_PHY_RESET_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_lane0_reset(struct exynos5_usbdrd_phy *phy_drd, in= t val) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + reg |=3D PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); + if (val) + reg &=3D ~PHY_RST_CTRL_PIPE_LANE0_RESET_N; + else + reg |=3D PHY_RST_CTRL_PIPE_LANE0_RESET_N; + + reg &=3D ~PHY_RST_CTRL_PIPE_LANE0_RESET_N_OVRD_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_RST_CTRL); +} + +static void +exynosautov920_usb31drd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* + * Phy and Pipe Lane reset assert. + * assert reset (phy_reset =3D 1). + * The lane-ack outputs are asserted during reset (tx_ack =3D rx_ack =3D = 1) + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + + /* + * ANA Power En, PCS & PMA PWR Stable Set + * ramp-up power suppiles + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + reg |=3D PHY_CONFIG0_PHY0_ANA_PWR_EN | PHY_CONFIG0_PHY0_PCS_PWR_STABLE | + PHY_CONFIG0_PHY0_PMA_PWR_STABLE; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG0); + + fsleep(10); + + /* + * phy is not functional in test_powerdown mode, test_powerdown to be + * de-asserted for normal operation + */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg &=3D ~PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + + /* + * phy reset signal be asserted for minimum 10us after power + * supplies are ramped-up + */ + fsleep(10); + + /* + * Phy and Pipe Lane reset assert de-assert + */ + exynosautov920_usb31drd_phy_reset(phy_drd, 0); + exynosautov920_usb31drd_lane0_reset(phy_drd, 0); + + /* Pipe_rx0_sris_mode_en =3D 1 */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + reg |=3D PHY_CONFIG4_PIPE_RX0_SRIS_MODE_EN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG4); + + /* + * wait for lane ack outputs to de-assert (tx_ack =3D rx_ack =3D 0) + * Exit from the reset state is indicated by de-assertion of *_ack + */ + exynosautov920_usb31drd_port_phy_ready(phy_drd); + + /* override values for level settings */ + exynosautov920_usb31drd_cr_write(phy_drd, 0x22, 0x00F5); +} + +static void +exynosautov920_usb31drd_ssphy_disable(struct exynos5_usbdrd_phy *phy_drd) +{ + void __iomem *reg_phy =3D phy_drd->reg_phy; + u32 reg; + + /* 1. Assert reset (phy_reset =3D 1) */ + exynosautov920_usb31drd_lane0_reset(phy_drd, 1); + exynosautov920_usb31drd_phy_reset(phy_drd, 1); + + /* phy test power down */ + reg =3D readl(reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); + reg |=3D PHY_CONFIG7_PHY_TEST_POWERDOWN; + writel(reg, reg_phy + EXYNOSAUTOV920_USB31DRD_PHY_CONFIG7); +} + static void exynosautov920_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) { @@ -2172,12 +2447,15 @@ exynosautov920_usbdrd_utmi_init(struct exynos5_usbd= rd_phy *phy_drd) /* after POR low and delay 75us, PHYCLOCK is guaranteed. */ fsleep(75); =20 - /* force pipe3 signal for link */ + /* Disable forcing pipe interface */ reg =3D readl(reg_phy + EXYNOS850_DRD_LINKCTRL); - reg |=3D LINKCTRL_FORCE_PIPE_EN; - reg &=3D ~LINKCTRL_FORCE_PHYSTATUS; - reg |=3D LINKCTRL_FORCE_RXELECIDLE; + reg &=3D ~LINKCTRL_FORCE_PIPE_EN; writel(reg, reg_phy + EXYNOS850_DRD_LINKCTRL); + + /* Pclk to pipe_clk */ + reg =3D readl(reg_phy + EXYNOS2200_DRD_CLKRST); + reg |=3D EXYNOS2200_CLKRST_LINK_PCLK_SEL; + writel(reg, reg_phy + EXYNOS2200_DRD_CLKRST); } =20 static void @@ -2264,6 +2542,8 @@ static int exynosautov920_usbdrd_combo_phy_exit(struc= t phy *phy) =20 if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_UTMI) exynosautov920_usbdrd_hsphy_disable(phy_drd); + else if (inst->phy_cfg->id =3D=3D EXYNOS5_DRDPHY_PIPE3) + exynosautov920_usb31drd_ssphy_disable(phy_drd); =20 /* enable PHY isol */ inst->phy_cfg->phy_isol(inst, true); @@ -2320,10 +2600,44 @@ static int exynosautov920_usbdrd_phy_power_off(stru= ct phy *phy) return 0; } =20 +static const char * const exynosautov920_usb30_regulators[] =3D { + "dvdd075-usb30", "vdd18-usb30", +}; + static const char * const exynosautov920_usb20_regulators[] =3D { "dvdd075-usb20", "vdd18-usb20", "vdd33-usb20", }; =20 +static const struct +exynos5_usbdrd_phy_config usb31drd_phy_cfg_exynosautov920[] =3D { + { + .id =3D EXYNOS5_DRDPHY_PIPE3, + .phy_isol =3D exynos5_usbdrd_phy_isol, + .phy_init =3D exynosautov920_usb31drd_pipe3_init, + }, +}; + +static const struct phy_ops exynosautov920_usb31drd_combo_ssphy_ops =3D { + .init =3D exynosautov920_usbdrd_phy_init, + .exit =3D exynosautov920_usbdrd_combo_phy_exit, + .power_on =3D exynosautov920_usbdrd_phy_power_on, + .power_off =3D exynosautov920_usbdrd_phy_power_off, + .owner =3D THIS_MODULE, +}; + +static const +struct exynos5_usbdrd_phy_drvdata exynosautov920_usb31drd_combo_ssphy =3D { + .phy_cfg =3D usb31drd_phy_cfg_exynosautov920, + .phy_ops =3D &exynosautov920_usb31drd_combo_ssphy_ops, + .pmu_offset_usbdrd0_phy =3D EXYNOSAUTOV920_PHY_CTRL_USB31, + .clk_names =3D exynos5_clk_names, + .n_clks =3D ARRAY_SIZE(exynos5_clk_names), + .core_clk_names =3D exynos5_core_clk_names, + .n_core_clks =3D ARRAY_SIZE(exynos5_core_clk_names), + .regulator_names =3D exynosautov920_usb30_regulators, + .n_regulators =3D ARRAY_SIZE(exynosautov920_usb30_regulators), +}; + static const struct phy_ops exynosautov920_usbdrd_combo_hsphy_ops =3D { .init =3D exynosautov920_usbdrd_phy_init, .exit =3D exynosautov920_usbdrd_combo_phy_exit, @@ -2588,6 +2902,9 @@ static const struct of_device_id exynos5_usbdrd_phy_o= f_match[] =3D { }, { .compatible =3D "samsung,exynos990-usbdrd-phy", .data =3D &exynos990_usbdrd_phy + }, { + .compatible =3D "samsung,exynosautov920-usb31drd-combo-ssphy", + .data =3D &exynosautov920_usb31drd_combo_ssphy }, { .compatible =3D "samsung,exynosautov920-usbdrd-combo-hsphy", .data =3D &exynosautov920_usbdrd_combo_hsphy diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/so= c/samsung/exynos-regs-pmu.h index 4923f9be3d1f..f96c773b85c9 100644 --- a/include/linux/soc/samsung/exynos-regs-pmu.h +++ b/include/linux/soc/samsung/exynos-regs-pmu.h @@ -690,4 +690,5 @@ =20 /* exynosautov920 */ #define EXYNOSAUTOV920_PHY_CTRL_USB20 (0x0710) +#define EXYNOSAUTOV920_PHY_CTRL_USB31 (0x0714) #endif /* __LINUX_SOC_EXYNOS_REGS_PMU_H */ --=20 2.34.1