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Darwish" , K Prateek Nayak Subject: [PATCH 2/2] x86/cpu/cacheinfo: Simplify cacheinfo_amd_init_llc_id() using _cpuid4_info Date: Thu, 21 Aug 2025 05:19:10 +0000 Message-ID: <20250821051910.7351-3-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250821051910.7351-1-kprateek.nayak@amd.com> References: <20250821051910.7351-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044FC:EE_|CH8PR12MB9838:EE_ X-MS-Office365-Filtering-Correlation-Id: 83aed064-bfb1-4f3a-bf8c-08dde07267a9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|376014|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?8a+FeRYwSiDojuXjwfYWsufTZtsriwbdeNj6JrtccH8JFbl2dZSu4QgSuVp0?= =?us-ascii?Q?JwedN3ca91NNmU+7QJTxkEAa+9CDq5FM5kQEzo+qE6MqY3XgObWPjFAxzI5Z?= =?us-ascii?Q?K7uAjO4sjPflc1adhLmA11axyiMZJ3WrnkPEV3D2gmJL3cxBAw43wZ/XwEDD?= =?us-ascii?Q?p8ysa6ps3wa80KzqvntWWSxRzbE01OwLanYBOOJxgub9H9N5f/plt3Oi/LA7?= =?us-ascii?Q?loS3OyqbWVW3+sPrVXo0LeN5CXgNokTfOGXKvBjPkZIqCTIfO/2qSjx3Sh7W?= =?us-ascii?Q?cJ60JdjTw44PcFYXh+7kAA1EtXtRYvQxZaySKbukBl/Q77psC27XR9C+1fXI?= =?us-ascii?Q?Sr3xs6R3kdk/A5Vu6xYaWqnoOIzMS5+KL5jJRi59HrpOabw7XlRYQjPmzHfj?= =?us-ascii?Q?fIWkRSuTDkICt614JnzsqvAbf4IE+2Sze+F/R0pvt0mFGp8ckEK8ZrVpraAl?= =?us-ascii?Q?YwVf4KHEhum/hbSr081/L2bN0rt9PjWFrXTpLGiY06Kj22z/Ly4bM7IiK5dq?= =?us-ascii?Q?nSCVaBmuv5YSCxwBeTvr+5V2F+MPPSeGYVgHVzzAEdIG1uob15PlrJnUqNrA?= =?us-ascii?Q?3N81xSPcWyZUP0fHNWQpquxoT+gyEf1x9D5zIsKTq6ulnAPmilRJZNmXDJJt?= =?us-ascii?Q?7KI+3uXgsAVi3oF19pyKz+tYncC8bWesU5WmEQJEgbH3a55eTrmGspaEfrsn?= =?us-ascii?Q?ukJVgd3taYkGW5IPDsqRey4aC9diWzsYtSKhz/0QcrzcDMNTbZ1RFCHAfNyO?= =?us-ascii?Q?A7G0OgyoIbB9428wl8TqnpfiownEi2ZrkNHYnaMUcEXGuX78Xz5ezUQE7MRF?= =?us-ascii?Q?x7x2sfyqi854XAVeA9lr0uLfi0wYRvjJ+mfKC0oxxx00AzpAhRv8bPlI8zJR?= =?us-ascii?Q?FVOcVabYcu/VE1ACWFheDcgsZhnyOd5mZIwtjSJrtbVhpTIi4Ofn55Qk8Bd1?= =?us-ascii?Q?bBoK27La2xWsorO3Dn/izT13UBaeawtSrn1Zl30DTMKoi4uWN0/KBg8HhSO4?= =?us-ascii?Q?qthRZCSD13+NFapFdGnQu3W+9payLKYdVVP8YoiMew294CYZh2q23vh2LibW?= =?us-ascii?Q?OyLHoPtvFcJ8DzHW3zB/7ZlDodGO6xOUv1f9I6OD6XAxwDDR0k6jbjfK0O+y?= =?us-ascii?Q?tLxEknQm5oFjPHuktuv8o9elIavBt8IpZoseIAM4LecInTly0yUMifeIIo5i?= =?us-ascii?Q?D3FsvhyHShbx2G0HuO4nHrrvlHpLkAlwi8HVJdB4v97WIVSNCZvcJbjSG4S5?= =?us-ascii?Q?nhVUnWNrmr5CLb9JY+U51x/+qp5skTFISXHnpS67M5pSjx/QUuv3EtGoGxYS?= =?us-ascii?Q?GB3h6onioq3WrDYAsa9y3R3Lahrl+4Lm51RS9hGjOassl/gbD/qn6uO9I5ip?= =?us-ascii?Q?sP/v8matxgf0SeiHKd0FG7YF8+jDpQqaUWTpEw5VmWm0suS5hm3jyPmvMbY4?= =?us-ascii?Q?Ql8ZL+of/SrqPEk4Oz8ZhGrc3wE+5QXAlMmeeAqrt878JkPN3Bo+WKXglEsh?= =?us-ascii?Q?0H2/7dhZvDVJS20zs+wE3y4Jb7MA1gn7afAt?= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(376014)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2025 05:20:12.5202 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83aed064-bfb1-4f3a-bf8c-08dde07267a9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044FC.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH8PR12MB9838 Content-Type: text/plain; charset="utf-8" "_cpuid4_info" struct has the same layout as the CPUID leaf 0x8000001d. Use the encoded definition and amd_fill_cpuid4_info(), get_cache_id() helpers instead of open coding masks and shifts to calculate the llc_id. cacheinfo_amd_init_llc_id() is only called on AMD systems that support X86_FEATURE_TOPOEXT and amd_fill_cpuid4_info() uses the information from CPUID leaf 0x8000001d on all these systems which is consistent with the current open coded implementation. No functional changes intended. Signed-off-by: K Prateek Nayak --- arch/x86/kernel/cpu/cacheinfo.c | 44 ++++++++++++++------------------- 1 file changed, 18 insertions(+), 26 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index e7b10a612c6f..f4fbca6030ad 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -289,6 +289,21 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c) return i; } =20 +/* + * The max shared threads number comes from CPUID(0x4) EAX[25-14] with inp= ut + * ECX as cache index. Then right shift apicid by the number's order to get + * cache id for this cache node. + */ +static unsigned int get_cache_id(u32 apicid, struct _cpuid4_info *id4) +{ + unsigned long num_threads_sharing; + int index_msb; + + num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; + index_msb =3D get_count_order(num_threads_sharing); + return apicid >> index_msb; +} + /* * AMD/Hygon CPUs may have multiple LLCs if L3 caches exist. */ @@ -312,18 +327,11 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c,= u16 die_id) * Newer families: LLC ID is calculated from the number * of threads sharing the L3 cache. */ - u32 eax, ebx, ecx, edx, num_sharing_cache =3D 0; u32 llc_index =3D find_num_cache_leaves(c) - 1; + struct _cpuid4_info id4 =3D {}; =20 - cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx); - if (eax) - num_sharing_cache =3D ((eax >> 14) & 0xfff) + 1; - - if (num_sharing_cache) { - int index_msb =3D get_count_order(num_sharing_cache); - - c->topo.llc_id =3D c->topo.apicid >> index_msb; - } + if (!amd_fill_cpuid4_info(llc_index, &id4)) + c->topo.llc_id =3D get_cache_id(c->topo.apicid, &id4); } } =20 @@ -598,22 +606,6 @@ int init_cache_level(unsigned int cpu) return 0; } =20 -/* - * The max shared threads number comes from CPUID(0x4) EAX[25-14] with inp= ut - * ECX as cache index. Then right shift apicid by the number's order to get - * cache id for this cache node. - */ -static unsigned int get_cache_id(u32 apicid, struct _cpuid4_info *id4) -{ - unsigned long num_threads_sharing; - int index_msb; - - num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; - index_msb =3D get_count_order(num_threads_sharing); - - return apicid >> index_msb; -} - int populate_cache_leaves(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); --=20 2.34.1