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charset="utf-8" From: Mohammad Rafi Shaik Add WSA LPASS macro Codec along with SoundWire controller. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 18e959806a13..c51c38cf147a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -28,6 +28,7 @@ #include #include #include +#include #include #include =20 @@ -2773,6 +2774,66 @@ swr1: soundwire@3230000 { status =3D "disabled"; }; =20 + lpass_wsa_macro: codec@3240000 { + compatible =3D "qcom,sc7280-lpass-wsa-macro"; + reg =3D <0x0 0x03240000 0x0 0x1000>; + + clocks =3D <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names =3D "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; + + pinctrl-0 =3D <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; + pinctrl-names =3D "default"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + + status =3D "disabled"; + }; + + swr2: soundwire@3250000 { + compatible =3D "qcom,soundwire-v1.6.0"; + reg =3D <0x0 0x03250000 0x0 0x2000>; + + interrupts =3D ; + clocks =3D <&lpass_wsa_macro>; + clock-names =3D "iface"; + + resets =3D <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names =3D "swr_audio_cgcr"; + + qcom,din-ports =3D <2>; + qcom,dout-ports =3D <6>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x07 0x1f 0x3f 0x07 + 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0= a>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x0= 0>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff= >; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff= 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 + 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + + status =3D "disabled"; + }; + lpass_audiocc: clock-controller@3300000 { compatible =3D "qcom,sc7280-lpassaudiocc"; reg =3D <0 0x03300000 0 0x30000>, @@ -2976,6 +3037,22 @@ lpass_tx_swr_data: tx-swr-data-state { pins =3D "gpio1", "gpio2", "gpio14"; function =3D "swr_tx_data"; }; + + lpass_wsa_swr_clk: wsa-swr-clk-state { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + lpass_wsa_swr_data: wsa-swr-data-state { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; }; =20 gpu: gpu@3d00000 { --=20 2.34.1