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charset="utf-8" From: Mohammad Rafi Shaik Add GPR(Generic Pack router) node along with APM(Audio Process Manager) and PRM(Proxy resource Manager) audio services. A new qcs6490-audioreach.dtsi file has been added to update AudioReach specific device tree configurations. The existing audio nodes in sc7280.dtsi, which were designed for the ADSP Bypass solution. The audio nodes now being updated in qcs6490-audioreach.dtsi to support the ADSP-based AudioReach architecture. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio --- .../boot/dts/qcom/qcs6490-audioreach.dtsi | 54 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 2 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi diff --git a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/arch/arm64/= boot/dts/qcom/qcs6490-audioreach.dtsi new file mode 100644 index 000000000000..282938c042f7 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi @@ -0,0 +1,54 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * qcs6490 device tree source for Audioreach Solution. + * This file will configure and manage nodes from sc7280.dtsi to + * support the AudioReach solution. + * + * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include + +&remoteproc_adsp_glink { + /delete-node/ apr; + + gpr { + compatible =3D "qcom,gpr"; + qcom,glink-channels =3D "adsp_apps"; + qcom,domain =3D ; + qcom,intents =3D <512 20>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + q6apm: service@1 { + compatible =3D "qcom,q6apm"; + reg =3D ; + #sound-dai-cells =3D <0>; + qcom,protection-domain =3D "avs/audio", "msm/adsp/audio_pd"; + + q6apmdai: dais { + compatible =3D "qcom,q6apm-dais"; + iommus =3D <&apps_smmu 0x1801 0x0>; + }; + + q6apmbedai: bedais { + compatible =3D "qcom,q6apm-lpass-dais"; + #sound-dai-cells =3D <1>; + }; + }; + + q6prm: service@2 { + compatible =3D "qcom,q6prm"; + reg =3D ; + qcom,protection-domain =3D "avs/audio", "msm/adsp/audio_pd"; + + q6prmcc: clock-controller { + compatible =3D "qcom,q6prm-lpass-clocks"; + #clock-cells =3D <2>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 0dd6a5c91d10..18e959806a13 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3944,7 +3944,7 @@ remoteproc_adsp: remoteproc@3700000 { =20 status =3D "disabled"; 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charset="utf-8" From: Mohammad Rafi Shaik Document the clock property in sc7280 LPASS LPI pinctrl node. Clock settings required for Audioreach solution. The existing SC7280 platform only supports non-ADSP audio solutions. To enable audio functionality on ADSP with the AudioReach solution. additional core and audio hardware clocks must be configured. Without these clocks, the ADSP will crash. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Krzysztof Kozlowski --- .../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lp= i-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpas= s-lpi-pinctrl.yaml index 08801cc4e476..bc7b8dda8837 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinct= rl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinct= rl.yaml @@ -20,6 +20,16 @@ properties: reg: maxItems: 2 =20 + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + patternProperties: "-state$": oneOf: @@ -70,10 +80,16 @@ unevaluatedProperties: false =20 examples: - | + #include lpass_tlmm: pinctrl@33c0000 { compatible =3D "qcom,sc7280-lpass-lpi-pinctrl"; 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charset="utf-8" From: Mohammad Rafi Shaik Manage clock settings for ADSP solution. On Existing ADSP bypass solutions, the macro and dcodec GDSCs are enabled using power domains in lpass-va-macro which is not applicable for ADSP based platform. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Krzysztof Kozlowski --- .../bindings/sound/qcom,lpass-va-macro.yaml | 23 +++++++++++++++---- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.ya= ml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index dd549db6c841..3bfb0538dba2 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -79,12 +79,25 @@ allOf: compatible: contains: const: qcom,sc7280-lpass-va-macro + then: - properties: - clocks: - maxItems: 1 - clock-names: - maxItems: 1 + if: + required: + - power-domains + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + else: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + minItems: 3 + maxItems: 3 =20 - if: properties: --=20 2.34.1 From nobody Sat Oct 4 01:48:20 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2ECCB2C21E1; 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charset="utf-8" From: Mohammad Rafi Shaik Add WSA LPASS macro Codec along with SoundWire controller. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 77 ++++++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 18e959806a13..c51c38cf147a 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -28,6 +28,7 @@ #include #include #include +#include #include #include =20 @@ -2773,6 +2774,66 @@ swr1: soundwire@3230000 { status =3D "disabled"; }; =20 + lpass_wsa_macro: codec@3240000 { + compatible =3D "qcom,sc7280-lpass-wsa-macro"; + reg =3D <0x0 0x03240000 0x0 0x1000>; + + clocks =3D <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, + <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, + <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names =3D "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; + + pinctrl-0 =3D <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; + pinctrl-names =3D "default"; + + #clock-cells =3D <0>; + clock-output-names =3D "mclk"; + #sound-dai-cells =3D <1>; + + status =3D "disabled"; + }; + + swr2: soundwire@3250000 { + compatible =3D "qcom,soundwire-v1.6.0"; + reg =3D <0x0 0x03250000 0x0 0x2000>; + + interrupts =3D ; + clocks =3D <&lpass_wsa_macro>; + clock-names =3D "iface"; + + resets =3D <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; + reset-names =3D "swr_audio_cgcr"; + + qcom,din-ports =3D <2>; + qcom,dout-ports =3D <6>; + + qcom,ports-sinterval-low =3D /bits/ 8 <0x07 0x1f 0x3f 0x07 + 0x1f 0x3f 0x0f 0x0f>; + qcom,ports-offset1 =3D /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0= a>; + qcom,ports-offset2 =3D /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x0= 0>; + qcom,ports-hstart =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff= >; + qcom,ports-hstop =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; + qcom,ports-word-length =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff= 0xff>; + qcom,ports-block-pack-mode =3D /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 + 0xff 0xff>; + qcom,ports-block-group-count =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff>; + qcom,ports-lane-control =3D /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff + 0xff 0xff>; + + #address-cells =3D <2>; + #size-cells =3D <0>; + #sound-dai-cells =3D <1>; + + status =3D "disabled"; + }; + lpass_audiocc: clock-controller@3300000 { compatible =3D "qcom,sc7280-lpassaudiocc"; reg =3D <0 0x03300000 0 0x30000>, @@ -2976,6 +3037,22 @@ lpass_tx_swr_data: tx-swr-data-state { pins =3D "gpio1", "gpio2", "gpio14"; function =3D "swr_tx_data"; }; + + lpass_wsa_swr_clk: wsa-swr-clk-state { + pins =3D "gpio10"; + function =3D "wsa_swr_clk"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-disable; + }; + + lpass_wsa_swr_data: wsa-swr-data-state { + pins =3D "gpio11"; + function =3D "wsa_swr_data"; + drive-strength =3D <2>; + slew-rate =3D <1>; + bias-bus-hold; + }; }; =20 gpu: gpu@3d00000 { --=20 2.34.1 From nobody Sat Oct 4 01:48:20 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ADC92D4802; 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charset="utf-8" From: Mohammad Rafi Shaik Modify and enable WSA, VA, RX and TX lpass macros and lpass_tlmm clock settings. For audioreach solution mclk, npl and fsgen clocks are enabled through the q6prm clock driver. For qcs6490 RX drives clk from TX CORE which is mandated from DSP side, Unlike dedicated core clocks. Core TX clk is used for both RX and WSA as per DSP recommendations. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio --- .../boot/dts/qcom/qcs6490-audioreach.dtsi | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/arch/arm64/= boot/dts/qcom/qcs6490-audioreach.dtsi index 282938c042f7..6d3a9e171066 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi @@ -12,6 +12,67 @@ #include #include =20 +&lpass_rx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE= _NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names =3D "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + +&lpass_tlmm { + clocks =3D <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "core", + "audio"; +}; + +&lpass_tx_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE= _NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names =3D "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + +&lpass_va_macro { + /delete-property/ power-domains; + /delete-property/ power-domain-names; + clocks =3D <&q6prmcc LPASS_CLK_ID_VA_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE= _NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names =3D "mclk", + "macro", + "dcodec"; +}; + +&lpass_wsa_macro { + clocks =3D <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE= _NO>, + <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&lpass_va_macro>; + clock-names =3D "mclk", + "npl", + "macro", + "dcodec", + "fsgen"; +}; + &remoteproc_adsp_glink { /delete-node/ apr; =20 --=20 2.34.1 From nobody Sat Oct 4 01:48:20 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C28692C11FE; Thu, 21 Aug 2025 04:49:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755751770; cv=none; b=TEvWW+n8JukKHytuDeZz4Yu7vklHYDgqJXjQSfwB/bsP5FXxWCZOo8gufCxw+VVxFz0dP4Ej1SKPN85hJAFbBCoHao54QVQxhZjvrH/NxCxshCnvV0ieRPapPlkH0svqN1bZT8TbO1zE4syqZIb3nV+Fls0SKZ90UhZYNeQgzhM= ARC-Message-Signature: i=1; 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charset="utf-8" From: Mohammad Rafi Shaik Add nodes for WSA8830 speakers amplifier on qcs6490-rb3gen2 board. Enable lpass_wsa and lpass_va macros along with pinctrl settings for audio. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla --- .../boot/dts/qcom/qcs6490-audioreach.dtsi | 6 ++++ arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 35 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 8 +++++ 3 files changed, 49 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/arch/arm64/= boot/dts/qcom/qcs6490-audioreach.dtsi index 6d3a9e171066..078936237e20 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi @@ -58,6 +58,12 @@ &lpass_va_macro { clock-names =3D "mclk", "macro", "dcodec"; + + pinctrl-0 =3D <&lpass_dmic01_clk>, <&lpass_dmic01_data>, + <&lpass_dmic23_clk>, <&lpass_dmic23_data>; + pinctrl-names =3D "default"; + + qcom,dmic-sample-rate =3D <4800000>; }; =20 &lpass_wsa_macro { diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index 7509c27bd3f8..09e2cb9053a6 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -19,6 +19,7 @@ #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "qcs6490-audioreach.dtsi" =20 /delete-node/ &ipa_fw_mem; /delete-node/ &rmtfs_mem; @@ -765,6 +766,14 @@ redriver_usb_con_sbu: endpoint { }; }; =20 +&lpass_va_macro { + status =3D "okay"; +}; + +&lpass_wsa_macro { + status =3D "okay"; +}; + &mdss { status =3D "okay"; }; @@ -1039,6 +1048,32 @@ &sdhc_2 { status =3D "okay"; }; =20 +&swr2 { + status =3D "okay"; + + left_spkr: speaker@0,1 { + compatible =3D "sdw10217020200"; + reg =3D <0 1>; + reset-gpios =3D <&tlmm 158 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + #thermal-sensor-cells =3D <0>; + vdd-supply =3D <&vreg_l18b_1p8>; + qcom,port-mapping =3D <1 2 3 7>; + }; + + right_spkr: speaker@0,2 { + compatible =3D "sdw10217020200"; + reg =3D <0 2>; + reset-gpios =3D <&tlmm 158 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + #thermal-sensor-cells =3D <0>; + vdd-supply =3D <&vreg_l18b_1p8>; + qcom,port-mapping =3D <4 5 6 8>; + }; +}; + &tlmm { gpio-reserved-ranges =3D <32 2>, /* ADSP */ <48 4>; /* NFC */ diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index c51c38cf147a..d472de18296b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3001,21 +3001,29 @@ lpass_tlmm: pinctrl@33c0000 { lpass_dmic01_clk: dmic01-clk-state { pins =3D "gpio6"; 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charset="utf-8" From: Mohammad Rafi Shaik Add the sound card node with tested playback over WSA8835 speakers and digital on-board mics. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 45 ++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot= /dts/qcom/qcs6490-rb3gen2.dts index 09e2cb9053a6..18cea8812001 100644 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts @@ -1048,6 +1048,51 @@ &sdhc_2 { status =3D "okay"; }; =20 +&sound { + compatible =3D "qcom,qcs6490-rb3gen2-sndcard"; + model =3D "QCS6490-RB3Gen2"; + + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "VA DMIC0", "vdd-micb", + "VA DMIC1", "vdd-micb", + "VA DMIC2", "vdd-micb", + "VA DMIC3", "vdd-micb"; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + codec { + sound-dai =3D <&left_spkr>, <&right_spkr>, + <&swr2 0>, <&lpass_wsa_macro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + va-dai-link { + link-name =3D "VA Capture"; + + codec { + sound-dai =3D <&lpass_va_macro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; +}; + &swr2 { status =3D "okay"; =20 --=20 2.34.1 From nobody Sat Oct 4 01:48:20 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F3504277020; Thu, 21 Aug 2025 04:49:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755751780; cv=none; b=KHXSjRUarNEptYsvfbwsfhfTd3Bu1V0JkT0yHMbYv3UzyP+Ew9WgMFRewHuF9NBoU86eyU/zdimnwybXV0Kl/1oq7rzhjMYq7fqeXrTMaxNjt22/Y1NHeKlwuYISb2obJPxcJq5q9H3LzVpqO1nUSQG+pBBq48YiLHcFZAFjSQk= ARC-Message-Signature: i=1; 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charset="utf-8" From: Mohammad Rafi Shaik Add nodes for WSA8830 speakers and WCD9370 headset codec on qcm6490-idp board. Enable lpass macros along with audio support pin controls. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 123 +++++++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 +++ 2 files changed, 135 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts= /qcom/qcm6490-idp.dts index 8ed6e28b0c29..379ee346a33a 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -18,6 +18,7 @@ #include "pm7325.dtsi" #include "pm8350c.dtsi" #include "pmk8350.dtsi" +#include "qcs6490-audioreach.dtsi" =20 /delete-node/ &ipa_fw_mem; /delete-node/ &rmtfs_mem; @@ -169,6 +170,30 @@ vph_pwr: vph-pwr-regulator { regulator-min-microvolt =3D <3700000>; regulator-max-microvolt =3D <3700000>; }; + + wcd9370: audio-codec-0 { + compatible =3D "qcom,wcd9370-codec"; + + pinctrl-0 =3D <&wcd_default>; + pinctrl-names =3D "default"; + + reset-gpios =3D <&tlmm 83 GPIO_ACTIVE_HIGH>; + + vdd-buck-supply =3D <&vreg_l17b_1p7>; + vdd-rxtx-supply =3D <&vreg_l18b_1p8>; + vdd-px-supply =3D <&vreg_l18b_1p8>; + vdd-mic-bias-supply =3D <&vreg_bob_3p296>; + + qcom,micbias1-microvolt =3D <1800000>; + qcom,micbias2-microvolt =3D <1800000>; + qcom,micbias3-microvolt =3D <1800000>; + qcom,micbias4-microvolt =3D <1800000>; + + qcom,rx-device =3D <&wcd937x_rx>; + qcom,tx-device =3D <&wcd937x_tx>; + + #sound-dai-cells =3D <1>; + }; }; =20 &apps_rsc { @@ -536,6 +561,22 @@ &gpu_zap_shader { firmware-name =3D "qcom/qcm6490/a660_zap.mbn"; }; =20 +&lpass_rx_macro { + status =3D "okay"; +}; + +&lpass_tx_macro { + status =3D "okay"; +}; + +&lpass_va_macro { + status =3D "okay"; +}; + +&lpass_wsa_macro { + status =3D "okay"; +}; + &mdss { status =3D "okay"; }; @@ -716,6 +757,81 @@ &sdhc_2 { cd-gpios =3D <&tlmm 91 GPIO_ACTIVE_LOW>; }; =20 +&swr0 { + status =3D "okay"; + + wcd937x_rx: codec@0,4 { + compatible =3D "sdw20217010a00"; + reg =3D <0 4>; + + /* + * WCD9370 RX Port 1 (HPH_L/R) <=3D=3D> SWR1 Port 1 (HPH_L/R) + * WCD9370 RX Port 2 (CLSH) <=3D=3D> SWR1 Port 2 (CLSH) + * WCD9370 RX Port 3 (COMP_L/R) <=3D=3D> SWR1 Port 3 (COMP_L/R) + * WCD9370 RX Port 4 (LO) <=3D=3D> SWR1 Port 4 (LO) + * WCD9370 RX Port 5 (DSD_L/R) <=3D=3D> SWR1 Port 5 (DSD) + */ + qcom,rx-port-mapping =3D <1 2 3 4 5>; + + /* + * Static channels mapping between slave and master rx port channels. + * In the order of slave port channels, which is + * hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. + */ + qcom,rx-channel-mapping =3D /bits/ 8 <1 2 1 1 2 1 1 2>; + }; +}; + +&swr1 { + status =3D "okay"; + + wcd937x_tx: codec@0,3 { + compatible =3D "sdw20217010a00"; + reg =3D <0 3>; + + /* + * WCD9370 TX Port 1 (ADC1) <=3D> SWR2 Port 2 + * WCD9370 TX Port 2 (ADC2, 3) <=3D> SWR2 Port 2 + * WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=3D> SWR2 Port 3 + * WCD9370 TX Port 4 (DMIC4,5,6,7) <=3D> SWR2 Port 4 + */ + qcom,tx-port-mapping =3D <1 1 2 3>; + + /* + * Static channel mapping between slave and master tx port channels. + * In the order of slave port channels which is adc1, adc2, adc3, + * mic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. + */ + qcom,tx-channel-mapping =3D /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>; + }; +}; + +&swr2 { + status =3D "okay"; + + left_spkr: speaker@0,1 { + compatible =3D "sdw10217020200"; + reg =3D <0 1>; + powerdown-gpios =3D <&tlmm 63 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrLeft"; + #thermal-sensor-cells =3D <0>; + vdd-supply =3D <&vreg_l18b_1p8>; + qcom,port-mapping =3D <1 2 3 7>; + }; + + right_spkr: speaker@0,2 { + compatible =3D "sdw10217020200"; + reg =3D <0 2>; + powerdown-gpios =3D <&tlmm 62 GPIO_ACTIVE_LOW>; + #sound-dai-cells =3D <0>; + sound-name-prefix =3D "SpkrRight"; + #thermal-sensor-cells =3D <0>; + vdd-supply =3D <&vreg_l18b_1p8>; + qcom,port-mapping =3D <4 5 6 8>; + }; +}; + &tlmm { gpio-reserved-ranges =3D <32 2>, /* ADSP */ <48 4>; /* NFC */ @@ -725,6 +841,13 @@ sd_cd: sd-cd-state { function =3D "gpio"; bias-pull-up; }; + + wcd_default: wcd-reset-n-active-state { + pins =3D "gpio83"; + function =3D "gpio"; + drive-strength =3D <16>; + bias-disable; + }; }; =20 &uart5 { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index d472de18296b..1b942e15377d 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3029,21 +3029,33 @@ lpass_dmic23_data: dmic23-data-state { lpass_rx_swr_clk: rx-swr-clk-state { pins =3D "gpio3"; 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charset="utf-8" From: Mohammad Rafi Shaik Add the sound card node with tested playback over WSA8835 speakers, digital on-board mics along with wcd9370 headset playabck and record. Signed-off-by: Mohammad Rafi Shaik Co-developed-by: Prasad Kumpatla Signed-off-by: Prasad Kumpatla Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 84 ++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/arch/arm64/boot/dts= /qcom/qcm6490-idp.dts index 379ee346a33a..73fce639370c 100644 --- a/arch/arm64/boot/dts/qcom/qcm6490-idp.dts +++ b/arch/arm64/boot/dts/qcom/qcm6490-idp.dts @@ -757,6 +757,90 @@ &sdhc_2 { cd-gpios =3D <&tlmm 91 GPIO_ACTIVE_LOW>; }; =20 +&sound { + compatible =3D "qcom,qcm6490-idp-sndcard"; + model =3D "QCM6490-IDP"; + + audio-routing =3D "SpkrLeft IN", "WSA_SPK1 OUT", + "SpkrRight IN", "WSA_SPK2 OUT", + "IN1_HPHL", "HPHL_OUT", + "IN2_HPHR", "HPHR_OUT", + "AMIC2", "MIC BIAS2", + "TX DMIC0", "MIC BIAS1", + "TX DMIC1", "MIC BIAS2", + "TX DMIC2", "MIC BIAS3", + "TX SWR_ADC1", "ADC2_OUTPUT", + "VA DMIC0", "VA MIC BIAS3", + "VA DMIC1", "VA MIC BIAS3", + "VA DMIC2", "VA MIC BIAS1", + "VA DMIC3", "VA MIC BIAS1"; + + wsa-dai-link { + link-name =3D "WSA Playback"; + + codec { + sound-dai =3D <&left_spkr>, <&right_spkr>, + <&swr2 0>, <&lpass_wsa_macro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai WSA_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-playback-dai-link { + link-name =3D "WCD Playback"; + + codec { + sound-dai =3D <&wcd9370 0>, <&swr0 0>, <&lpass_rx_macro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai RX_CODEC_DMA_RX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + wcd-capture-dai-link { + link-name =3D "WCD Capture"; + + codec { + sound-dai =3D <&wcd9370 1>, <&swr1 0>, <&lpass_tx_macro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai TX_CODEC_DMA_TX_3>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; + + va-dai-link { + link-name =3D "VA Capture"; + + codec { + sound-dai =3D <&lpass_va_macro 0>; + }; + + cpu { + sound-dai =3D <&q6apmbedai VA_CODEC_DMA_TX_0>; + }; + + platform { + sound-dai =3D <&q6apm>; + }; + }; +}; + &swr0 { status =3D "okay"; =20 --=20 2.34.1