From nobody Sat Oct 4 03:08:23 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D8AC52E972D; Thu, 21 Aug 2025 03:59:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.9 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755748779; cv=none; b=XP+arVft4Eg/A5C0aGOvYt57k3x6O8xDcqxZmHH125yqyUKDovpMJ55k+QEe6vpYbMP4/bjB1GKW0gFMFWUeveqGyDjg79EZcum6Jub54L9l5jZ/WkfuokyA09z7JHvRP/vc+NTjew92bqwmZ331bRXM6OpyyfucH5YFjD0AT6I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755748779; c=relaxed/simple; bh=aXYdU9KOSqarKDWf7rpj6IvBcVNLlwGDr2KFjGJ3ZY8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=OOHLlA2gmUkMV98dZaxOPXhRti/tNoRc1M6ZU/paFnMv2s9dIN2dNSbTCvaqRzATz64tWckIoh0KnwNNaZBZAgm9iRzfIv29QgrT4oXmN7zR0mmQmd3xjQwB2/Rk3RGRN4lcs0YwRiotTn8CHs4X9FDW42tGIX4MKK4tcaGfq+4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=WorgIcK1; arc=none smtp.client-ip=192.198.163.9 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="WorgIcK1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755748778; x=1787284778; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aXYdU9KOSqarKDWf7rpj6IvBcVNLlwGDr2KFjGJ3ZY8=; b=WorgIcK1err0S7HpDTkDwsBYqgO7aZKVzt1aGXuNIKc+QGXFIzzLY5j3 gxjMEfrNRjQA1OUXfknU9GrGDweJLhDLRUtOdQC/18U94Ud7ZLlV9H9Sr NI1PFnpZYXY7KsY0LcH6OlRnm05/DUUchvpkGaJD+m4URIqWT+kLdeAW9 PJx7+0onz+RpHh5xNbZb/5SMwfI8Er66vlhFO9Xdodn+e/MtB0LG0fNVw CVsjaI/TC6Z99FqxLGxHod9IGEvVqs4q71noOs2DVF2bQShoB1+uaHbZ4 UR6KQo+K1/SRLTGDTpDOrAwbtwfHUTfoKtLSApLCJCF2Ly5m1DagLzF7G w==; X-CSE-ConnectionGUID: HqFrdgc/Q4iJPhD7pFRQRA== X-CSE-MsgGUID: YnyQO5KaRvq3I6iz54LEnA== X-IronPort-AV: E=McAfee;i="6800,10657,11527"; a="68731975" X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="68731975" Received: from fmviesa009.fm.intel.com ([10.60.135.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 20 Aug 2025 20:59:38 -0700 X-CSE-ConnectionGUID: OmG1/shDQiuQrjWKgbJBOg== X-CSE-MsgGUID: RrRJKaT1SV+uCVKhpcMtqQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,306,1747724400"; d="scan'208";a="168713082" Received: from spr.sh.intel.com ([10.112.229.196]) by fmviesa009.fm.intel.com with ESMTP; 20 Aug 2025 20:59:34 -0700 From: Dapeng Mi To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , Adrian Hunter , Alexander Shishkin , Kan Liang , Andi Kleen , Eranian Stephane Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Dapeng Mi , Dapeng Mi Subject: [Patch v6 05/10] perf/x86/intel/ds: Factor out PEBS group processing code to functions Date: Thu, 21 Aug 2025 11:58:00 +0800 Message-Id: <20250821035805.159494-6-dapeng1.mi@linux.intel.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250821035805.159494-1-dapeng1.mi@linux.intel.com> References: <20250821035805.159494-1-dapeng1.mi@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Adaptive PEBS and arch-PEBS share lots of same code to process these PEBS groups, like basic, GPR and meminfo groups. Extract these shared code to generic functions to avoid duplicated code. Signed-off-by: Dapeng Mi --- arch/x86/events/intel/ds.c | 170 +++++++++++++++++++++++-------------- 1 file changed, 104 insertions(+), 66 deletions(-) diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 7fe631da3334..0641371a96e3 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2072,6 +2072,90 @@ static inline void __setup_pebs_counter_group(struct= cpu_hw_events *cpuc, =20 #define PEBS_LATENCY_MASK 0xffff =20 +static inline void __setup_perf_sample_data(struct perf_event *event, + struct pt_regs *iregs, + struct perf_sample_data *data) +{ + perf_sample_data_init(data, 0, event->hw.last_period); + + /* + * We must however always use iregs for the unwinder to stay sane; the + * record BP,SP,IP can point into thin air when the record is from a + * previous PMI context or an (I)RET happened between the record and + * PMI. + */ + perf_sample_save_callchain(data, event, iregs); +} + +static inline void __setup_pebs_basic_group(struct perf_event *event, + struct pt_regs *regs, + struct perf_sample_data *data, + u64 sample_type, u64 ip, + u64 tsc, u16 retire) +{ + /* The ip in basic is EventingIP */ + set_linear_ip(regs, ip); + regs->flags =3D PERF_EFLAGS_EXACT; + setup_pebs_time(event, data, tsc); + + if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) + data->weight.var3_w =3D retire; +} + +static inline void __setup_pebs_gpr_group(struct perf_event *event, + struct pt_regs *regs, + struct pebs_gprs *gprs, + u64 sample_type) +{ + if (event->attr.precise_ip < 2) { + set_linear_ip(regs, gprs->ip); + regs->flags &=3D ~PERF_EFLAGS_EXACT; + } + + if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)) + adaptive_pebs_save_regs(regs, gprs); +} + +static inline void __setup_pebs_meminfo_group(struct perf_event *event, + struct perf_sample_data *data, + u64 sample_type, u64 latency, + u16 instr_latency, u64 address, + u64 aux, u64 tsx_tuning, u64 ax) +{ + if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) { + u64 tsx_latency =3D intel_get_tsx_weight(tsx_tuning); + + data->weight.var2_w =3D instr_latency; + + /* + * Although meminfo::latency is defined as a u64, + * only the lower 32 bits include the valid data + * in practice on Ice Lake and earlier platforms. + */ + if (sample_type & PERF_SAMPLE_WEIGHT) + data->weight.full =3D latency ?: tsx_latency; + else + data->weight.var1_dw =3D (u32)latency ?: tsx_latency; + + data->sample_flags |=3D PERF_SAMPLE_WEIGHT_TYPE; + } + + if (sample_type & PERF_SAMPLE_DATA_SRC) { + data->data_src.val =3D get_data_src(event, aux); + data->sample_flags |=3D PERF_SAMPLE_DATA_SRC; + } + + if (sample_type & PERF_SAMPLE_ADDR_TYPE) { + data->addr =3D address; + data->sample_flags |=3D PERF_SAMPLE_ADDR; + } + + if (sample_type & PERF_SAMPLE_TRANSACTION) { + data->txn =3D intel_get_tsx_transaction(tsx_tuning, ax); + data->sample_flags |=3D PERF_SAMPLE_TRANSACTION; + } +} + /* * With adaptive PEBS the layout depends on what fields are configured. */ @@ -2081,12 +2165,14 @@ static void setup_pebs_adaptive_sample_data(struct = perf_event *event, struct pt_regs *regs) { struct cpu_hw_events *cpuc =3D this_cpu_ptr(&cpu_hw_events); + u64 sample_type =3D event->attr.sample_type; struct pebs_basic *basic =3D __pebs; void *next_record =3D basic + 1; - u64 sample_type, format_group; struct pebs_meminfo *meminfo =3D NULL; struct pebs_gprs *gprs =3D NULL; struct x86_perf_regs *perf_regs; + u64 format_group; + u16 retire; =20 if (basic =3D=3D NULL) return; @@ -2094,31 +2180,17 @@ static void setup_pebs_adaptive_sample_data(struct = perf_event *event, perf_regs =3D container_of(regs, struct x86_perf_regs, regs); perf_regs->xmm_regs =3D NULL; =20 - sample_type =3D event->attr.sample_type; format_group =3D basic->format_group; - perf_sample_data_init(data, 0, event->hw.last_period); =20 - setup_pebs_time(event, data, basic->tsc); - - /* - * We must however always use iregs for the unwinder to stay sane; the - * record BP,SP,IP can point into thin air when the record is from a - * previous PMI context or an (I)RET happened between the record and - * PMI. - */ - perf_sample_save_callchain(data, event, iregs); + __setup_perf_sample_data(event, iregs, data); =20 *regs =3D *iregs; - /* The ip in basic is EventingIP */ - set_linear_ip(regs, basic->ip); - regs->flags =3D PERF_EFLAGS_EXACT; =20 - if (sample_type & PERF_SAMPLE_WEIGHT_STRUCT) { - if (x86_pmu.flags & PMU_FL_RETIRE_LATENCY) - data->weight.var3_w =3D basic->retire_latency; - else - data->weight.var3_w =3D 0; - } + /* basic group */ + retire =3D x86_pmu.flags & PMU_FL_RETIRE_LATENCY ? + basic->retire_latency : 0; + __setup_pebs_basic_group(event, regs, data, sample_type, + basic->ip, basic->tsc, retire); =20 /* * The record for MEMINFO is in front of GP @@ -2134,54 +2206,20 @@ static void setup_pebs_adaptive_sample_data(struct = perf_event *event, gprs =3D next_record; next_record =3D gprs + 1; =20 - if (event->attr.precise_ip < 2) { - set_linear_ip(regs, gprs->ip); - regs->flags &=3D ~PERF_EFLAGS_EXACT; - } - - if (sample_type & (PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)) - adaptive_pebs_save_regs(regs, gprs); + __setup_pebs_gpr_group(event, regs, gprs, sample_type); } =20 if (format_group & PEBS_DATACFG_MEMINFO) { - if (sample_type & PERF_SAMPLE_WEIGHT_TYPE) { - u64 latency =3D x86_pmu.flags & PMU_FL_INSTR_LATENCY ? - meminfo->cache_latency : meminfo->mem_latency; - - if (x86_pmu.flags & PMU_FL_INSTR_LATENCY) - data->weight.var2_w =3D meminfo->instr_latency; - - /* - * Although meminfo::latency is defined as a u64, - * only the lower 32 bits include the valid data - * in practice on Ice Lake and earlier platforms. - */ - if (sample_type & PERF_SAMPLE_WEIGHT) { - data->weight.full =3D latency ?: - intel_get_tsx_weight(meminfo->tsx_tuning); - } else { - data->weight.var1_dw =3D (u32)latency ?: - intel_get_tsx_weight(meminfo->tsx_tuning); - } - - data->sample_flags |=3D PERF_SAMPLE_WEIGHT_TYPE; - } - - if (sample_type & PERF_SAMPLE_DATA_SRC) { - data->data_src.val =3D get_data_src(event, meminfo->aux); - data->sample_flags |=3D PERF_SAMPLE_DATA_SRC; - } - - if (sample_type & PERF_SAMPLE_ADDR_TYPE) { - data->addr =3D meminfo->address; - data->sample_flags |=3D PERF_SAMPLE_ADDR; - } - - if (sample_type & PERF_SAMPLE_TRANSACTION) { - data->txn =3D intel_get_tsx_transaction(meminfo->tsx_tuning, - gprs ? gprs->ax : 0); - data->sample_flags |=3D PERF_SAMPLE_TRANSACTION; - } + u64 latency =3D x86_pmu.flags & PMU_FL_INSTR_LATENCY ? + meminfo->cache_latency : meminfo->mem_latency; + u64 instr_latency =3D x86_pmu.flags & PMU_FL_INSTR_LATENCY ? + meminfo->instr_latency : 0; + u64 ax =3D gprs ? gprs->ax : 0; + + __setup_pebs_meminfo_group(event, data, sample_type, latency, + instr_latency, meminfo->address, + meminfo->aux, meminfo->tsx_tuning, + ax); } =20 if (format_group & PEBS_DATACFG_XMMS) { --=20 2.34.1