From nobody Sat Oct 4 05:02:39 2025 Received: from szxga06-in.huawei.com (szxga06-in.huawei.com [45.249.212.32]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96DCA242D62; Thu, 21 Aug 2025 01:38:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.32 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755740302; cv=none; b=kRDxaAWttoMH7xIvgzfyTEVvwsuIWTaTdJtxkuyFTU2pzmQk5z8synroGPS084X5qE3vGQjXjVAAr3L2FezeNXVaR+cY6lLCJFLlvrt+RLM//5nWf6orTxggq6HVjdqQde7EzRoBTV6iFyqi9HvXW47ofPeUqwnNDn6CY+Jz8oI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755740302; c=relaxed/simple; bh=A8tlPZwwTYm1xICAETpYUMgRf2FY/fHYiez3h9vnYr0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=HTxbnqSLwfwRQSlN+xp0dGOxOXC6mYtW4aTJ2rhNTAayaepKDJICKZUv7Fh4d8pMauX1xRAtMA8esTrok0h/f53F8ZBcKQj2tyBhd4sPuP8q0q5oCiZCGBEuIzfwPWOXana4CoCGyQo2IG8wamrUSBt4oJ7JHsiP9nPopp/K5YQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.32 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.163.17]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4c6mFc37Hjz27jSD; Thu, 21 Aug 2025 09:39:16 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id 038FB1A0190; Thu, 21 Aug 2025 09:38:11 +0800 (CST) Received: from kwepemq200001.china.huawei.com (7.202.195.16) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 21 Aug 2025 09:38:10 +0800 Received: from localhost.huawei.com (10.90.31.46) by kwepemq200001.china.huawei.com (7.202.195.16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 21 Aug 2025 09:38:09 +0800 From: Chenghai Huang To: , CC: , , , , , , , Subject: [PATCH v2 1/6] crypto: hisilicon/zip - remove unnecessary validation for high-performance mode configurations Date: Thu, 21 Aug 2025 09:38:04 +0800 Message-ID: <20250821013809.4016506-2-huangchenghai2@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250821013809.4016506-1-huangchenghai2@huawei.com> References: <20250821013809.4016506-1-huangchenghai2@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100001.china.huawei.com (7.221.188.238) To kwepemq200001.china.huawei.com (7.202.195.16) Content-Type: text/plain; charset="utf-8" When configuring the high-performance mode register, there is no need to verify whether the register has been successfully enabled, as there is no possibility of a write failure for this register. Fixes: a9864bae1806 ("crypto: hisilicon/zip - add zip comp high perf mode c= onfiguration") Signed-off-by: Chenghai Huang --- drivers/crypto/hisilicon/zip/zip_main.c | 14 ++------------ 1 file changed, 2 insertions(+), 12 deletions(-) diff --git a/drivers/crypto/hisilicon/zip/zip_main.c b/drivers/crypto/hisil= icon/zip/zip_main.c index d8ba23b7cc7d..fb7b19927dd3 100644 --- a/drivers/crypto/hisilicon/zip/zip_main.c +++ b/drivers/crypto/hisilicon/zip/zip_main.c @@ -448,10 +448,9 @@ bool hisi_zip_alg_support(struct hisi_qm *qm, u32 alg) return false; } =20 -static int hisi_zip_set_high_perf(struct hisi_qm *qm) +static void hisi_zip_set_high_perf(struct hisi_qm *qm) { u32 val; - int ret; =20 val =3D readl_relaxed(qm->io_base + HZIP_HIGH_PERF_OFFSET); if (perf_mode =3D=3D HZIP_HIGH_COMP_PERF) @@ -461,13 +460,6 @@ static int hisi_zip_set_high_perf(struct hisi_qm *qm) =20 /* Set perf mode */ writel(val, qm->io_base + HZIP_HIGH_PERF_OFFSET); - ret =3D readl_relaxed_poll_timeout(qm->io_base + HZIP_HIGH_PERF_OFFSET, - val, val =3D=3D perf_mode, HZIP_DELAY_1_US, - HZIP_POLL_TIMEOUT_US); - if (ret) - pci_err(qm->pdev, "failed to set perf mode\n"); - - return ret; } =20 static void hisi_zip_open_sva_prefetch(struct hisi_qm *qm) @@ -1251,9 +1243,7 @@ static int hisi_zip_pf_probe_init(struct hisi_zip *hi= si_zip) if (ret) return ret; =20 - ret =3D hisi_zip_set_high_perf(qm); - if (ret) - return ret; + hisi_zip_set_high_perf(qm); =20 hisi_zip_open_sva_prefetch(qm); hisi_qm_dev_err_init(qm); --=20 2.33.0