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Thu, 21 Aug 2025 12:55:53 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 57LCtpX6021436 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Aug 2025 12:55:51 GMT Received: from hu-vpernami-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Thu, 21 Aug 2025 05:55:50 -0700 From: Vivek.Pernamitta@quicinc.com Date: Thu, 21 Aug 2025 18:25:38 +0530 Subject: [PATCH v3 6/6] bus: mhi: host: pci_generic: Support independent DMA mask for VFs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250821-vdev_next-20250821_sriov-v3-6-e1b017c48d4a@quicinc.com> References: <20250821-vdev_next-20250821_sriov-v3-0-e1b017c48d4a@quicinc.com> In-Reply-To: <20250821-vdev_next-20250821_sriov-v3-0-e1b017c48d4a@quicinc.com> To: Manivannan Sadhasivam CC: , , , Vivek Pernamitta X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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However, Virtual Functions (VFs) are enabled only after the device enters Mission Mode and can support higher DMA address ranges (up to 40 bits). A 32-bit DMA mask limits addressable space to 4GiB, which is insufficient for data transfer requirements over VFs on platforms like QDU100. These devices require larger memory regions to be mapped for efficient VF operation. To address this, configure `dma_mask` independently for Physical Functions (PFs) and Virtual Functions (VFs), allowing VFs to use higher DMA mask values where supported. As per PCIe SR-IOV specification (rev 0.9, Section 1), VFs are capable of handling resources associated with the main data movement of the Function. This change ensures compatibility with bootloaders that have limited DMA capabilities while enabling full VF functionality once the device reaches Mission Mode. Signed-off-by: Vivek Pernamitta --- drivers/bus/mhi/host/pci_generic.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/bus/mhi/host/pci_generic.c b/drivers/bus/mhi/host/pci_= generic.c index f922cca0ab633aeae942587f0c40038342ce9c33..fad08bdd59919a1cab05e9864fb= 38151ef79e457 100644 --- a/drivers/bus/mhi/host/pci_generic.c +++ b/drivers/bus/mhi/host/pci_generic.c @@ -41,6 +41,7 @@ * @edl_trigger: capable of triggering EDL mode in the device (if supporte= d) * @bar_num: PCI base address register to use for MHI MMIO register space * @dma_data_width: DMA transfer word size (32 or 64 bits) + * @vf_dma_data_width: DMA transfer word size for VF's (optional) * @mru_default: default MRU size for MBIM network packets * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead * of inband wake support (such as sdx24) @@ -57,6 +58,7 @@ struct mhi_pci_dev_info { bool edl_trigger; unsigned int bar_num; unsigned int dma_data_width; + unsigned int vf_dma_data_width; unsigned int mru_default; bool sideband_wake; bool no_m3; @@ -301,6 +303,7 @@ static const struct mhi_pci_dev_info mhi_qcom_qdu100_in= fo =3D { .config =3D &mhi_qcom_qdu100_config, .bar_num =3D MHI_PCI_DEFAULT_BAR_NUM, .dma_data_width =3D 32, + .vf_dma_data_width =3D 40, .sideband_wake =3D false, .no_m3 =3D true, .reset_on_remove =3D true, @@ -1312,6 +1315,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const = struct pci_device_id *id) const struct mhi_controller_config *mhi_cntrl_config; struct mhi_pci_device *mhi_pdev; struct mhi_controller *mhi_cntrl; + unsigned int dma_data_width; int err; =20 dev_info(&pdev->dev, "MHI PCI device found: %s\n", info->name); @@ -1333,9 +1337,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const= struct pci_device_id *id) =20 mhi_cntrl =3D &mhi_pdev->mhi_cntrl; =20 + dma_data_width =3D (pdev->is_virtfn && info->vf_dma_data_width) ? + info->vf_dma_data_width : info->dma_data_width; + mhi_cntrl->cntrl_dev =3D &pdev->dev; mhi_cntrl->iova_start =3D 0; - mhi_cntrl->iova_stop =3D (dma_addr_t)DMA_BIT_MASK(info->dma_data_width); + mhi_cntrl->iova_stop =3D (dma_addr_t)DMA_BIT_MASK(dma_data_width); mhi_cntrl->fw_image =3D info->fw; mhi_cntrl->edl_image =3D info->edl; =20 @@ -1359,7 +1366,7 @@ static int mhi_pci_probe(struct pci_dev *pdev, const = struct pci_device_id *id) mhi_cntrl->wake_toggle =3D mhi_pci_wake_toggle_nop; } =20 - err =3D mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_da= ta_width)); + err =3D mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(dma_data_wid= th)); if (err) return err; =20 --=20 2.34.1