From nobody Sat Oct 4 02:56:40 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8DA3A30BF7F; Thu, 21 Aug 2025 11:12:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755774759; cv=none; b=PnAFAQRsLb7aPO0zafLDw1nWyHkolq5bctc+bNLC+7EyNTZFc6xWsX+vcv3lNP2Q2ita2SVbq+e3bS0D5xb1s/C5134ZJSSSaHhhNFSzqvJKcZnSVx1JqYxqPkXu0Jg/NCGbTX4HjmRk4B4Poyn0QERS+7qA7TaFbVrbxnaUg5Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755774759; c=relaxed/simple; bh=OYdOTPp/WleG/23x+u2iGWLmZo8oqF7YKe5sSXtY4gI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Ct9eA5sXuCb8oPeVCECtnYcDmBFMJp1qlsQuNZHJe5UHikylGdvfkXyVvtWfI7KNeMMWAT7eLQX40nDtnChu/xiD/YDqH6f9UL3YRQjcNH+2zAka2YQ1w4l0gNfBiTocKwDo04jdbg32zX0WXrU33/CZUhe2s0B/bWt0F77SvQY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=H7T03kvY; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="H7T03kvY" Received: from pps.filterd (m0369458.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57LAg3FV015986; Thu, 21 Aug 2025 13:12:20 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= kyXtN74VkBaQLErnP6Oirfq2yZX1obNwJfBjqV4IEtw=; b=H7T03kvYX0IT6lpa KX8qLkMNB74dElBoq0a78nBv6n+ZCMzvfT4WkXIY/OVPUHHur0qSPwuonYqvxIYw HdNq93xtjGC1epAKUaAT4KS9r86adubWIBU7X7IS4MSyZxo38KZ+mOihi7jFhR3q +s4RXHXLdefKIClBiDzR40b+CDY7t29VJUp+I/7vdNUitseSysLA9z//0mb076kc nsccQJQB+2j641TCNfgjxSSIBcVqDcW0xGU/UW0RdEjZA/Zo1mYqFSL6FNN1Nin0 F5wuQFt/5uoeFqDZvchvVlqJ/Cgf+COtd/ABQhnzXAeZFPd9URURErLrz5dcd+WO IrdGeQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48nj3v3n8j-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Aug 2025 13:12:20 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 12CA440046; Thu, 21 Aug 2025 13:10:52 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5F83574E7BF; Thu, 21 Aug 2025 13:09:56 +0200 (CEST) Received: from localhost (10.252.7.99) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 21 Aug 2025 13:09:56 +0200 From: Raphael Gallais-Pou Date: Thu, 21 Aug 2025 13:08:56 +0200 Subject: [PATCH v4 06/13] dt-bindings: arm: stm32: add required #clock-cells property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250821-drm-misc-next-v4-6-7060500f8fd3@foss.st.com> References: <20250821-drm-misc-next-v4-0-7060500f8fd3@foss.st.com> In-Reply-To: <20250821-drm-misc-next-v4-0-7060500f8fd3@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE2.st.com (10.75.129.73) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-21_03,2025-08-20_03,2025-03-28_01 On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Reviewed-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou Reviewed-by: Yannick Fertre --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 +++++++++++++++---= ---- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.ya= ml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c84922813e94b1818c07fe8714891c089..95d2319afe235fa86974d80f89c= 9deeae2275232 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 =20 + "#clock-cells": + const: 0 + required: - compatible - reg =20 -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" =20 additionalProperties: false =20 --=20 2.25.1