From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A0DD27814A; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790803; cv=none; b=gth5N4H2jKd4w9xGrqxX//+SmVTWSMaCwrbiyzk+oHGEhbRI/mcYRwZEEJ/hKS7lEe94c18bqvIgct0w/y9Wxc6LWHy9aq2/ra8I/p5B1FW3hmU4dlzoWUuAuYTU6gM8aT4S1UMw8JGeYbz7BqpphEl6vG01/VQeftoLapGXjvg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790803; c=relaxed/simple; bh=//lvZcgVxWAuEEA3XDGiToePWRSnH3bkVOU2t/uuiIc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jXYT1BW/fvzCHTCGONIYDOOSCVP72l08ytx0GFxE50lhD7NLfyfK4cJXGSfEYPXFU/hUahOwIHuHZOzrgKx1lmyrsq8vL6CF44viqpox5NPKhRe7Zw9xuhhmxGBrxdJSq3IMs8wi2d1IoD/FY+bKkW8LHcWktDh6ZVmrTQwYzyQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Cb4iDmJt; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Cb4iDmJt" Received: by smtp.kernel.org (Postfix) with ESMTPS id 15470C4CEF4; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755790803; bh=//lvZcgVxWAuEEA3XDGiToePWRSnH3bkVOU2t/uuiIc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Cb4iDmJtkvpsfcraaWTJZwH7A20AGhAqlH073Mpqv/DpHXKx6KOthBtxZsP7jYcoN N9txmEQVcmHsGM3lvrG2hxAVZxi7cAEJkashq8lOwFu6MnimEMXSvZYok+QnJPpRdN KtQZG3PqG73FS2zxJ+pXF7OpRSqF3MbWDtmsl/aoJCNWZw2fVikSrQDXCvpue7n0G7 7a/eYQktIOEzlS+4ffvts5dttKR7ZUILF9zi4iF7p73K54URX/LfCuWhnAswA2/jT+ IG2HwJfU2uiHJxYilgNp7NZA00vSUdTfuFEzYqOUzyP5/245W3MfKmQ8p5m/zsaqpm jpny5O8dALkvg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01B64CA0EFC; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) From: Sven Peter Date: Thu, 21 Aug 2025 15:38:53 +0000 Subject: [PATCH RFC 01/22] dt-bindings: usb: snps,dwc3: Allow multiple iommus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-1-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=707; i=sven@kernel.org; h=from:subject:message-id; bh=//lvZcgVxWAuEEA3XDGiToePWRSnH3bkVOU2t/uuiIc=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy2/nG0SnPma7s+1u9jC+KO32S4AWrnn8X92R/kFnUn 2z0xmB1RykLgxgHg6yYIsv2/famTx6+EVy66dJ7mDmsTCBDGLg4BWAiD7oY/koEWFjGfok9kx3/ k3v65I0bfsR5Ji8oqNnHKmv2waD6PwvD/+qt78+F3JXaOeHTz5Ji7xnMT1MXKv9Yqbvl3YXZ3vw +zzgA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Apple's dwc3 variant requires two iommus. Signed-off-by: Sven Peter --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documen= tation/devicetree/bindings/usb/snps,dwc3.yaml index 4380bb6fa2f08a475b557e80467abc2861f622e2..6d35dcc605c01977f4fc6fdb6f1= 2976f1cef2b9e 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -60,7 +60,7 @@ properties: dma-coherent: true =20 iommus: - maxItems: 1 + maxItems: 2 =20 power-domains: description: --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7A151278751; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790803; cv=none; b=bc7I93AF7RCCzWoqenypCwoeIovA/IhcxTyz53u5DsBeyJsj06Z+dO71vme4nlAILjs9oG2RCsuZ6ZDyfkOEjZ73sWfFDQqG1rhpKJengY3WBujsjPVrlLB8MhXNorioWCET5AOwOIt02EnrtlYITIotwJNaXU1SUERElqfiVCE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790803; c=relaxed/simple; bh=KhK3tFPXEaW8oRX7V89m4hRJe9gH2p2NAg0H4Auc1J0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=u+idsAMOrq5QSSaawFsoquAHcO9WPLeLbcWNxEzZzWj0BohiWO5JDU9WeTTrt8WKWgwYdOqiRHpeU//usXVd3V8r1G35C0QLWrtD//06jldii67isprNVr76VS5bR99GV1wRDwFWlrdHUSyY6dxbsCGdfQIWgxAw2uZViTnBjaM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TY1C7k6m; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TY1C7k6m" Received: by smtp.kernel.org (Postfix) with ESMTPS id 1E9BAC4AF0B; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755790803; bh=KhK3tFPXEaW8oRX7V89m4hRJe9gH2p2NAg0H4Auc1J0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TY1C7k6mAmNysKSRRxeYibJWfICSrik07eeIUlSOPDzLpLvUbrhByyFuL5BBsXLbJ fw8l216o7DARUWuwsv5LzgMggLTFipK2/RXH8dFAzjA+jwExXE4RVGIwEQF8Rc/rqC 83i3XyiGEx86cZVrt5xswqXyvXpttJRrm6zCVN3unsGlq2UwBLMvxc6yYNDd9oHDAN DFBp5sX/JcFmNhZbwN00l1Q8dDz3oRGM3+ix+kXnw48AqTPv9JJ5gbFCP6TgbXmdv2 iHo89eS5pZ2I7RYwTSEP3hPRVu17ByGv8eRoILr6+cRGSpKKX/QuPSA4KxmjyfewWL OsNTZA7gSE7pQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FF9CCA0EEB; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) From: Sven Peter Date: Thu, 21 Aug 2025 15:38:54 +0000 Subject: [PATCH RFC 02/22] dt-bindings: usb: Add Apple dwc3 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-2-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3081; i=sven@kernel.org; h=from:subject:message-id; bh=KhK3tFPXEaW8oRX7V89m4hRJe9gH2p2NAg0H4Auc1J0=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy2wXG8elX/z7wf6pRNDWlUGz1Lavf3wXntPbXsL/Jt qvav1y3o5SFQYyDQVZMkWX7fnvTJw/fCC7ddOk9zBxWJpAhDFycAjCRBYUM/xMniTx1iDprul9L btaFe48znky+dG2yUJPMcmsRV2mLFUUM/+sbU98riQeZlR2oeVjyYaLWA86evHlV///c7r+50lZ BjAkA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Apple Silicon uses Synopsys DesignWare dwc3 based USB controllers for their Type-C ports. Signed-off-by: Sven Peter --- .../devicetree/bindings/usb/apple,dwc3.yaml | 82 ++++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 83 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/apple,dwc3.yaml b/Docume= ntation/devicetree/bindings/usb/apple,dwc3.yaml new file mode 100644 index 0000000000000000000000000000000000000000..dfea726a6c053ad0c8f3d973a95= b45bbf1724234 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/apple,dwc3.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/apple,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple Silicon DWC3 USB controller + +maintainers: + - Sven Peter + +description: + Apple Silicon SoCs use a Synopsys DesignWare DWC3 based controller for e= ach of + their Type-C ports. + + The common content of the node is defined in snps,dwc3.yaml. + +allOf: + - $ref: snps,dwc3.yaml# + +select: + properties: + compatible: + contains: + const: apple,t8103-dwc3 + required: + - compatible + +properties: + compatible: + oneOf: + - items: + - enum: + - apple,t6000-dwc3 + - apple,t6020-dwc3 + - apple,t8112-dwc3 + - const: apple,t8103-dwc3 + - const: snps,dwc3 + - items: + - const: apple,t8103-dwc3 + - const: snps,dwc3 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + iommus: + maxItems: 2 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + - iommus + - resets + - power-domains + +examples: + - | + #include + #include + + usb@82280000 { + compatible =3D "apple,t8103-dwc3", "snps,dwc3"; + reg =3D <0x82280000 0x10000>; + interrupts =3D ; + iommus =3D <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + }; diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa45799dfe07de2f54de6d6a1ce0615..0e085cb0762f765958d67be61ae= 0d3d773503431 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2399,6 +2399,7 @@ F: Documentation/devicetree/bindings/power/reset/appl= e,smc-reboot.yaml F: Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml F: Documentation/devicetree/bindings/spi/apple,spi.yaml F: Documentation/devicetree/bindings/spmi/apple,spmi.yaml +F: Documentation/devicetree/bindings/usb/apple,dwc3.yaml F: Documentation/devicetree/bindings/watchdog/apple,wdt.yaml F: arch/arm64/boot/dts/apple/ F: drivers/bluetooth/hci_bcm4377.c --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96428278E63; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-3-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7858; i=sven@kernel.org; h=from:subject:message-id; bh=ZBquEoju0Ehd8uVDnoJAdyF7CKQqE2ec9LJ2isJ/Imo=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy20X6NQ1LN35NFuTu+Hlz8SvjC1Uvmf8Urvr52lP91 KOvytv4O0pZGMQ4GGTFFFm277c3ffLwjeDSTZfew8xhZQIZwsDFKQATKa5jZJjOvEmyWz2/xezy ooDavK/H3+9eUyTU9rdv42t90Xu6iZ8YGRY8uDNv7651G05EGjm4yqz6abI+ZbmVd1Z0VtWFI7+ vSXMBAA== X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Apple's Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x, USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon SoCs. The PHY handles muxing between these different protocols and also provides the reset controller for the attached dwc3 USB controller. Signed-off-by: Sven Peter --- .../devicetree/bindings/phy/apple,atcphy.yaml | 210 +++++++++++++++++= ++++ MAINTAINERS | 1 + 2 files changed, 211 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/apple,atcphy.yaml b/Docu= mentation/devicetree/bindings/phy/apple,atcphy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..eb14010557c94f313b54b528e2d= 4039fe540062a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/apple,atcphy.yaml @@ -0,0 +1,210 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/apple,atcphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple Type-C PHY (ATCPHY) + +maintainers: + - Sven Peter + +description: + The Apple Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x, + USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon So= Cs. + + The PHY handles muxing between these different protocols and also provid= es the + reset controller for the attached dwc3 USB controller. + + The PHY is designed for USB4 operation and does not handle individual + differential pairs as distinct DisplayPort lanes. Any reference to lane = in + this binding hence refers to two differential pairs (RX and TX) as used = in USB + terminology. + +properties: + compatible: + enum: + - apple,t6000-atcphy + - apple,t6000-atcphy-dp-only # PHY hardwired to DP-to-HDMI converter= on M2 Pro MacBook + - apple,t6020-atcphy + - apple,t8103-atcphy + - apple,t8112-atcphy + + reg: + minItems: 5 + maxItems: 5 + + reg-names: + items: + - const: core + - const: lpdptx + - const: axi2af + - const: usb2phy + - const: pipehandler + + "#phy-cells": + const: 1 + + "#reset-cells": + const: 0 + + orientation-switch: + type: boolean + description: + The PHY handles swapping lanes if the Type-C connector is flipped. + + mode-switch: + type: boolean + description: + The PHY handles muxing between USB 2.0, USB 3.x, USB4/Thunderbolt, a= nd DisplayPort. + + power-domains: + minItems: 1 + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Output endpoint of the PHY to the Type-C connector + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB3 controller + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the DisplayPort controller + + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Incoming endpoint from the USB4/Thunderbolt controller + + apple,tunable-axi2af: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + AXI2AF tunables. + + This array is filled with 3-tuples each containing three 32-bit valu= es + , , and by the bootloader. + The driver will use these to configure the PHY by reading from each + register, ANDing it with , ORing it with , and storing = the + result back to the register. + These values slightly differ even between different chips of the same + generation and are likely calibration values determined by Apple at + manufacturing time. + + apple,tunable-common: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Common tunables required for all modes, see apple,tunable-axi2af for= details. + + apple,tunable-fuses: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Fuse based tunables required for all modes, see apple,tunable-axi2af= for details. + + apple,tunable-lane0-usb: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + USB tunables on lane 0, see apple,tunable-axi2af for details. + + apple,tunable-lane1-usb: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + USB tunables on lane 1, see apple,tunable-axi2af for details. + + apple,tunable-lane0-cio: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + USB4/Thunderbolt ("converged IO") tunables on lane 0, see apple,tuna= ble-axi2af for details. + + apple,tunable-lane1-cio: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + USB4/Thunderbolt ("converged IO") tunables on lane 1, see apple,tuna= ble-axi2af for details. + + apple,tunable-lane0-dp: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + DisplayPort tunables on lane 0, see apple,tunable-axi2af for details. + + Note that lane here refers to a USB RX and TX pair re-used for Displ= ayPort + and not to an individual DisplayPort differential lane. + + apple,tunable-lane1-dp: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + DisplayPort tunables on lane 1, see apple,tunable-axi2af for details. + + Note that lane here refers to a USB RX and TX pair re-used for Displ= ayPort + and not to an individual DisplayPort differential lane. + +required: + - compatible + - reg + - reg-names + - "#phy-cells" + - "#reset-cells" + - orientation-switch + - mode-switch + +additionalProperties: false + +examples: + - | + phy@383000000 { + compatible =3D "apple,t8103-atcphy"; + reg =3D <0x3 0x83000000 0x0 0x4c000>, + <0x3 0x83050000 0x0 0x8000>, + <0x3 0x80000000 0x0 0x4000>, + <0x3 0x82a90000 0x0 0x4000>, + <0x3 0x82a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&ps_atc0_usb>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + endpoint { + remote-endpoint =3D <&typec_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + + endpoint { + remote-endpoint =3D <&dwc3_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + endpoint { + remote-endpoint =3D <&dcp_dp_out>; + }; + }; + + port@3 { + reg =3D <3>; + + endpoint { + remote-endpoint =3D <&acio_tbt_out>; + }; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 0e085cb0762f765958d67be61ae0d3d773503431..11a9b084a2e51d7b9b2e4c1777a= 2439df4a6858b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2393,6 +2393,7 @@ F: Documentation/devicetree/bindings/nvme/apple,nvme-= ans.yaml F: Documentation/devicetree/bindings/nvmem/apple,efuses.yaml F: Documentation/devicetree/bindings/nvmem/apple,spmi-nvmem.yaml F: Documentation/devicetree/bindings/pci/apple,pcie.yaml +F: Documentation/devicetree/bindings/phy/apple,atcphy.yaml F: Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml F: Documentation/devicetree/bindings/power/apple* F: Documentation/devicetree/bindings/power/reset/apple,smc-reboot.yaml --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0623280324; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-4-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8338; i=sven@kernel.org; h=from:subject:message-id; bh=a5iByOwmuIst1Br18o+6QngL0G+1LuBDoKuObEUxjUA=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy28VH+d89+XTrz3pPE9mDy1KzVPocVvPxzWGfX5HYd 2WXoHB5RykLgxgHg6yYIsv2/famTx6+EVy66dJ7mDmsTCBDGLg4BWAimYsZ/icnpUZm3Xe4mjS5 +Qorx6RFOncyV62PZsn4Vr90Q9eUf3sYGV7/vlLVzCxi77rda0qeT+LUSXcTGGyNZA5oTRPuO8e +iQUA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 As mad as it sounds, the dwc3 controller present on the Apple M1 must be reset and reinitialized whenever a device is unplugged from the root port or when the PHY mode is changed. This is required for at least the following reasons: - The USB2 D+/D- lines are connected through a stateful eUSB2 repeater which in turn is controlled by a variant of the TI TPS6598x USB PD chip. When the USB PD controller detects a hotplug event it resets the eUSB2 repeater. Afterwards, no new device is recognized before the DWC3 core and PHY are reset as well because the eUSB2 repeater and the PHY/dwc3 block disagree about the current state. - It's possible to completely break the dwc3 controller by switching it to device mode and unplugging the cable at just the wrong time. If this happens dwc3 behaves as if no device is connected. CORESOFTRESET will also never clear after it has been set. The only workaround is to trigger a hard reset of the entire dwc3 core with its external reset line. - Whenever the PHY mode is changed (to e.g. transition to DisplayPort alternate mode or USB4) dwc3 has to be shutdown and reinitialized. Otherwise the Type-C port will not be usable until the entire SoC has been reset. All of this can be easily worked around by respecting transitions to USB_ROLE_NONE and making sure the external reset line is asserted when switching roles. We additionally have to ensure that the PHY is suspended during init. Signed-off-by: Sven Peter --- drivers/usb/dwc3/core.c | 61 +++++++++++++++++++++++++++++++++++++++++++++= ---- drivers/usb/dwc3/core.h | 3 +++ drivers/usb/dwc3/drd.c | 11 ++++++++- drivers/usb/dwc3/host.c | 3 ++- 4 files changed, 72 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 8002c23a5a02acb8f3e87b2662a53998a4cf4f5c..26aa507a738f001409a97ef563c= 6561433a1cac5 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -158,6 +158,9 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool i= gnore_susphy) dwc->current_dr_role =3D mode; } =20 +static void dwc3_core_exit(struct dwc3 *dwc); +static int dwc3_core_init_for_resume(struct dwc3 *dwc); + static void __dwc3_set_mode(struct work_struct *work) { struct dwc3 *dwc =3D work_to_dwc(work); @@ -177,7 +180,7 @@ static void __dwc3_set_mode(struct work_struct *work) if (dwc->current_dr_role =3D=3D DWC3_GCTL_PRTCAP_OTG) dwc3_otg_update(dwc, 0); =20 - if (!desired_dr_role) + if (!desired_dr_role && !dwc->role_switch_reset_quirk) goto out; =20 if (desired_dr_role =3D=3D dwc->current_dr_role) @@ -205,13 +208,32 @@ static void __dwc3_set_mode(struct work_struct *work) break; } =20 + if (dwc->role_switch_reset_quirk) { + if (dwc->current_dr_role) { + dwc->current_dr_role =3D 0; + dwc3_core_exit(dwc); + } + + if (desired_dr_role) { + ret =3D dwc3_core_init_for_resume(dwc); + if (ret) { + dev_err(dwc->dev, + "failed to reinitialize core\n"); + goto out; + } + } else { + goto out; + } + } + /* * When current_dr_role is not set, there's no role switching. * Only perform GCTL.CoreSoftReset when there's DRD role switching. */ - if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || + if (dwc->role_switch_reset_quirk || + (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || DWC3_VER_IS_PRIOR(DWC31, 190A)) && - desired_dr_role !=3D DWC3_GCTL_PRTCAP_OTG)) { + desired_dr_role !=3D DWC3_GCTL_PRTCAP_OTG))) { reg =3D dwc3_readl(dwc->regs, DWC3_GCTL); reg |=3D DWC3_GCTL_CORESOFTRESET; dwc3_writel(dwc->regs, DWC3_GCTL, reg); @@ -1372,6 +1394,9 @@ static int dwc3_core_init(struct dwc3 *dwc) if (ret) goto err_exit_phy; =20 + if (dwc->role_switch_reset_quirk) + dwc3_enable_susphy(dwc, true); + dwc3_core_setup_global_control(dwc); dwc3_core_num_eps(dwc); =20 @@ -1635,6 +1660,18 @@ static int dwc3_core_init_mode(struct dwc3 *dwc) ret =3D dwc3_drd_init(dwc); if (ret) return dev_err_probe(dev, ret, "failed to initialize dual-role\n"); + + /* + * If the role switch reset quirk is required the first role + * switch notification will initialize the core such that we + * have to shut it down here. Make sure that the __dwc3_set_mode + * queued by dwc3_drd_init has completed before since it + * may still try to access MMIO. + */ + if (dwc->role_switch_reset_quirk) { + flush_work(&dwc->drd_work); + dwc3_core_exit(dwc); + } break; default: dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode); @@ -2223,6 +2260,22 @@ int dwc3_core_probe(const struct dwc3_probe_data *da= ta) goto err_put_psy; } =20 + if (dev->of_node) { + if (of_device_is_compatible(dev->of_node, "apple,t8103-dwc3")) { + if (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) || + !IS_ENABLED(CONFIG_USB_DWC3_DUAL_ROLE)) { + dev_err(dev, + "Apple DWC3 requires role switch support.\n" + ); + ret =3D -EINVAL; + goto err_put_psy; + } + + dwc->dr_mode =3D USB_DR_MODE_OTG; + dwc->role_switch_reset_quirk =3D true; + } + } + ret =3D reset_control_deassert(dwc->reset); if (ret) goto err_put_psy; @@ -2391,7 +2444,6 @@ static void dwc3_remove(struct platform_device *pdev) dwc3_core_remove(platform_get_drvdata(pdev)); } =20 -#ifdef CONFIG_PM static int dwc3_core_init_for_resume(struct dwc3 *dwc) { int ret; @@ -2418,6 +2470,7 @@ static int dwc3_core_init_for_resume(struct dwc3 *dwc) return ret; } =20 +#ifdef CONFIG_PM static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg) { u32 reg; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index d5b985fa12f4d9ee3f318ea5cce7c1b225cd3623..38f32f2a6193c1b2662ab4f38f4= d20cf4b0e198d 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1154,6 +1154,7 @@ struct dwc3_scratchpad_array { * @suspended: set to track suspend event due to U3/L2. * @susphy_state: state of DWC3_GUSB2PHYCFG_SUSPHY + DWC3_GUSB3PIPECTL_SUS= PHY * before PM suspend. + * @role_switch_reset_quirk: set to force reinitialization after any role = switch * @imod_interval: set the interrupt moderation interval in 250ns * increments or 0 to disable. * @max_cfg_eps: current max number of IN eps used across all USB configs. @@ -1392,6 +1393,8 @@ struct dwc3 { unsigned suspended:1; unsigned susphy_state:1; =20 + unsigned role_switch_reset_quirk:1; + u16 imod_interval; =20 int max_cfg_eps; diff --git a/drivers/usb/dwc3/drd.c b/drivers/usb/dwc3/drd.c index 7977860932b142924edd19f859f7c4041d11eda6..65450db91bdea00bb30bfb368f5= 195ad2fd58da4 100644 --- a/drivers/usb/dwc3/drd.c +++ b/drivers/usb/dwc3/drd.c @@ -464,6 +464,9 @@ static int dwc3_usb_role_switch_set(struct usb_role_swi= tch *sw, break; } =20 + if (dwc->role_switch_reset_quirk && role =3D=3D USB_ROLE_NONE) + mode =3D 0; + dwc3_set_mode(dwc, mode); return 0; } @@ -492,6 +495,10 @@ static enum usb_role dwc3_usb_role_switch_get(struct u= sb_role_switch *sw) role =3D USB_ROLE_DEVICE; break; } + + if (dwc->role_switch_reset_quirk && !dwc->current_dr_role) + role =3D USB_ROLE_NONE; + spin_unlock_irqrestore(&dwc->lock, flags); return role; } @@ -502,7 +509,9 @@ static int dwc3_setup_role_switch(struct dwc3 *dwc) u32 mode; =20 dwc->role_switch_default_mode =3D usb_get_role_switch_default_mode(dwc->d= ev); - if (dwc->role_switch_default_mode =3D=3D USB_DR_MODE_HOST) { + if (dwc->role_switch_reset_quirk) { + mode =3D 0; + } else if (dwc->role_switch_default_mode =3D=3D USB_DR_MODE_HOST) { mode =3D DWC3_GCTL_PRTCAP_HOST; } else { dwc->role_switch_default_mode =3D USB_DR_MODE_PERIPHERAL; diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c index 1c513bf8002ec9ec91b41bfd096cbd0da1dd2d2e..f7a71e6f9d80aca632f1f970d90= 0a3de8a76f0a7 100644 --- a/drivers/usb/dwc3/host.c +++ b/drivers/usb/dwc3/host.c @@ -223,7 +223,8 @@ void dwc3_host_exit(struct dwc3 *dwc) if (dwc->sys_wakeup) device_init_wakeup(&dwc->xhci->dev, false); =20 - dwc3_enable_susphy(dwc, false); + if (!dwc->role_switch_reset_quirk) + dwc3_enable_susphy(dwc, false); platform_device_unregister(dwc->xhci); dwc->xhci =3D NULL; } --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E71FB2BE7D9; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-5-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2484; i=sven@kernel.org; h=from:subject:message-id; bh=K4xGHgVuy+gCBsZ5+L/7Ixe1BRKZmb/9H0zcphQVQWY=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy26XL+h6aXW/svSIoXp77ec99t4L5FxRE9iT+zz8Sv zhiwRuPjlIWBjEOBlkxRZbt++1Nnzx8I7h006X3MHNYmUCGMHBxCsBEtgkwMvwx/5Zrkv990taN vudNDv9UPxd3rKY64paVQMfvQ4/PLU1l+Gd1L/hZwftLj6zC8xxPRr+ZtPYtr82Ze3sXXmI6wiC 9XIkHAA== X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Janne Grunau It results in SErrors during init presumedly because MMIO accesses fail while certain parts are shutdown. Signed-off-by: Janne Grunau Signed-off-by: Sven Peter --- drivers/usb/dwc3/core.c | 1 + drivers/usb/dwc3/core.h | 2 ++ drivers/usb/dwc3/host.c | 5 ++++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 26aa507a738f001409a97ef563c6561433a1cac5..8d2dc7fa18114102cc8893c4ca0= e745e16f30754 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -2273,6 +2273,7 @@ int dwc3_core_probe(const struct dwc3_probe_data *dat= a) =20 dwc->dr_mode =3D USB_DR_MODE_OTG; dwc->role_switch_reset_quirk =3D true; + dwc->no_early_roothub_poweroff =3D true; } } =20 diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 38f32f2a6193c1b2662ab4f38f4d20cf4b0e198d..3c3a36ec37345b2f9e71444ba3b= 90b52dbd24443 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1155,6 +1155,7 @@ struct dwc3_scratchpad_array { * @susphy_state: state of DWC3_GUSB2PHYCFG_SUSPHY + DWC3_GUSB3PIPECTL_SUS= PHY * before PM suspend. * @role_switch_reset_quirk: set to force reinitialization after any role = switch + * @no_early_roothub_poweroff: set to skip early root hub port power off * @imod_interval: set the interrupt moderation interval in 250ns * increments or 0 to disable. * @max_cfg_eps: current max number of IN eps used across all USB configs. @@ -1394,6 +1395,7 @@ struct dwc3 { unsigned susphy_state:1; =20 unsigned role_switch_reset_quirk:1; + unsigned no_early_roothub_poweroff:1; =20 u16 imod_interval; =20 diff --git a/drivers/usb/dwc3/host.c b/drivers/usb/dwc3/host.c index f7a71e6f9d80aca632f1f970d900a3de8a76f0a7..f7c3a0fc5fe258705311f89c1ba= 11ff599c01afe 100644 --- a/drivers/usb/dwc3/host.c +++ b/drivers/usb/dwc3/host.c @@ -134,8 +134,11 @@ int dwc3_host_init(struct dwc3 *dwc) /* * Some platforms need to power off all Root hub ports immediately after = DWC3 set to host * mode to avoid VBUS glitch happen when xhci get reset later. + * On Apple platforms we must not touch any MMIO yet because dwc3 + * will not work correctly before its PHY has been initialized. */ - dwc3_power_off_all_roothub_ports(dwc); + if (!dwc->no_early_roothub_poweroff) + dwc3_power_off_all_roothub_ports(dwc); =20 irq =3D dwc3_host_get_irq(dwc); if (irq < 0) --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3CC9A2D2493; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-6-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2573; i=sven@kernel.org; h=from:subject:message-id; bh=058aqG9bEa8oe7SO+GMmVlqjGZcjvS/tEo3r4EQvouk=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy2+UC0hd+Bh823r3XcKJ8oEPnnJ3HmfjaXOV2l7ybd 2dpspNjRykLgxgHg6yYIsv2/famTx6+EVy66dJ7mDmsTCBDGLg4BWAij7IYGfq0fz73rlgw8+zH w99XssXN+PqrL/+oTxr39wN3ha5FGaswMvyzSAzbEJJwf1ad3P38q6p3lrSHS6XvVD/GPOHQ5a5 VR3gB X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin Apple's dwc3 is connected to a Type-C PHY which supports multiple protocols (USB2, 3, DisplayPort, Thunderbolt) and has to act as a Type-C protocol mux driven by the PD prot driver (tipd). The mode and mux transitions have to be tightly synchronized with dwc3 bringup and shutdown. To avoid racing PHY (re-)configuration during hotplug or role switch events run the role switching inside dwc3 synchronously instead of relying on a work queue on these controllers. Signed-off-by: Hector Martin [sven: added commit description] Signed-off-by: Sven Peter --- drivers/usb/dwc3/core.c | 6 +++++- drivers/usb/dwc3/core.h | 3 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 8d2dc7fa18114102cc8893c4ca0e745e16f30754..f8013ba2bdc22fa5e719df0841b= 12b84d9465b62 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -317,7 +317,10 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode) dwc->desired_dr_role =3D mode; spin_unlock_irqrestore(&dwc->lock, flags); =20 - queue_work(system_freezable_wq, &dwc->drd_work); + if (dwc->synchronous_drd_switch) + __dwc3_set_mode(&dwc->drd_work); + else + queue_work(system_freezable_wq, &dwc->drd_work); } =20 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type) @@ -2274,6 +2277,7 @@ int dwc3_core_probe(const struct dwc3_probe_data *dat= a) dwc->dr_mode =3D USB_DR_MODE_OTG; dwc->role_switch_reset_quirk =3D true; dwc->no_early_roothub_poweroff =3D true; + dwc->synchronous_drd_switch =3D true; } } =20 diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 3c3a36ec37345b2f9e71444ba3b90b52dbd24443..98e748cc348dfd9de1962c93fcf= 9f6a6690c2388 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -1156,6 +1156,8 @@ struct dwc3_scratchpad_array { * before PM suspend. * @role_switch_reset_quirk: set to force reinitialization after any role = switch * @no_early_roothub_poweroff: set to skip early root hub port power off + * @synchronous_drd_switch: set to perform role switches synchronously ins= tead + * of using a workqueue * @imod_interval: set the interrupt moderation interval in 250ns * increments or 0 to disable. * @max_cfg_eps: current max number of IN eps used across all USB configs. @@ -1396,6 +1398,7 @@ struct dwc3 { =20 unsigned role_switch_reset_quirk:1; unsigned no_early_roothub_poweroff:1; + unsigned synchronous_drd_switch:1; =20 u16 imod_interval; =20 --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 060E22D0620; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-7-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2771; i=sven@kernel.org; h=from:subject:message-id; bh=Ikp6czp+quI9KYT9CWH9WFMemYOvMSa7Gr19hm1ueGQ=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy2xVS+teCv0fd52+62njLwutKT41zZ+O9/bz75wlvL pgvVt/dUcrCIMbBICumyLJ9v73pk4dvBJduuvQeZg4rE8gQBi5OAZjI1B5GhjadZ9FrY78wRmp7 NX++XLy80071lkXGivInUwP1uPbLRDL8T9LQdmuR5mrdu8jPKO/k4vYE4eU37k1duEylI+kKj+o NFgA= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin When tracing Apple's dwc3 driver under our hypervisor and comparing its MMIO access with their kernel debug output these vendor-specific registers have been identified. We don't know exactly what these do or why they are required but without changing these parameters sometimes USB3 devices don't work or take an additional 5 seconds to be recognized. Signed-off-by: Hector Martin Co-developed-by: Sven Peter Signed-off-by: Sven Peter --- drivers/usb/dwc3/core.c | 17 +++++++++++++++++ drivers/usb/dwc3/core.h | 18 ++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f8013ba2bdc22fa5e719df0841b12b84d9465b62..e018e80778cf39a9981d438c7e5= 4534b26cddf63 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1366,6 +1366,23 @@ static int dwc3_core_init(struct dwc3 *dwc) */ dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE); =20 + /* Apply Apple quirks */ + if (of_device_is_compatible(dwc->dev->of_node, "apple,t8103-dwc3")) { + dwc3_writel(dwc->regs, + APPLE_DWC3_CIO_LFPS_OFFSET, + APPLE_DWC3_CIO_LFPS_OFFSET_VALUE); + dwc3_writel(dwc->regs, + APPLE_DWC3_CIO_BW_NGT_OFFSET, + APPLE_DWC3_CIO_BW_NGT_OFFSET_VALUE); + + u32 link_timer =3D dwc3_readl(dwc->regs, APPLE_DWC3_CIO_LINK_TIMER); + + link_timer &=3D ~APPLE_DWC3_CIO_PENDING_HP_TIMER; + link_timer |=3D FIELD_PREP(APPLE_DWC3_CIO_PENDING_HP_TIMER, + APPLE_DWC3_CIO_PENDING_HP_TIMER_VALUE); + dwc3_writel(dwc->regs, APPLE_DWC3_CIO_LINK_TIMER, link_timer); + } + ret =3D dwc3_phy_setup(dwc); if (ret) return ret; diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 98e748cc348dfd9de1962c93fcf9f6a6690c2388..1caa46ca8b2ffb74dd3e58b1741= 22e8f8216dd48 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -181,6 +181,24 @@ =20 #define DWC3_LLUCTL(n) (0xd024 + ((n) * 0x80)) =20 +/* + * Apple Silicon dwc3 vendor-specific registers + * + * These registers were identified by tracing XNU's memory access patterns + * and correlating them with debug output over serial to determine their n= ames. + * We don't exactly know what these do but without these USB3 devices some= times + * don't work. + */ +#define APPLE_DWC3_CIO_LFPS_OFFSET 0xcd38 +#define APPLE_DWC3_CIO_LFPS_OFFSET_VALUE 0xf800f80 + +#define APPLE_DWC3_CIO_BW_NGT_OFFSET 0xcd3c +#define APPLE_DWC3_CIO_BW_NGT_OFFSET_VALUE 0xfc00fc0 + +#define APPLE_DWC3_CIO_LINK_TIMER 0xcd40 +#define APPLE_DWC3_CIO_PENDING_HP_TIMER GENMASK(23, 16) +#define APPLE_DWC3_CIO_PENDING_HP_TIMER_VALUE 0x14 + /* Bit fields */ =20 /* Global SoC Bus Configuration INCRx Register 0 */ --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3D1042D2496; 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a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Right now the interrupt handler first reads all updated status registers and only then clears the interrupts. It's possible that a duplicate interrupt for a changed register or plug state comes in after the interrupts have been processed but before they have been cleared: * plug is inserted, TPS_REG_INT_PLUG_EVENT is set * TPS_REG_INT_EVENT1 is read * tps6598x_handle_plug_event() has run and registered the plug * plug is removed again, TPS_REG_INT_PLUG_EVENT is set (again) * TPS_REG_INT_CLEAR1 is written, TPS_REG_INT_PLUG_EVENT is cleared We then have no plug connected and no pending interrupt but the tipd core still thinks there is a plug. It's possible to trigger this with e.g. a slightly broken Type-C to USB A converter. Fix this by first clearing the interrupts and only then reading the updated registers. Fixes: 45188f27b3d0 ("usb: typec: tipd: Add support for Apple CD321X") Fixes: 0a4c005bd171 ("usb: typec: driver for TI TPS6598x USB Power Delivery= controllers") Cc: stable@kernel.org Signed-off-by: Sven Peter Reviewed-by: Heikki Krogerus --- drivers/usb/typec/tipd/core.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index dcf141ada07812295a6f07e41d77f95f98116010..1c80296c3b273e24ceacb3feff4= 32c4f6e6835cc 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -545,24 +545,23 @@ static irqreturn_t cd321x_interrupt(int irq, void *da= ta) if (!event) goto err_unlock; =20 + tps6598x_write64(tps, TPS_REG_INT_CLEAR1, event); + if (!tps6598x_read_status(tps, &status)) - goto err_clear_ints; + goto err_unlock; =20 if (event & APPLE_CD_REG_INT_POWER_STATUS_UPDATE) if (!tps6598x_read_power_status(tps)) - goto err_clear_ints; + goto err_unlock; =20 if (event & APPLE_CD_REG_INT_DATA_STATUS_UPDATE) if (!tps6598x_read_data_status(tps)) - goto err_clear_ints; + goto err_unlock; =20 /* Handle plug insert or removal */ if (event & APPLE_CD_REG_INT_PLUG_EVENT) tps6598x_handle_plug_event(tps, status); =20 -err_clear_ints: - tps6598x_write64(tps, TPS_REG_INT_CLEAR1, event); - err_unlock: mutex_unlock(&tps->lock); =20 @@ -668,25 +667,24 @@ static irqreturn_t tps6598x_interrupt(int irq, void *= data) if (!(event1[0] | event1[1] | event2[0] | event2[1])) goto err_unlock; =20 + tps6598x_block_write(tps, TPS_REG_INT_CLEAR1, event1, intev_len); + tps6598x_block_write(tps, TPS_REG_INT_CLEAR2, event2, intev_len); + if (!tps6598x_read_status(tps, &status)) - goto err_clear_ints; + goto err_unlock; =20 if ((event1[0] | event2[0]) & TPS_REG_INT_POWER_STATUS_UPDATE) if (!tps6598x_read_power_status(tps)) - goto err_clear_ints; + goto err_unlock; =20 if ((event1[0] | event2[0]) & TPS_REG_INT_DATA_STATUS_UPDATE) if (!tps6598x_read_data_status(tps)) - goto err_clear_ints; + goto err_unlock; =20 /* Handle plug insert or removal */ if ((event1[0] | event2[0]) & TPS_REG_INT_PLUG_EVENT) tps6598x_handle_plug_event(tps, status); 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Thu, 21 Aug 2025 15:40:03 +0000 (UTC) From: Sven Peter Date: Thu, 21 Aug 2025 15:39:01 +0000 Subject: [PATCH RFC 09/22] usb: typec: tipd: Move initial irq mask to tipd_data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-9-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3168; i=sven@kernel.org; h=from:subject:message-id; bh=eKL7OgN/DvasHSMHY1JVLFsa5OJf2n5Y1v/SsiTf9mc=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy29X37j8tXW0dVX/4fuKD1QwXrzTmbLzzSqfre/7cg ANRd7KLOkpZGMQ4GGTFFFm277c3ffLwjeDSTZfew8xhZQIZwsDFKQAT+WXMyPDlg+aeFWmbFnVG VHzKC/6to/fT4O6yrr6O3/yLxauu3w1j+CvEr+Aj/2KZ2tLtriqpZ9n6f6mfi3gnvSNV+u7/tPO +CewA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Since the irq mask was originally added more tipd variants have been introduced and there's now struct tipd_data. Move the initial mask in there. Signed-off-by: Sven Peter Reviewed-by: Heikki Krogerus --- drivers/usb/typec/tipd/core.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 1c80296c3b273e24ceacb3feff432c4f6e6835cc..6d8bcbc9cad8a1394e066504d4c= 5ca570edd4e4f 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -112,6 +112,7 @@ struct tps6598x; =20 struct tipd_data { irq_handler_t irq_handler; + u64 irq_mask1; int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); void (*trace_power_status)(u16 status); void (*trace_status)(u32 status); @@ -1298,7 +1299,6 @@ static int tps6598x_probe(struct i2c_client *client) u32 status; u32 vid; int ret; - u64 mask1; =20 tps =3D devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL); if (!tps) @@ -1337,16 +1337,6 @@ static int tps6598x_probe(struct i2c_client *client) if (ret) return ret; =20 - /* CD321X chips have all interrupts masked initially */ - mask1 =3D APPLE_CD_REG_INT_POWER_STATUS_UPDATE | - APPLE_CD_REG_INT_DATA_STATUS_UPDATE | - APPLE_CD_REG_INT_PLUG_EVENT; - - } else { - /* Enable power status, data status and plug event interrupts */ - mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | - TPS_REG_INT_DATA_STATUS_UPDATE | - TPS_REG_INT_PLUG_EVENT; } =20 tps->data =3D i2c_get_match_data(client); @@ -1364,7 +1354,7 @@ static int tps6598x_probe(struct i2c_client *client) return ret; } =20 - ret =3D tps6598x_write64(tps, TPS_REG_INT_MASK1, mask1); + ret =3D tps6598x_write64(tps, TPS_REG_INT_MASK1, tps->data->irq_mask1); if (ret) goto err_reset_controller; =20 @@ -1527,6 +1517,9 @@ static const struct dev_pm_ops tps6598x_pm_ops =3D { =20 static const struct tipd_data cd321x_data =3D { .irq_handler =3D cd321x_interrupt, + .irq_mask1 =3D APPLE_CD_REG_INT_POWER_STATUS_UPDATE | + APPLE_CD_REG_INT_DATA_STATUS_UPDATE | + APPLE_CD_REG_INT_PLUG_EVENT, .register_port =3D tps6598x_register_port, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, @@ -1536,6 +1529,9 @@ static const struct tipd_data cd321x_data =3D { =20 static const struct tipd_data tps6598x_data =3D { .irq_handler =3D tps6598x_interrupt, + .irq_mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | + TPS_REG_INT_DATA_STATUS_UPDATE | + TPS_REG_INT_PLUG_EVENT, .register_port =3D tps6598x_register_port, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, @@ -1546,6 +1542,9 @@ static const struct tipd_data tps6598x_data =3D { =20 static const struct tipd_data tps25750_data =3D { .irq_handler =3D tps25750_interrupt, + .irq_mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | + TPS_REG_INT_DATA_STATUS_UPDATE | + TPS_REG_INT_PLUG_EVENT, .register_port =3D tps25750_register_port, .trace_power_status =3D trace_tps25750_power_status, .trace_status =3D trace_tps25750_status, --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 595BE2D3EE6; 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a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 When support for CD321x was originally added no other hardware variant was supported and there was no need for struct tipd_data. Now that it exists move the special case in there so that we can drop the of_device_is_compatible_check entirely. Signed-off-by: Sven Peter Reviewed-by: Heikki Krogerus --- drivers/usb/typec/tipd/core.c | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 6d8bcbc9cad8a1394e066504d4c5ca570edd4e4f..4815c5c462837865a5f9d37bbc1= 39249c82c2f75 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -118,6 +118,7 @@ struct tipd_data { void (*trace_status)(u32 status); int (*apply_patch)(struct tps6598x *tps); int (*init)(struct tps6598x *tps); + int (*switch_power_state)(struct tps6598x *tps, u8 target_state); int (*reset)(struct tps6598x *tps); }; =20 @@ -1293,7 +1294,6 @@ tps25750_register_port(struct tps6598x *tps, struct f= wnode_handle *fwnode) =20 static int tps6598x_probe(struct i2c_client *client) { - struct device_node *np =3D client->dev.of_node; struct tps6598x *tps; struct fwnode_handle *fwnode; u32 status; @@ -1331,18 +1331,16 @@ static int tps6598x_probe(struct i2c_client *client) if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) tps->i2c_protocol =3D true; =20 - if (np && of_device_is_compatible(np, "apple,cd321x")) { - /* Switch CD321X chips to the correct system power state */ - ret =3D cd321x_switch_power_state(tps, TPS_SYSTEM_POWER_STATE_S0); - if (ret) - return ret; - - } - tps->data =3D i2c_get_match_data(client); if (!tps->data) return -EINVAL; =20 + if (tps->data->switch_power_state) { + ret =3D tps->data->switch_power_state(tps, TPS_SYSTEM_POWER_STATE_S0); + if (ret) + return ret; + } + /* Make sure the controller has application firmware running */ ret =3D tps6598x_check_mode(tps); if (ret < 0) @@ -1525,6 +1523,7 @@ static const struct tipd_data cd321x_data =3D { .trace_status =3D trace_tps6598x_status, .init =3D cd321x_init, .reset =3D cd321x_reset, + .switch_power_state =3D cd321x_switch_power_state, }; =20 static const struct tipd_data tps6598x_data =3D { --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42C0B2D29A9; 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a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Some bits inside the CD321x TPS_DATA_STATUS register have a different function compared to the original tipd chip. Add these and introduce a separate trace function to show them correctly. Signed-off-by: Sven Peter Reviewed-by: Heikki Krogerus --- drivers/usb/typec/tipd/core.c | 8 +++++++- drivers/usb/typec/tipd/tps6598x.h | 5 +++++ drivers/usb/typec/tipd/trace.h | 39 +++++++++++++++++++++++++++++++++++= ++++ 3 files changed, 51 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 4815c5c462837865a5f9d37bbc139249c82c2f75..19d713937870304e68325a441b0= de63eb5db3b80 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -114,6 +114,7 @@ struct tipd_data { irq_handler_t irq_handler; u64 irq_mask1; int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); + void (*trace_data_status)(u32 status); void (*trace_power_status)(u16 status); void (*trace_status)(u32 status); int (*apply_patch)(struct tps6598x *tps); @@ -492,7 +493,9 @@ static bool tps6598x_read_data_status(struct tps6598x *= tps) dev_err(tps->dev, "failed to read data status: %d\n", ret); return false; } - trace_tps6598x_data_status(data_status); + + if (tps->data->trace_data_status) + tps->data->trace_data_status(data_status); =20 return true; } @@ -1519,6 +1522,7 @@ static const struct tipd_data cd321x_data =3D { APPLE_CD_REG_INT_DATA_STATUS_UPDATE | APPLE_CD_REG_INT_PLUG_EVENT, .register_port =3D tps6598x_register_port, + .trace_data_status =3D trace_cd321x_data_status, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, .init =3D cd321x_init, @@ -1532,6 +1536,7 @@ static const struct tipd_data tps6598x_data =3D { TPS_REG_INT_DATA_STATUS_UPDATE | TPS_REG_INT_PLUG_EVENT, .register_port =3D tps6598x_register_port, + .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, .apply_patch =3D tps6598x_apply_patch, @@ -1545,6 +1550,7 @@ static const struct tipd_data tps25750_data =3D { TPS_REG_INT_DATA_STATUS_UPDATE | TPS_REG_INT_PLUG_EVENT, .register_port =3D tps25750_register_port, + .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps25750_power_status, .trace_status =3D trace_tps25750_status, .apply_patch =3D tps25750_apply_patch, diff --git a/drivers/usb/typec/tipd/tps6598x.h b/drivers/usb/typec/tipd/tps= 6598x.h index cecb8d11d23972dab0d8c15458b4052af7510b03..03edbb77bbd6d8093b2560db83e= 5913e25d06154 100644 --- a/drivers/usb/typec/tipd/tps6598x.h +++ b/drivers/usb/typec/tipd/tps6598x.h @@ -197,6 +197,11 @@ #define TPS_DATA_STATUS_FORCE_LSX BIT(23) #define TPS_DATA_STATUS_POWER_MISMATCH BIT(24) =20 +/* modified TPS_REG_DATA_STATUS bits for CD321x (and likely also TPS65987D= DK) */ +#define CD321X_DATA_STATUS_HPD_IRQ BIT(14) +#define CD321X_DATA_STATUS_HPD_LEVEL BIT(15) +#define CD321X_DATA_STATUS_USB4_CONNECTION BIT(23) + #define TPS_DATA_STATUS_DP_PIN_ASSIGNMENT_MASK GENMASK(11, 10) #define TPS_DATA_STATUS_DP_PIN_ASSIGNMENT(x) \ TPS_FIELD_GET(TPS_DATA_STATUS_DP_PIN_ASSIGNMENT_MASK, (x)) diff --git a/drivers/usb/typec/tipd/trace.h b/drivers/usb/typec/tipd/trace.h index bea383f2db9de5bbf1804fbad9ee6b134407b932..e9e40425138a01f15e35867f38f= 62e13623dbcec 100644 --- a/drivers/usb/typec/tipd/trace.h +++ b/drivers/usb/typec/tipd/trace.h @@ -217,6 +217,26 @@ { TPS_DATA_STATUS_FORCE_LSX, "FORCE_LSX" }, \ { TPS_DATA_STATUS_POWER_MISMATCH, "POWER_MISMATCH" }) =20 +#define show_cd321x_data_status_flags(data_status) \ + __print_flags(data_status & TPS_DATA_STATUS_FLAGS_MASK, "|", \ + { TPS_DATA_STATUS_DATA_CONNECTION, "DATA_CONNECTION" }, \ + { TPS_DATA_STATUS_UPSIDE_DOWN, "DATA_UPSIDE_DOWN" }, \ + { TPS_DATA_STATUS_ACTIVE_CABLE, "ACTIVE_CABLE" }, \ + { TPS_DATA_STATUS_USB2_CONNECTION, "USB2_CONNECTION" }, \ + { TPS_DATA_STATUS_USB3_CONNECTION, "USB3_CONNECTION" }, \ + { TPS_DATA_STATUS_USB3_GEN2, "USB3_GEN2" }, \ + { TPS_DATA_STATUS_USB_DATA_ROLE, "USB_DATA_ROLE" }, \ + { TPS_DATA_STATUS_DP_CONNECTION, "DP_CONNECTION" }, \ + { TPS_DATA_STATUS_DP_SINK, "DP_SINK" }, \ + { CD321X_DATA_STATUS_HPD_IRQ, "HPD_IRQ" }, \ + { CD321X_DATA_STATUS_HPD_LEVEL, "HPD_LEVEL" }, \ + { TPS_DATA_STATUS_TBT_CONNECTION, "TBT_CONNECTION" }, \ + { TPS_DATA_STATUS_TBT_TYPE, "TBT_TYPE" }, \ + { TPS_DATA_STATUS_OPTICAL_CABLE, "OPTICAL_CABLE" }, \ + { TPS_DATA_STATUS_ACTIVE_LINK_TRAIN, "ACTIVE_LINK_TRAIN" }, \ + { CD321X_DATA_STATUS_USB4_CONNECTION, "USB4" }, \ + { TPS_DATA_STATUS_POWER_MISMATCH, "POWER_MISMATCH" }) + #define show_data_status_dp_pin_assignment(data_status) \ __print_symbolic(TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT(data_status), \ { TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_E, "E" }, \ @@ -388,6 +408,25 @@ TRACE_EVENT(tps6598x_data_status, ) ); =20 +TRACE_EVENT(cd321x_data_status, + TP_PROTO(u32 data_status), + TP_ARGS(data_status), + + TP_STRUCT__entry( + __field(u32, data_status) + ), + + TP_fast_assign( + __entry->data_status =3D data_status; + ), + + TP_printk("%s%s%s", + show_cd321x_data_status_flags(__entry->data_status), + __entry->data_status & TPS_DATA_STATUS_DP_CONNECTION ? ", DP pinout " = : "", + maybe_show_data_status_dp_pin_assignment(__entry->data_status) + ) +); + #endif /* _TPS6598X_TRACE_H_ */ =20 /* This part must be outside protection */ --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8140B2D7818; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790804; cv=none; b=oktwWinLQcCREGeSeoCwtx/H2OM6xI87Lz88ty7YMNBonVMF0sHrrTwexAvyFM+QhSgzGs3jKUVlv58z9NvFYB2tTnkzOtLHF6NdlcVkjpLNdyZsjglVh9bVvStKmrsq0+ffr72F7atto0P8rrmoFlNpI3Drhs1DDUMcwMoKZok= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790804; c=relaxed/simple; bh=ZU/ah4guW5/JR15Fg0P75HIjEN5tcqmapd5/VETG0AI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=q+AsNqw/cvwQnXxgUDpeXIl0lHcXDDBzLDRH2zaydZnxZuG0HnNQZCKVJyOK0TMZLUKnauU1jZGXitzob5eI3IZx4sVIFFuUKbIO33qV7DLigvNH4ohFQlejNrq5MsbeNBXyyCZTLA6AmFayhiGbsQ/1RBrKq1PmhgZCYyAyg80= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WuMm542a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WuMm542a" Received: by smtp.kernel.org (Postfix) with ESMTPS id C0049C4AF12; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755790803; bh=ZU/ah4guW5/JR15Fg0P75HIjEN5tcqmapd5/VETG0AI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WuMm542aqa4sWUYaCtLS66EVjj263bxrB1iBZ0crLF9C1dqnWfp7KL/nnQXL5ZaEO hdWrsS+Ex8PeaLubZkxkJictWcFXOByzJYHU4aTJ6kjawZ8fCs7SkZAQre99kT92h6 DCTJARt9Q3sAptmtO+lRrP9poXaQoRhI1UTcX8V2+lMSRUL1GUw/bHbXu1CbHFM+/w IsnIYcSF/Qbvr7DrEfd2E/hJd9JKZV6VREK6O+fDRTPS/rW/dBMJylWAdTvsDFGSCg 0KTaFwUe6Ea6nwnCm3nSt9jKU9RHMy6JGm2P4GuXUUVRsaKpwP6EUu0xwEzY091Oqx Zz/DPgTqn8jJQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2A43CA0FE7; Thu, 21 Aug 2025 15:40:03 +0000 (UTC) From: Sven Peter Date: Thu, 21 Aug 2025 15:39:04 +0000 Subject: [PATCH RFC 12/22] usb: typec: tipd: Add cd321x struct with separate size Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-12-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3506; i=sven@kernel.org; h=from:subject:message-id; bh=ZU/ah4guW5/JR15Fg0P75HIjEN5tcqmapd5/VETG0AI=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy2w12UnfuHZn8e//ziTqlcUJxIYeFOhQXq5++qbWv2 fuIdpNeRykLgxgHg6yYIsv2/famTx6+EVy66dJ7mDmsTCBDGLg4BWAi0qUM/9PMnm3xKZtX/GXF eZMPDxses89mnidQuTfW6Zd8uyCbjyXDf//lk9PNzhblNnZNmRO3/O88TgOXjS+v2rqe/qY45UC 4PgMA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 We're about to add more fields to struct tps6598x which are only relevant for Apple's CD321x and to ensure that we don't waste memory everywhere for those add a separate struct for cd321x and prepare to allocate more space inside probe. Signed-off-by: Sven Peter Reviewed-by: Heikki Krogerus --- drivers/usb/typec/tipd/core.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 19d713937870304e68325a441b0de63eb5db3b80..51b0f3be8b66a743ddc3ea96c1b= 25f597a1e8f6c 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -113,6 +113,7 @@ struct tps6598x; struct tipd_data { irq_handler_t irq_handler; u64 irq_mask1; + size_t tps_struct_size; int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); void (*trace_data_status)(u32 status); void (*trace_power_status)(u16 status); @@ -148,6 +149,10 @@ struct tps6598x { const struct tipd_data *data; }; =20 +struct cd321x { + struct tps6598x tps; +}; + static enum power_supply_property tps6598x_psy_props[] =3D { POWER_SUPPLY_PROP_USB_TYPE, POWER_SUPPLY_PROP_ONLINE, @@ -1297,18 +1302,24 @@ tps25750_register_port(struct tps6598x *tps, struct= fwnode_handle *fwnode) =20 static int tps6598x_probe(struct i2c_client *client) { + const struct tipd_data *data; struct tps6598x *tps; struct fwnode_handle *fwnode; u32 status; u32 vid; int ret; =20 - tps =3D devm_kzalloc(&client->dev, sizeof(*tps), GFP_KERNEL); + data =3D i2c_get_match_data(client); + if (!data) + return -EINVAL; + + tps =3D devm_kzalloc(&client->dev, data->tps_struct_size, GFP_KERNEL); if (!tps) return -ENOMEM; =20 mutex_init(&tps->lock); tps->dev =3D &client->dev; + tps->data =3D data; =20 tps->reset =3D devm_gpiod_get_optional(tps->dev, "reset", GPIOD_OUT_LOW); if (IS_ERR(tps->reset)) @@ -1334,10 +1345,6 @@ static int tps6598x_probe(struct i2c_client *client) if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) tps->i2c_protocol =3D true; =20 - tps->data =3D i2c_get_match_data(client); - if (!tps->data) - return -EINVAL; - if (tps->data->switch_power_state) { ret =3D tps->data->switch_power_state(tps, TPS_SYSTEM_POWER_STATE_S0); if (ret) @@ -1521,6 +1528,7 @@ static const struct tipd_data cd321x_data =3D { .irq_mask1 =3D APPLE_CD_REG_INT_POWER_STATUS_UPDATE | APPLE_CD_REG_INT_DATA_STATUS_UPDATE | APPLE_CD_REG_INT_PLUG_EVENT, + .tps_struct_size =3D sizeof(struct cd321x), .register_port =3D tps6598x_register_port, .trace_data_status =3D trace_cd321x_data_status, .trace_power_status =3D trace_tps6598x_power_status, @@ -1535,6 +1543,7 @@ static const struct tipd_data tps6598x_data =3D { .irq_mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | TPS_REG_INT_DATA_STATUS_UPDATE | TPS_REG_INT_PLUG_EVENT, + .tps_struct_size =3D sizeof(struct tps6598x), .register_port =3D tps6598x_register_port, .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps6598x_power_status, @@ -1549,6 +1558,7 @@ static const struct tipd_data tps25750_data =3D { .irq_mask1 =3D TPS_REG_INT_POWER_STATUS_UPDATE | TPS_REG_INT_DATA_STATUS_UPDATE | TPS_REG_INT_PLUG_EVENT, + .tps_struct_size =3D sizeof(struct tps6598x), .register_port =3D tps25750_register_port, .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps25750_power_status, --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 815942D8360; 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a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 CD321x supports various alternate modes and stores information once these are entered into separate status registers. Read those when they are active when reading TPS_DATA_STATUS to prepare supporting these. Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 81 +++++++++++++++++++++++++++++++++++++++= +--- 1 file changed, 77 insertions(+), 4 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 51b0f3be8b66a743ddc3ea96c1b25f597a1e8f6c..59d270eb50ea3dc49ad32ff71f8= 354e23c1083c9 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -35,14 +35,19 @@ #define TPS_REG_INT_MASK2 0x17 #define TPS_REG_INT_CLEAR1 0x18 #define TPS_REG_INT_CLEAR2 0x19 -#define TPS_REG_SYSTEM_POWER_STATE 0x20 #define TPS_REG_STATUS 0x1a +#define TPS_REG_SYSTEM_POWER_STATE 0x20 +#define TPS_REG_USB4_STATUS 0x24 +#define TPS_REG_DP_SID_STATUS 0x58 #define TPS_REG_SYSTEM_CONF 0x28 #define TPS_REG_CTRL_CONF 0x29 #define TPS_REG_BOOT_STATUS 0x2D #define TPS_REG_POWER_STATUS 0x3f #define TPS_REG_PD_STATUS 0x40 #define TPS_REG_RX_IDENTITY_SOP 0x48 +#define TPS_REG_CF_VID_STATUS 0x5e +#define TPS_REG_DP_SID_STATUS 0x58 +#define TPS_REG_INTEL_VID_STATUS 0x59 #define TPS_REG_DATA_STATUS 0x5f #define TPS_REG_SLEEP_CONF 0x70 =20 @@ -85,6 +90,31 @@ struct tps6598x_rx_identity_reg { struct usb_pd_identity identity; } __packed; =20 +/* TPS_REG_USB4_STATUS */ +struct tps6598x_usb4_status_reg { + u8 mode_status; + __le32 eudo; + __le32 unknown; +} __packed; + +/* TPS_REG_DP_SID_STATUS */ +struct tps6598x_dp_sid_status_reg { + u8 mode_status; + __le32 status_tx; + __le32 status_rx; + __le32 configure; + __le32 mode_data; +} __packed; + +/* TPS_REG_INTEL_VID_STATUS */ +struct tps6598x_intel_vid_status_reg { + u8 mode_status; + __le32 attention_vdo; + __le16 enter_vdo; + __le16 device_mode; + __le16 cable_mode; +} __packed; + /* Standard Task return codes */ #define TPS_TASK_TIMEOUT 1 #define TPS_TASK_REJECTED 3 @@ -121,6 +151,7 @@ struct tipd_data { int (*apply_patch)(struct tps6598x *tps); int (*init)(struct tps6598x *tps); int (*switch_power_state)(struct tps6598x *tps, u8 target_state); + bool (*read_data_status)(struct tps6598x *tps); int (*reset)(struct tps6598x *tps); }; =20 @@ -151,6 +182,10 @@ struct tps6598x { =20 struct cd321x { struct tps6598x tps; + + struct tps6598x_dp_sid_status_reg dp_sid_status; + struct tps6598x_intel_vid_status_reg intel_vid_status; + struct tps6598x_usb4_status_reg usb4_status; }; =20 static enum power_supply_property tps6598x_psy_props[] =3D { @@ -505,6 +540,41 @@ static bool tps6598x_read_data_status(struct tps6598x = *tps) return true; } =20 +static bool cd321x_read_data_status(struct tps6598x *tps) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + int ret; + + ret =3D tps6598x_read_data_status(tps); + if (ret < 0) + return false; + + if (tps->data_status & TPS_DATA_STATUS_DP_CONNECTION) { + ret =3D tps6598x_block_read(tps, TPS_REG_DP_SID_STATUS, + &cd321x->dp_sid_status, sizeof(cd321x->dp_sid_status)); + if (ret) + dev_err(tps->dev, "Failed to read DP SID Status: %d\n", + ret); + } + + if (tps->data_status & TPS_DATA_STATUS_TBT_CONNECTION) { + ret =3D tps6598x_block_read(tps, TPS_REG_INTEL_VID_STATUS, + &cd321x->intel_vid_status, sizeof(cd321x->intel_vid_status)); + if (ret) + dev_err(tps->dev, "Failed to read Intel VID Status: %d\n", ret); + } + + if (tps->data_status & CD321X_DATA_STATUS_USB4_CONNECTION) { + ret =3D tps6598x_block_read(tps, TPS_REG_USB4_STATUS, + &cd321x->usb4_status, sizeof(cd321x->usb4_status)); + if (ret) + dev_err(tps->dev, + "Failed to read USB4 Status: %d\n", ret); + } + + return true; +} + static bool tps6598x_read_power_status(struct tps6598x *tps) { u16 pwr_status; @@ -565,7 +635,7 @@ static irqreturn_t cd321x_interrupt(int irq, void *data) goto err_unlock; =20 if (event & APPLE_CD_REG_INT_DATA_STATUS_UPDATE) - if (!tps6598x_read_data_status(tps)) + if (!tps->data->read_data_status(tps)) goto err_unlock; =20 /* Handle plug insert or removal */ @@ -614,7 +684,7 @@ static irqreturn_t tps25750_interrupt(int irq, void *da= ta) goto err_clear_ints; =20 if (event[0] & TPS_REG_INT_DATA_STATUS_UPDATE) - if (!tps6598x_read_data_status(tps)) + if (!tps->data->read_data_status(tps)) goto err_clear_ints; =20 /* @@ -688,7 +758,7 @@ static irqreturn_t tps6598x_interrupt(int irq, void *da= ta) goto err_unlock; =20 if ((event1[0] | event2[0]) & TPS_REG_INT_DATA_STATUS_UPDATE) - if (!tps6598x_read_data_status(tps)) + if (!tps->data->read_data_status(tps)) goto err_unlock; =20 /* Handle plug insert or removal */ @@ -1534,6 +1604,7 @@ static const struct tipd_data cd321x_data =3D { .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, .init =3D cd321x_init, + .read_data_status =3D cd321x_read_data_status, .reset =3D cd321x_reset, .switch_power_state =3D cd321x_switch_power_state, }; @@ -1550,6 +1621,7 @@ static const struct tipd_data tps6598x_data =3D { .trace_status =3D trace_tps6598x_status, .apply_patch =3D tps6598x_apply_patch, .init =3D tps6598x_init, + .read_data_status =3D tps6598x_read_data_status, .reset =3D tps6598x_reset, }; =20 @@ -1565,6 +1637,7 @@ static const struct tipd_data tps25750_data =3D { .trace_status =3D trace_tps25750_status, .apply_patch =3D tps25750_apply_patch, .init =3D tps25750_init, + .read_data_status =3D tps6598x_read_data_status, .reset =3D tps25750_reset, }; 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Thu, 21 Aug 2025 15:40:03 +0000 (UTC) From: Sven Peter Date: Thu, 21 Aug 2025 15:39:06 +0000 Subject: [PATCH RFC 14/22] usb: typec: tipd: Register DisplayPort and Thunderbolt altmodes for cd321x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-14-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5612; i=sven@kernel.org; h=from:subject:message-id; bh=7y9x8hEHEH19KOEuvgwq8U5ghcJb+lno5nXbqmMoyEw=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy280yG+TuV3wOdP+vnLqb+fuppvYiRya3CcJaFvc4w +a/L7vdUcrCIMbBICumyLJ9v73pk4dvBJduuvQeZg4rE8gQBi5OAZjI7YmMDB3ua6oZjwqx+Vz4 9tU5cLtjyeNv66cmFQYXvUwznf7tZSTDP2NXM6XHzxt7bmw8kfFUt9GV17xl2s7Dq7VbdC1ULBu KOQE= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Ports equipped with a CD321x are only found on Apple Silicon machines and always support DisplayPort, Thunderbolt and USB4. Register these port modes unconditionally. Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 87 +++++++++++++++++++++++++++++++++++++++= ++-- 1 file changed, 84 insertions(+), 3 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 59d270eb50ea3dc49ad32ff71f8354e23c1083c9..e369897bfa017ca96e559a8bd70= da11207d4513a 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -16,6 +16,8 @@ #include #include #include +#include +#include #include #include #include @@ -145,6 +147,7 @@ struct tipd_data { u64 irq_mask1; size_t tps_struct_size; int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); + void (*unregister_port)(struct tps6598x *tps); void (*trace_data_status)(u32 status); void (*trace_power_status)(u16 status); void (*trace_status)(u32 status); @@ -186,6 +189,9 @@ struct cd321x { struct tps6598x_dp_sid_status_reg dp_sid_status; struct tps6598x_intel_vid_status_reg intel_vid_status; struct tps6598x_usb4_status_reg usb4_status; + + struct typec_altmode *port_altmode_dp; + struct typec_altmode *port_altmode_tbt; }; =20 static enum power_supply_property tps6598x_psy_props[] =3D { @@ -965,6 +971,78 @@ tps6598x_register_port(struct tps6598x *tps, struct fw= node_handle *fwnode) return 0; } =20 +static int cd321x_register_port_altmodes(struct cd321x *cd321x) +{ + struct typec_altmode_desc desc; + struct typec_altmode *amode; + + memset(&desc, 0, sizeof(desc)); + desc.svid =3D USB_TYPEC_DP_SID; + desc.mode =3D USB_TYPEC_DP_MODE; + desc.vdo =3D DP_CONF_SET_PIN_ASSIGN(BIT(DP_PIN_ASSIGN_C) | BIT(DP_PIN_ASS= IGN_D)); + desc.vdo |=3D DP_CAP_DFP_D; + amode =3D typec_port_register_altmode(cd321x->tps.port, &desc); + if (IS_ERR(amode)) + return PTR_ERR(amode); + cd321x->port_altmode_dp =3D amode; + + memset(&desc, 0, sizeof(desc)); + desc.svid =3D USB_TYPEC_TBT_SID; + desc.mode =3D TYPEC_ANY_MODE; + amode =3D typec_port_register_altmode(cd321x->tps.port, &desc); + if (IS_ERR(amode)) { + typec_unregister_altmode(cd321x->port_altmode_dp); + cd321x->port_altmode_dp =3D NULL; + return PTR_ERR(amode); + } + cd321x->port_altmode_tbt =3D amode; + + return 0; +} + +static int +cd321x_register_port(struct tps6598x *tps, struct fwnode_handle *fwnode) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + int ret; + + ret =3D tps6598x_register_port(tps, fwnode); + if (ret) + return ret; + + ret =3D cd321x_register_port_altmodes(cd321x); + if (ret) + goto err_unregister_port; + + typec_set_mode(tps->port, TYPEC_STATE_SAFE); + + return 0; + +err_unregister_port: + typec_unregister_port(tps->port); + return ret; +} + +static void +tps6598x_unregister_port(struct tps6598x *tps) +{ + typec_unregister_port(tps->port); +} + +static void +cd321x_unregister_port(struct tps6598x *tps) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + if (cd321x->port_altmode_dp) + typec_unregister_altmode(cd321x->port_altmode_dp); + if (cd321x->port_altmode_tbt) + typec_unregister_altmode(cd321x->port_altmode_tbt); + cd321x->port_altmode_dp =3D NULL; + cd321x->port_altmode_tbt =3D NULL; + typec_unregister_port(tps->port); +} + static int tps_request_firmware(struct tps6598x *tps, const struct firmwar= e **fw, const char **firmware_name) { @@ -1506,7 +1584,7 @@ static int tps6598x_probe(struct i2c_client *client) err_disconnect: tps6598x_disconnect(tps, 0); err_unregister_port: - typec_unregister_port(tps->port); + tps->data->unregister_port(tps); err_role_put: usb_role_switch_put(tps->role_sw); err_fwnode_put: @@ -1530,7 +1608,7 @@ static void tps6598x_remove(struct i2c_client *client) devm_free_irq(tps->dev, client->irq, tps); =20 tps6598x_disconnect(tps, 0); - typec_unregister_port(tps->port); + tps->data->unregister_port(tps); usb_role_switch_put(tps->role_sw); =20 /* Reset PD controller to remove any applied patch */ @@ -1599,7 +1677,8 @@ static const struct tipd_data cd321x_data =3D { APPLE_CD_REG_INT_DATA_STATUS_UPDATE | APPLE_CD_REG_INT_PLUG_EVENT, .tps_struct_size =3D sizeof(struct cd321x), - .register_port =3D tps6598x_register_port, + .register_port =3D cd321x_register_port, + .unregister_port =3D cd321x_unregister_port, .trace_data_status =3D trace_cd321x_data_status, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, @@ -1616,6 +1695,7 @@ static const struct tipd_data tps6598x_data =3D { TPS_REG_INT_PLUG_EVENT, .tps_struct_size =3D sizeof(struct tps6598x), .register_port =3D tps6598x_register_port, + .unregister_port =3D tps6598x_unregister_port, .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps6598x_power_status, .trace_status =3D trace_tps6598x_status, @@ -1632,6 +1712,7 @@ static const struct tipd_data tps25750_data =3D { TPS_REG_INT_PLUG_EVENT, .tps_struct_size =3D sizeof(struct tps6598x), .register_port =3D tps25750_register_port, + .unregister_port =3D tps6598x_unregister_port, .trace_data_status =3D trace_tps6598x_data_status, .trace_power_status =3D trace_tps25750_power_status, .trace_status =3D trace_tps25750_status, --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70FD52D46B7; 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a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin Whenever the power status is changed make sure to also update the partner identity to be able to detect changes once de-bouncing and mode changes arre added for CD321x. Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index e369897bfa017ca96e559a8bd70da11207d4513a..b0fdd4dddd3a490dbc2a8ced21e= a0803658f36a7 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -636,9 +636,16 @@ static irqreturn_t cd321x_interrupt(int irq, void *dat= a) if (!tps6598x_read_status(tps, &status)) goto err_unlock; =20 - if (event & APPLE_CD_REG_INT_POWER_STATUS_UPDATE) + if (event & APPLE_CD_REG_INT_POWER_STATUS_UPDATE) { if (!tps6598x_read_power_status(tps)) goto err_unlock; + if (TPS_POWER_STATUS_PWROPMODE(tps->pwr_status) =3D=3D TYPEC_PWR_MODE_PD= ) { + if (tps6598x_read_partner_identity(tps)) { + dev_err(tps->dev, "%s: failed to partner identity\n", __func__); + tps->partner_identity =3D (struct usb_pd_identity) {0}; + } + } + } =20 if (event & APPLE_CD_REG_INT_DATA_STATUS_UPDATE) if (!tps->data->read_data_status(tps)) --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C2612E03F1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-16-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1231; i=sven@kernel.org; h=from:subject:message-id; bh=y56aSt+8+GGBv7M4CTBesZmBIVzkBqBitGUe5JAi5T0=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy2237661DTmzwOHm3mbPDcmX2qgs3eK6999ObE5S38 /LNpg8xHaUsDGIcDLJiiizb99ubPnn4RnDppkvvYeawMoEMYeDiFICJOGQyMlyaPP+BF4fSZaXg QtsbrLFT1izcynz27/T9fp5b1A49TbFi+MMz6W6tkv3fle2n4u5t9l4jtl71vu/lBo8+Ye2uw+x +s9kA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin We need the initial power status to be able to reliably detect connector changes once we introduce de-bouncing for CD321x next. read_power_status takes care of this and also forwards the status to the trace subsystem so let's use that instead of open-coding it inside probe. Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index b0fdd4dddd3a490dbc2a8ced21ea0803658f36a7..2b7c5017a347d153b50383b3412= 3a2ecc424eb68 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -1552,11 +1552,8 @@ static int tps6598x_probe(struct i2c_client *client) goto err_role_put; =20 if (status & TPS_STATUS_PLUG_PRESENT) { - ret =3D tps6598x_read16(tps, TPS_REG_POWER_STATUS, &tps->pwr_status); - if (ret < 0) { - dev_err(tps->dev, "failed to read power status: %d\n", ret); + if (!tps6598x_read_power_status(tps)) goto err_unregister_port; - } ret =3D tps6598x_connect(tps, status); if (ret) dev_err(&client->dev, "failed to register partner\n"); --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C0092DFF28; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790804; cv=none; b=qzIMJp34Zu/r2wnzv/YW+9zn5Jfu7ipiz1aYbmqQRwzj8wgnSHdLWNqoHDY+rQglH2+FUaqskGoRw5Zyr21mEGJycHzTL2zTB39Foke2HWHkkIwBiAXIPLvXbaKQnKzHhXZ/R/vqIakwrHB9UNPDhLFdNJIxTxMivCbXFHS84Vs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790804; c=relaxed/simple; bh=983CG/MM3PcL5TC3u/pW2QKWD6qqvQjonF9bKDfHiWU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=tDSjpGuiJrWE1Md2SFn9Nuy50S5NmQPRN6iJNFZk2/fMpDaKrXCxD/5o70BC6EsWhpwBzjQEnlCjCx2qcGJit6CaxgnA4V1cIjAO7oYrHIs52HCZHZpAL87E1ZDLTnz/wMNv01HeAX2IvStOIAxQcLeBBV0UFOT/vj+32+rjxEI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UtZ4GISr; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UtZ4GISr" Received: by smtp.kernel.org (Postfix) with ESMTPS id 115E3C4DDF1; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755790804; bh=983CG/MM3PcL5TC3u/pW2QKWD6qqvQjonF9bKDfHiWU=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=UtZ4GISrLRQy+Ri5tVkjPwREu68Lb90FYK/T6sOy/+DORJGscW+c+VHx83+bWusmm VXT3O/0JYdI1HVw47UGrfSivi2Zm8xAhotj9q//asJYeaDD/0muDrHvVMpHlu5D1bQ X1YnICf4vH5T0RczalmnVb10mC14y0SrBYGhFMQc2lzhqxMyLUHdj77u54vzL1wOLe CygYzLFroCp4pn4YQfxZLV202+sWERFk9ca9VT7euRgpzTLD5V/ROp9mC0y/3iAtER yRjqWNcSD199syP08bcDwpjNS2r7cKDMlzrZRy5hC1DJRYk/1v3KtY/NwBMGPf3yNa MNZ2CYgCEc50g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 012D9CA0FE2; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) From: Sven Peter Date: Thu, 21 Aug 2025 15:39:09 +0000 Subject: [PATCH RFC 17/22] usb: typec: tipd: Read data status in probe and cache its value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-17-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1479; i=sven@kernel.org; h=from:subject:message-id; bh=w4gEKin788lV37T7P3ejSzEd1QqxJ5N159RtspJlYHw=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy293PtrFe1BQWP/vRXeAgT+GkU3W2b+NczGo2eV7zt up74nq0o5SFQYyDQVZMkWX7fnvTJw/fCC7ddOk9zBxWJpAhDFycAjAR91kM//O2n1hQUxEYfLGx sX7rsSpGabXncYsZP/usTD9rMT9R35iR4bHO0kmcCd/XHDfWuefYe7dzv+05v5lTVv+q/1Ecn7I kkRcA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin Just like for power status we also need to keep track of data status to be able to detect mode changes once we introduce de-bouncing for CD321x. Read it during probe and keep a cached copy of its value. Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index 2b7c5017a347d153b50383b34123a2ecc424eb68..bada42fbe59b29a9e864e17644d= a41908a445102 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -177,6 +177,7 @@ struct tps6598x { =20 int wakeup; u32 status; /* status reg */ + u32 data_status; u16 pwr_status; struct delayed_work wq_poll; =20 @@ -539,6 +540,7 @@ static bool tps6598x_read_data_status(struct tps6598x *= tps) dev_err(tps->dev, "failed to read data status: %d\n", ret); return false; } + tps->data_status =3D data_status; =20 if (tps->data->trace_data_status) tps->data->trace_data_status(data_status); @@ -1554,6 +1556,8 @@ static int tps6598x_probe(struct i2c_client *client) if (status & TPS_STATUS_PLUG_PRESENT) { if (!tps6598x_read_power_status(tps)) goto err_unregister_port; + if (!tps->data->read_data_status(tps)) + goto err_unregister_port; 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Thu, 21 Aug 2025 15:40:04 +0000 (UTC) From: Sven Peter Date: Thu, 21 Aug 2025 15:39:10 +0000 Subject: [PATCH RFC 18/22] usb: typec: mux: Introduce data_role to mux state Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-18-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=832; i=sven@kernel.org; h=from:subject:message-id; bh=JRN0Pkcv1Gw9Rq/i5eF+ACOnqAvxuHK0oC9pDd6cKvY=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy233WGZb7kycy/csIv9MoWLJLr6P0mWfg/jSNDxKST q8L0z07SlkYxDgYZMUUWbbvtzd98vCN4NJNl97DzGFlAhnCwMUpABPZOpWRYRk3h9t/k1k257m0 GFvPl7k9vnvu1M5pF6/eV9nQJnT2WCvD/8ItJ1ynXdys4DJ9nmP53TPh5nHccsFrAx2X+30qdlx 8mREA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin Some muxes may need to know the data role that is being switched to, such as to direct the data pins to separate host/device controllers or configure a unified PHY correctly. Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- include/linux/usb/typec_mux.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/linux/usb/typec_mux.h b/include/linux/usb/typec_mux.h index 2489a7857d8e10a73450a66ee85b5068f401f047..89b64ed081aecaa70529aaa7175= 79c0dc7a5f961 100644 --- a/include/linux/usb/typec_mux.h +++ b/include/linux/usb/typec_mux.h @@ -45,6 +45,7 @@ void *typec_switch_get_drvdata(struct typec_switch_dev *s= w); struct typec_mux_state { struct typec_altmode *alt; unsigned long mode; + enum typec_data_role data_role; void *data; }; =20 --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1D842FB61A; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790805; cv=none; b=TJ272OwB0r9n0r/gs+BWjQ0yIisB8ELb7yMtnxyXLZly08/RSbHSDXrWk3VhIQaNVu+d2gnsJTi6cimh2N0YI26yem5n8NcKKr3KjTmbTmfPglpShAOuHnHKjDewIzd24dXzeMKsZoZWPqGd9h9YMoCnjMiCLDGMViC79kODL+o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755790805; c=relaxed/simple; bh=JrKgl9FC81RS9LriNUwHBMZMpDkdku/m0ieHcReczgQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=riR62yqCSeWmU+ZfGYCSaYQ09E21D7ApBO/8nz4BMHYIsS2XiOVl9xcg6ZNTbIWwvUq3U9g5w5/i8YZtq+9LKZWsmlQHazP4KtI5J/6wu+Lwjvq1xungrviawhKPyeN5ZG+8hZI6+uVzX6B6dztfGJZepxJ+k9u4iX2bEtgkl50= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Rn3ORfoe; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Rn3ORfoe" Received: by smtp.kernel.org (Postfix) with ESMTPS id 30385C4CEEB; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755790804; bh=JrKgl9FC81RS9LriNUwHBMZMpDkdku/m0ieHcReczgQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Rn3ORfoe0yJOfpnntCU6be/UTgrm+uzL7NsWJ/Wa2hMBu9Z8s4QoEaygKMMXqOLwX 1R5PQpIY34uPHZxpZqY61tSmQIgxppjKSCltjGxNkQE1uGlvjBWt1FlRLKQkY5jt3e 7l4PVcx8QF4DQK9GH70sv8Ijk+wMhxubBNfWjstPtJFi6V9HvNUrjJ2VQO84Owjzbe g6EprN1VK1KfPogvcwvWYcORkCZ3r1Bc3fizlWY8xQDNHzXIkHihzB6k06Tn//lJiZ fCdypH/4gOn0f3znXDsX7eaaQ3f4k1bdoIhREp9OzmCU9h2PJRWwmFwHqtuntwa6Ok Ng3+MGNIYK4qQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B795CA0FE1; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) From: Sven Peter Date: Thu, 21 Aug 2025 15:39:11 +0000 Subject: [PATCH RFC 19/22] usb: typec: tipd: Handle mode transitions for CD321x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-19-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=16024; i=sven@kernel.org; h=from:subject:message-id; bh=bJqdko/4l7cVZ4e5szSZ9ex2DQ6pDzSFlJsLsj9dEYY=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy2/3rJ7wysUtZF8LWWp9m+zW/u6JyyfZTdjeldoZxt D5N/va1o5SFQYyDQVZMkWX7fnvTJw/fCC7ddOk9zBxWJpAhDFycAjCROeIM/8tl3ac29wj17As0 72+KNZ9xS81G5uz5QLaLe259X9U+/ywjw0fOZU8eW11oOFoXrXf8a+omtshbS+ZGq5ZPCL2+2si ylxsA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 From: Hector Martin On Apple Silicon machines there is no control over which alt mode is chosen. The CD321x' firmware negotiates the target mode on its own and only lets the main CPU know after the mode has already been chosen. Especially after plugging a new cable in this can result to quick mode changes from e.g. power only -> USB3 only -> USB3+DisplayPort in a short time. It is not possile to influence this in any way and we also do not get direct access to the PDOs or VDOs exchanged via USB PD. Additionally, mode changes must be tightly synchronized between DWC3 and the Type C PHY and most mode changes require a full reset of DWC3 to make the port work correctly. On the machines the usb role change is used to reset the controller. The role change is additionally done synchronously from the callback instead of relying on a workqueue as usual in order to avoid any races which can, in the worst case, result in resetting the entire SoC if Type-C PHY and DWC3 are out of sync. To be able to control all this we trigger the entire process in the correct order directly from the TIPD driver and de-bounce any mode changes to avoid tearing down and re-setting DWC3 back up multiple times any time a new connection is made. Signed-off-by: Hector Martin Co-developed-by: Sven Peter Signed-off-by: Sven Peter --- drivers/usb/typec/tipd/core.c | 299 ++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 295 insertions(+), 4 deletions(-) diff --git a/drivers/usb/typec/tipd/core.c b/drivers/usb/typec/tipd/core.c index bada42fbe59b29a9e864e17644da41908a445102..cad6adba131b8289645b1cabadc= 8d4216f0f0eee 100644 --- a/drivers/usb/typec/tipd/core.c +++ b/drivers/usb/typec/tipd/core.c @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -121,6 +122,9 @@ struct tps6598x_intel_vid_status_reg { #define TPS_TASK_TIMEOUT 1 #define TPS_TASK_REJECTED 3 =20 +/* Debounce delay for mode changes, in milliseconds */ +#define CD321X_DEBOUNCE_DELAY_MS 500 + enum { TPS_MODE_APP, TPS_MODE_BOOT, @@ -146,6 +150,7 @@ struct tipd_data { irq_handler_t irq_handler; u64 irq_mask1; size_t tps_struct_size; + void (*remove)(struct tps6598x *tps); int (*register_port)(struct tps6598x *tps, struct fwnode_handle *node); void (*unregister_port)(struct tps6598x *tps); void (*trace_data_status)(u32 status); @@ -156,6 +161,7 @@ struct tipd_data { int (*switch_power_state)(struct tps6598x *tps, u8 target_state); bool (*read_data_status)(struct tps6598x *tps); int (*reset)(struct tps6598x *tps); + int (*connect)(struct tps6598x *tps, u32 status); }; =20 struct tps6598x { @@ -184,6 +190,17 @@ struct tps6598x { const struct tipd_data *data; }; =20 +struct cd321x_status { + u32 status; + u32 pwr_status; + u32 data_status; + u32 status_changed; + struct usb_pd_identity partner_identity; + struct tps6598x_dp_sid_status_reg dp_sid_status; + struct tps6598x_intel_vid_status_reg intel_vid_status; + struct tps6598x_usb4_status_reg usb4_status; +}; + struct cd321x { struct tps6598x tps; =20 @@ -193,6 +210,13 @@ struct cd321x { =20 struct typec_altmode *port_altmode_dp; struct typec_altmode *port_altmode_tbt; + + struct typec_mux *mux; + struct typec_mux_state state; + + struct cd321x_status update_status; + struct delayed_work update_work; + struct usb_pd_identity cur_partner_identity; }; =20 static enum power_supply_property tps6598x_psy_props[] =3D { @@ -614,9 +638,238 @@ static void tps6598x_handle_plug_event(struct tps6598= x *tps, u32 status) } } =20 +static void cd321x_typec_update_mode(struct tps6598x *tps, struct cd321x_s= tatus *st) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + if (st->data_status & TPS_DATA_STATUS_USB_DATA_ROLE) + cd321x->state.data_role =3D TYPEC_DEVICE; + else + cd321x->state.data_role =3D TYPEC_HOST; + + if (!(st->data_status & TPS_DATA_STATUS_DATA_CONNECTION)) { + if (cd321x->state.mode =3D=3D TYPEC_STATE_SAFE) + return; + cd321x->state.alt =3D NULL; + cd321x->state.mode =3D TYPEC_STATE_SAFE; + cd321x->state.data =3D NULL; + typec_mux_set(cd321x->mux, &cd321x->state); + } else if (st->data_status & TPS_DATA_STATUS_DP_CONNECTION) { + struct typec_displayport_data dp_data; + unsigned long mode; + + switch (TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT(st->data_status)) { + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_A: + mode =3D TYPEC_DP_STATE_A; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_B: + mode =3D TYPEC_DP_STATE_B; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_C: + mode =3D TYPEC_DP_STATE_C; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_D: + mode =3D TYPEC_DP_STATE_D; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_E: + mode =3D TYPEC_DP_STATE_E; + break; + case TPS_DATA_STATUS_DP_SPEC_PIN_ASSIGNMENT_F: + mode =3D TYPEC_DP_STATE_F; + break; + default: + dev_err(tps->dev, "Invalid DP pin assignment\n"); + return; + } + + if (cd321x->state.alt =3D=3D cd321x->port_altmode_dp && + cd321x->state.mode =3D=3D mode) { + return; + } + + dp_data.status =3D le32_to_cpu(st->dp_sid_status.status_rx); + dp_data.conf =3D le32_to_cpu(st->dp_sid_status.configure); + cd321x->state.alt =3D cd321x->port_altmode_dp; + cd321x->state.data =3D &dp_data; + cd321x->state.mode =3D mode; + typec_mux_set(cd321x->mux, &cd321x->state); + } else if (st->data_status & TPS_DATA_STATUS_TBT_CONNECTION) { + struct typec_thunderbolt_data tbt_data; + + if (cd321x->state.alt =3D=3D cd321x->port_altmode_tbt && + cd321x->state.mode =3D=3D TYPEC_TBT_MODE) + return; + + tbt_data.cable_mode =3D le16_to_cpu(st->intel_vid_status.cable_mode); + tbt_data.device_mode =3D le16_to_cpu(st->intel_vid_status.device_mode); + tbt_data.enter_vdo =3D le16_to_cpu(st->intel_vid_status.enter_vdo); + cd321x->state.alt =3D cd321x->port_altmode_tbt; + cd321x->state.mode =3D TYPEC_TBT_MODE; + cd321x->state.data =3D &tbt_data; + typec_mux_set(cd321x->mux, &cd321x->state); + } else if (st->data_status & CD321X_DATA_STATUS_USB4_CONNECTION) { + struct enter_usb_data eusb_data; + + if (cd321x->state.alt =3D=3D NULL && cd321x->state.mode =3D=3D TYPEC_MOD= E_USB4) + return; + + eusb_data.eudo =3D le32_to_cpu(st->usb4_status.eudo); + eusb_data.active_link_training =3D + !!(st->data_status & TPS_DATA_STATUS_ACTIVE_LINK_TRAIN); + + cd321x->state.alt =3D NULL; + cd321x->state.data =3D &eusb_data; + cd321x->state.mode =3D TYPEC_MODE_USB4; + typec_mux_set(cd321x->mux, &cd321x->state); + } else { + if (cd321x->state.alt =3D=3D NULL && cd321x->state.mode =3D=3D TYPEC_STA= TE_USB) + return; + cd321x->state.alt =3D NULL; + cd321x->state.mode =3D TYPEC_STATE_USB; + cd321x->state.data =3D NULL; + typec_mux_set(cd321x->mux, &cd321x->state); + } +} + +static void cd321x_update_work(struct work_struct *work) +{ + struct cd321x *cd321x =3D container_of(to_delayed_work(work), + struct cd321x, update_work); + struct tps6598x *tps =3D &cd321x->tps; + struct cd321x_status st; + guard(mutex)(&tps->lock); + + st =3D cd321x->update_status; + cd321x->update_status.status_changed =3D 0; + + bool old_connected =3D !!tps->partner; + bool new_connected =3D st.status & TPS_STATUS_PLUG_PRESENT; + bool was_disconnected =3D st.status_changed & TPS_STATUS_PLUG_PRESENT; + + bool usb_connection =3D st.data_status & + (TPS_DATA_STATUS_USB2_CONNECTION | TPS_DATA_STATUS_USB3_CONNECTIO= N); + + enum usb_role old_role =3D usb_role_switch_get_role(tps->role_sw); + enum usb_role new_role =3D USB_ROLE_NONE; + enum typec_pwr_opmode pwr_opmode =3D TYPEC_PWR_MODE_USB; + enum typec_orientation orientation =3D TYPEC_ORIENTATION_NONE; + + if (usb_connection) { + if (tps->data_status & TPS_DATA_STATUS_USB_DATA_ROLE) + new_role =3D USB_ROLE_DEVICE; + else + new_role =3D USB_ROLE_HOST; + } + + if (new_connected) { + pwr_opmode =3D TPS_POWER_STATUS_PWROPMODE(st.pwr_status); + orientation =3D TPS_STATUS_TO_UPSIDE_DOWN(st.status) ? + TYPEC_ORIENTATION_REVERSE : TYPEC_ORIENTATION_NORMAL; + } + + bool is_pd =3D pwr_opmode =3D=3D TYPEC_PWR_MODE_PD; + bool partner_changed =3D old_connected && new_connected && + (was_disconnected || + (is_pd && memcmp(&st.partner_identity, + &cd321x->cur_partner_identity, sizeof(struct usb_pd_identity)))); + + /* If we are switching from an active role, transition to USB_ROLE_NONE f= irst */ + if (old_role !=3D USB_ROLE_NONE && (new_role !=3D old_role || was_disconn= ected)) + usb_role_switch_set_role(tps->role_sw, USB_ROLE_NONE); + + /* Process partner disconnection or change */ + if (!new_connected || partner_changed) { + if (!IS_ERR(tps->partner)) + typec_unregister_partner(tps->partner); + tps->partner =3D NULL; + } + + /* If there was a disconnection, set PHY to off */ + if (!new_connected || was_disconnected) { + cd321x->state.alt =3D NULL; + cd321x->state.mode =3D TYPEC_STATE_SAFE; + cd321x->state.data =3D NULL; + typec_set_mode(tps->port, TYPEC_STATE_SAFE); + } + + /* Update Type-C properties */ + typec_set_pwr_opmode(tps->port, pwr_opmode); + typec_set_pwr_role(tps->port, TPS_STATUS_TO_TYPEC_PORTROLE(st.status)); + typec_set_vconn_role(tps->port, TPS_STATUS_TO_TYPEC_VCONN(st.status)); + typec_set_orientation(tps->port, orientation); + typec_set_data_role(tps->port, TPS_STATUS_TO_TYPEC_DATAROLE(st.status)); + power_supply_changed(tps->psy); + + /* If the plug is disconnected, we are done */ + if (!new_connected) + return; + + /* Set up partner if we were previously disconnected (or changed). */ + if (!tps->partner) { + struct typec_partner_desc desc; + desc.usb_pd =3D is_pd; + desc.accessory =3D TYPEC_ACCESSORY_NONE; /* XXX: handle accessories */ + desc.identity =3D NULL; + + if (desc.usb_pd) + desc.identity =3D &st.partner_identity; + + tps->partner =3D typec_register_partner(tps->port, &desc); + if (IS_ERR(tps->partner)) + dev_warn(tps->dev, "%s: failed to register partnet\n", __func__); + + if (desc.identity) { + typec_partner_set_identity(tps->partner); + cd321x->cur_partner_identity =3D st.partner_identity; + } + } + + /* Update the TypeC MUX/PHY state */ + cd321x_typec_update_mode(tps, &st); + + /* Launch the USB role switch */ + usb_role_switch_set_role(tps->role_sw, new_role); + + power_supply_changed(tps->psy); +} + +static void cd321x_queue_status(struct tps6598x *tps) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + cd321x->update_status.status_changed |=3D cd321x->update_status.status ^ = tps->status; + + cd321x->update_status.status =3D tps->status; + cd321x->update_status.pwr_status =3D tps->pwr_status; + cd321x->update_status.data_status =3D tps->data_status; + + cd321x->update_status.partner_identity =3D tps->partner_identity; + cd321x->update_status.dp_sid_status =3D cd321x->dp_sid_status; + cd321x->update_status.intel_vid_status =3D cd321x->intel_vid_status; + cd321x->update_status.usb4_status =3D cd321x->usb4_status; +} + +static int cd321x_connect(struct tps6598x *tps, u32 status) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + /* + * This is only called from _probe such that update_work can be + * initialized and then scheduled for the first time to handle + * plugs already connected at boot time. + */ + INIT_DELAYED_WORK(&cd321x->update_work, cd321x_update_work); + tps->status =3D status; + cd321x_queue_status(tps); + schedule_delayed_work(&cd321x->update_work, msecs_to_jiffies(CD321X_DEBOU= NCE_DELAY_MS)); + + return 0; +} + static irqreturn_t cd321x_interrupt(int irq, void *data) { struct tps6598x *tps =3D data; + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); u64 event =3D 0; u32 status; int ret; @@ -653,9 +906,15 @@ static irqreturn_t cd321x_interrupt(int irq, void *dat= a) if (!tps->data->read_data_status(tps)) goto err_unlock; =20 - /* Handle plug insert or removal */ - if (event & APPLE_CD_REG_INT_PLUG_EVENT) - tps6598x_handle_plug_event(tps, status); + cd321x_queue_status(tps); + tps->status =3D status; + + /* + * Cancel pending work if not already running. + * We will requeue the work after CD321X_DEBOUNCE_DELAY_MS regardless. + */ + cancel_delayed_work(&cd321x->update_work); + schedule_delayed_work(&cd321x->update_work, msecs_to_jiffies(CD321X_DEBOU= NCE_DELAY_MS)); =20 err_unlock: mutex_unlock(&tps->lock); @@ -1023,10 +1282,26 @@ cd321x_register_port(struct tps6598x *tps, struct f= wnode_handle *fwnode) if (ret) goto err_unregister_port; =20 + cd321x->mux =3D fwnode_typec_mux_get(fwnode); + if (IS_ERR(cd321x->mux)) { + ret =3D PTR_ERR(cd321x->mux); + goto err_unregister_altmodes; + } + + cd321x->state.alt =3D NULL; + cd321x->state.mode =3D TYPEC_STATE_SAFE; + cd321x->state.data =3D NULL; typec_set_mode(tps->port, TYPEC_STATE_SAFE); =20 return 0; =20 +err_unregister_altmodes: + if (cd321x->port_altmode_dp) + typec_unregister_altmode(cd321x->port_altmode_dp); + if (cd321x->port_altmode_tbt) + typec_unregister_altmode(cd321x->port_altmode_tbt); + cd321x->port_altmode_dp =3D NULL; + cd321x->port_altmode_tbt =3D NULL; err_unregister_port: typec_unregister_port(tps->port); return ret; @@ -1043,6 +1318,8 @@ cd321x_unregister_port(struct tps6598x *tps) { struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); =20 + if (cd321x->mux) + typec_mux_put(cd321x->mux); if (cd321x->port_altmode_dp) typec_unregister_altmode(cd321x->port_altmode_dp); if (cd321x->port_altmode_tbt) @@ -1457,6 +1734,13 @@ tps25750_register_port(struct tps6598x *tps, struct = fwnode_handle *fwnode) return 0; } =20 +static void cd321x_remove(struct tps6598x *tps) +{ + struct cd321x *cd321x =3D container_of(tps, struct cd321x, tps); + + cancel_delayed_work_sync(&cd321x->update_work); +} + static int tps6598x_probe(struct i2c_client *client) { const struct tipd_data *data; @@ -1558,7 +1842,7 @@ static int tps6598x_probe(struct i2c_client *client) goto err_unregister_port; if (!tps->data->read_data_status(tps)) goto err_unregister_port; - ret =3D tps6598x_connect(tps, status); + ret =3D tps->data->connect(tps, status); if (ret) dev_err(&client->dev, "failed to register partner\n"); } @@ -1615,6 +1899,9 @@ static void tps6598x_remove(struct i2c_client *client) else devm_free_irq(tps->dev, client->irq, tps); =20 + if (tps->data->remove) + tps->data->remove(tps); + tps6598x_disconnect(tps, 0); tps->data->unregister_port(tps); usb_role_switch_put(tps->role_sw); @@ -1685,6 +1972,7 @@ static const struct tipd_data cd321x_data =3D { APPLE_CD_REG_INT_DATA_STATUS_UPDATE | APPLE_CD_REG_INT_PLUG_EVENT, .tps_struct_size =3D sizeof(struct cd321x), + .remove =3D cd321x_remove, .register_port =3D cd321x_register_port, .unregister_port =3D cd321x_unregister_port, .trace_data_status =3D trace_cd321x_data_status, @@ -1694,6 +1982,7 @@ static const struct tipd_data cd321x_data =3D { .read_data_status =3D cd321x_read_data_status, .reset =3D cd321x_reset, .switch_power_state =3D cd321x_switch_power_state, + .connect =3D cd321x_connect, }; =20 static const struct tipd_data tps6598x_data =3D { @@ -1711,6 +2000,7 @@ static const struct tipd_data tps6598x_data =3D { .init =3D tps6598x_init, .read_data_status =3D tps6598x_read_data_status, .reset =3D tps6598x_reset, + .connect =3D tps6598x_connect, }; =20 static const struct tipd_data tps25750_data =3D { @@ -1728,6 +2018,7 @@ static const struct tipd_data tps25750_data =3D { .init =3D tps25750_init, .read_data_status =3D tps6598x_read_data_status, .reset =3D tps25750_reset, + .connect =3D tps6598x_connect, }; =20 static const struct of_device_id tps6598x_of_match[] =3D { --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E22D92FB61B; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-20-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6361; i=sven@kernel.org; h=from:subject:message-id; bh=vklN4/w2hbW7rNLgTYVlAI33wbeeVkY8FZwbhVtsJVg=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy21PV4iZzXpfc0TPWYvT0/nIx9ueWn9s2MSiGzV+wq 3PZic03OkpYGMQ4GGTFFFm277c3ffLwjeDSTZfew8xhZQIZwsDFKQATKb7CyPCkcbqJ7JuLEkmz GQsYm1WZ/gfP4DiiZfVrhvfthdsfbv/J8OP35dRP5QF28fv/v5s9keVIj4O/1YYbfVMs/nf/tnu 9hAcA X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Various hardware, like the Type-C PHY or the Thunderbolt/USB4 NHI, present on Apple SoCs need machine-specific tunables passed from our bootloader m1n1 to the device tree. Add generic helpers so that we don't have to duplicate this across multiple drivers. Signed-off-by: Sven Peter --- drivers/soc/apple/Kconfig | 4 ++ drivers/soc/apple/Makefile | 3 ++ drivers/soc/apple/tunable.c | 77 +++++++++++++++++++++++++++++++++++= ++++ include/linux/soc/apple/tunable.h | 64 ++++++++++++++++++++++++++++++++ 4 files changed, 148 insertions(+) diff --git a/drivers/soc/apple/Kconfig b/drivers/soc/apple/Kconfig index 6388cbe1e56b5a9d90acad3ee2377ed6ac0d207d..f266b70fd9620cc940dc685f7eb= 2972c21a361df 100644 --- a/drivers/soc/apple/Kconfig +++ b/drivers/soc/apple/Kconfig @@ -41,6 +41,10 @@ config APPLE_SART =20 Say 'y' here if you have an Apple SoC. =20 +config APPLE_TUNABLE + tristate + depends on ARCH_APPLE || COMPILE_TEST + endmenu =20 endif diff --git a/drivers/soc/apple/Makefile b/drivers/soc/apple/Makefile index 4d9ab8f3037b7159771d8817fa507ba29f99ae10..0b85ab61aefe131349a67d0aa80= 204edd8e89925 100644 --- a/drivers/soc/apple/Makefile +++ b/drivers/soc/apple/Makefile @@ -8,3 +8,6 @@ apple-rtkit-y =3D rtkit.o rtkit-crashlog.o =20 obj-$(CONFIG_APPLE_SART) +=3D apple-sart.o apple-sart-y =3D sart.o + +obj-$(CONFIG_APPLE_TUNABLE) +=3D apple-tunable.o +apple-tunable-y =3D tunable.o diff --git a/drivers/soc/apple/tunable.c b/drivers/soc/apple/tunable.c new file mode 100644 index 0000000000000000000000000000000000000000..3d9d47b3861f6fea637a3c82f27= 0e5d321b1a48e --- /dev/null +++ b/drivers/soc/apple/tunable.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/* + * Apple Silicon hardware tunable support + * + * Each tunable is a list with each entry containing a offset into the MMIO + * region, a mask of bits to be cleared and a set of bits to be set. These + * tunables are passed along by the previous boot stages and vary from dev= ice + * to device such that they cannot be hardcoded in the individual drivers. + * + * Copyright (C) The Asahi Linux Contributors + */ + +#include +#include +#include +#include + +int devm_apple_parse_tunable(struct device *dev, struct device_node *np, + struct apple_tunable *tunable, const char *name) +{ + struct property *prop; + const __le32 *p =3D NULL; + int i; + + prop =3D of_find_property(np, name, NULL); + if (!prop) { + dev_err(dev, "tunable %s not found\n", name); + return -ENOENT; + } + + if (prop->length % (3 * sizeof(u32))) + return -EINVAL; + + tunable->sz =3D prop->length / (3 * sizeof(u32)); + tunable->values =3D devm_kcalloc(dev, tunable->sz, + sizeof(*tunable->values), GFP_KERNEL); + if (!tunable->values) { + tunable->sz =3D 0; + return -ENOMEM; + } + + for (i =3D 0; i < tunable->sz; ++i) { + p =3D of_prop_next_u32(prop, p, &tunable->values[i].offset); + p =3D of_prop_next_u32(prop, p, &tunable->values[i].mask); + p =3D of_prop_next_u32(prop, p, &tunable->values[i].value); + } + + return 0; +} +EXPORT_SYMBOL(devm_apple_parse_tunable); + +void devm_apple_free_tunable(struct device *dev, struct apple_tunable *tun= able) +{ + devm_kfree(dev, tunable->values); + tunable->sz =3D 0; +} +EXPORT_SYMBOL(devm_apple_free_tunable); + +void apple_apply_tunable(void __iomem *regs, struct apple_tunable *tunable) +{ + size_t i; + + for (i =3D 0; i < tunable->sz; ++i) { + u32 val, old_val; + + val =3D old_val =3D readl_relaxed(regs + tunable->values[i].offset); + val &=3D ~tunable->values[i].mask; + val |=3D tunable->values[i].value; + if (val !=3D old_val) + writel_relaxed(val, regs + tunable->values[i].offset); + } +} +EXPORT_SYMBOL(apple_apply_tunable); + +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_AUTHOR("Sven Peter "); +MODULE_DESCRIPTION("Apple Silicon hardware tunable support"); diff --git a/include/linux/soc/apple/tunable.h b/include/linux/soc/apple/tu= nable.h new file mode 100644 index 0000000000000000000000000000000000000000..4a149f0f210d0b4b9e17c213f04= 82e8fbe02355f --- /dev/null +++ b/include/linux/soc/apple/tunable.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/* + * Apple Silicon hardware tunable support + * + * Each tunable is a list with each entry containing a offset into the MMIO + * region, a mask of bits to be cleared and a set of bits to be set. These + * tunables are passed along by the previous boot stages and vary from dev= ice + * to device such that they cannot be hardcoded in the individual drivers. + * + * Copyright (C) The Asahi Linux Contributors + */ + +#ifndef _LINUX_SOC_APPLE_TUNABLE_H_ +#define _LINUX_SOC_APPLE_TUNABLE_H_ + +#include +#include + +/* + * Struct to store a Apple Silicon hardware tunable. + * + * sz: number of [offset, mask, value] tuples stored in values. + * values: array containing the hardware tunables. + */ +struct apple_tunable { + size_t sz; + struct { + u32 offset; + u32 mask; + u32 value; + } *values; +}; + +/* + * Parse an array of hardware tunables from the device tree. + * + * Return 0 on success, -ENOMEM if the allocation failed and -ENOENT if the + * tunable could not be found or was in an invalid format. + * + * dev: Device node used for devm_kzalloc internally. + * np: Device node which contains the tunable array. + * tunable: Pointer to where the parsed tunables will be stored. + * name: Name of the device tree property which contains the tunables. + */ +int devm_apple_parse_tunable(struct device *dev, struct device_node *np, + struct apple_tunable *tunable, const char *name); + +/* + * Apply a previously loaded hardware tunable. + * + * regs: MMIO to which the tunable will be applied. + * tunable: Pointer to the tunable. + */ +void apple_apply_tunable(void __iomem *regs, struct apple_tunable *tunable= ); + +/* + * Manually frees a previous allocated tunable. + * + * dev: Device node used for devm_apple_parse_tunable + * tunable: Tunable allocaated by devm_apple_parse_tunable + */ +void devm_apple_free_tunable(struct device *dev, struct apple_tunable *tun= able); + +#endif --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E2ABD2FB61C; Thu, 21 Aug 2025 15:40:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-21-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=88292; i=sven@kernel.org; h=from:subject:message-id; bh=CRvRMMsvQMmwr7Q6LcV1f0nv/ORI6UNsyCo1rk+WUY0=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy27Nzjq0L+PXQ/tGP3bwRUtlG4ovWLL7dVnvt3SNP4 Q1Pz8ZYdpSyMIhxMMiKKbJs329v+uThG8Glmy69h5nDygQyhIGLUwAmIruDkWF51JydUb8S3lrP TH3z5/TCKatW/lz7cKXKRZN1UbuEq/8eZWSYf43jXtRmd7uZawvKAs4JTLuR23E+0LgjR4F1v/6 J+w94AQ== X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 The Apple Type-C PHY (ATCPHY) is a PHY for USB 2.0, USB 3.x, USB4/Thunderbolt, and DisplayPort connectivity found in Apple Silicon SoCs. The PHY handles muxing between these different protocols and also provides the reset controller for the attached dwc3 USB controller. There is no documentation available for this PHY and the entire sequence of MMIO pokes has been figured out by tracing all MMIO access of Apple's driver under a thin hypervisor and correlating the register reads/writes to their kernel's debug output to find their names. Deviations from this sequence generally results in the port not working or, especially when the mode is switched to USB4 or Thunderbolt, to some watchdog resetting the entire SoC. This initial commit already introduces support for Display Port and USB4/Thunderbolt but the drivers for these are not ready. We cannot control the alternate mode negotiation and are stuck with whatever Apple's firmware decides such that any DisplayPort or USB4/Thunderbolt device will result in a correctly setup PHY but not be usable until the other drivers are upstreamed as well. Co-developed-by: Janne Grunau Signed-off-by: Janne Grunau Co-developed-by: Hector Martin Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- MAINTAINERS | 1 + drivers/phy/Kconfig | 1 + drivers/phy/Makefile | 1 + drivers/phy/apple/Kconfig | 14 + drivers/phy/apple/Makefile | 4 + drivers/phy/apple/atc.c | 2537 ++++++++++++++++++++++++++++++++++++++++= ++++ 6 files changed, 2558 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 11a9b084a2e51d7b9b2e4c1777a2439df4a6858b..f17dc2140ef3aab88a51b710eaf= 5d8251df972d8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2419,6 +2419,7 @@ F: drivers/mfd/macsmc.c F: drivers/nvme/host/apple.c F: drivers/nvmem/apple-efuses.c F: drivers/nvmem/apple-spmi-nvmem.c +F: drivers/phy/apple/ F: drivers/pinctrl/pinctrl-apple-gpio.c F: drivers/power/reset/macsmc-reboot.c F: drivers/pwm/pwm-apple.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 58c911e1b2d20a0398f02550e938ce62633230d4..602339a1f14e35f1941880c71c4= 442b5fa73c9f9 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -103,6 +103,7 @@ config PHY_NXP_PTN3222 =20 source "drivers/phy/allwinner/Kconfig" source "drivers/phy/amlogic/Kconfig" +source "drivers/phy/apple/Kconfig" source "drivers/phy/broadcom/Kconfig" source "drivers/phy/cadence/Kconfig" source "drivers/phy/freescale/Kconfig" diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c670a8dac46807863c9ef990beb149082238ad16..e5933f7c38337e0745ec0e32bed= 0c544e4af383a 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PHY_AIROHA_PCIE) +=3D phy-airoha-pcie.o obj-$(CONFIG_PHY_NXP_PTN3222) +=3D phy-nxp-ptn3222.o obj-y +=3D allwinner/ \ amlogic/ \ + apple/ \ broadcom/ \ cadence/ \ freescale/ \ diff --git a/drivers/phy/apple/Kconfig b/drivers/phy/apple/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..67f460512592602ae60b2245b15= 62f5f667488c9 --- /dev/null +++ b/drivers/phy/apple/Kconfig @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +config PHY_APPLE_ATC + tristate "Apple Type-C PHY" + depends on (ARM64 && ARCH_APPLE) || (COMPILE_TEST && !GENERIC_ATOMIC64) + depends on TYPEC + select GENERIC_PHY + select APPLE_TUNABLE + help + Enable this to add support for the Apple Type-C PHY found in + Apple Silicon M-series SoCs. This PHY supports USB2, + USB3, USB4, Thunderbolt, and DisplayPort. + + If M is selected the module will be called 'phy-apple-atc'. + diff --git a/drivers/phy/apple/Makefile b/drivers/phy/apple/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e02836a63df3b5324c5ac102b37= 9b12a24494301 --- /dev/null +++ b/drivers/phy/apple/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause + +obj-$(CONFIG_PHY_APPLE_ATC) +=3D phy-apple-atc.o +phy-apple-atc-y :=3D atc.o diff --git a/drivers/phy/apple/atc.c b/drivers/phy/apple/atc.c new file mode 100644 index 0000000000000000000000000000000000000000..51c5d7880d9bb36089e286c159c= cc3505c62ecff --- /dev/null +++ b/drivers/phy/apple/atc.c @@ -0,0 +1,2537 @@ +// SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +/* + * Apple Type-C PHY driver + * + * Copyright (C) The Asahi Linux Contributors + * Author: Sven Peter + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AUSPLL_FSM_CTRL 0x1014 + +#define AUSPLL_APB_CMD_OVERRIDE 0x2000 +#define AUSPLL_APB_CMD_OVERRIDE_REQ BIT(0) +#define AUSPLL_APB_CMD_OVERRIDE_ACK BIT(1) +#define AUSPLL_APB_CMD_OVERRIDE_UNK28 BIT(28) +#define AUSPLL_APB_CMD_OVERRIDE_CMD GENMASK(27, 3) + +#define AUSPLL_FREQ_DESC_A 0x2080 +#define AUSPLL_FD_FREQ_COUNT_TARGET GENMASK(9, 0) +#define AUSPLL_FD_FBDIVN_HALF BIT(10) +#define AUSPLL_FD_REV_DIVN GENMASK(13, 11) +#define AUSPLL_FD_KI_MAN GENMASK(17, 14) +#define AUSPLL_FD_KI_EXP GENMASK(21, 18) +#define AUSPLL_FD_KP_MAN GENMASK(25, 22) +#define AUSPLL_FD_KP_EXP GENMASK(29, 26) +#define AUSPLL_FD_KPKI_SCALE_HBW GENMASK(31, 30) + +#define AUSPLL_FREQ_DESC_B 0x2084 +#define AUSPLL_FD_FBDIVN_FRAC_DEN GENMASK(13, 0) +#define AUSPLL_FD_FBDIVN_FRAC_NUM GENMASK(27, 14) + +#define AUSPLL_FREQ_DESC_C 0x2088 +#define AUSPLL_FD_SDM_SSC_STEP GENMASK(7, 0) +#define AUSPLL_FD_SDM_SSC_EN BIT(8) +#define AUSPLL_FD_PCLK_DIV_SEL GENMASK(13, 9) +#define AUSPLL_FD_LFSDM_DIV GENMASK(15, 14) +#define AUSPLL_FD_LFCLK_CTRL GENMASK(19, 16) +#define AUSPLL_FD_VCLK_OP_DIVN GENMASK(21, 20) +#define AUSPLL_FD_VCLK_PRE_DIVN BIT(22) + +#define AUSPLL_DCO_EFUSE_SPARE 0x222c +#define AUSPLL_RODCO_ENCAP_EFUSE GENMASK(10, 9) +#define AUSPLL_RODCO_BIAS_ADJUST_EFUSE GENMASK(14, 12) + +#define AUSPLL_FRACN_CAN 0x22a4 +#define AUSPLL_DLL_START_CAPCODE GENMASK(18, 17) + +#define AUSPLL_CLKOUT_MASTER 0x2200 +#define AUSPLL_CLKOUT_MASTER_PCLK_DRVR_EN BIT(2) +#define AUSPLL_CLKOUT_MASTER_PCLK2_DRVR_EN BIT(4) +#define AUSPLL_CLKOUT_MASTER_REFBUFCLK_DRVR_EN BIT(6) + +#define AUSPLL_CLKOUT_DIV 0x2208 +#define AUSPLL_CLKOUT_PLLA_REFBUFCLK_DI GENMASK(20, 16) + +#define AUSPLL_BGR 0x2214 +#define AUSPLL_BGR_CTRL_AVAIL BIT(0) + +#define AUSPLL_CLKOUT_DTC_VREG 0x2220 +#define AUSPLL_DTC_VREG_ADJUST GENMASK(16, 14) +#define AUSPLL_DTC_VREG_BYPASS BIT(7) + +#define AUSPLL_FREQ_CFG 0x2224 +#define AUSPLL_FREQ_REFCLK GENMASK(1, 0) + +#define AUS_COMMON_SHIM_BLK_VREG 0x0a04 +#define AUS_VREG_TRIM GENMASK(6, 2) + +#define AUS_UNK_A20 0x0a20 +#define AUS_UNK_A20_TX_CAL_CODE GENMASK(23, 20) + +#define ACIOPHY_CMN_SHM_STS_REG0 0x0a74 +#define ACIOPHY_CMN_SHM_STS_REG0_CMD_READY BIT(0) + +#define CIO3PLL_CLK_CTRL 0x2a00 +#define CIO3PLL_CLK_PCLK_EN BIT(1) +#define CIO3PLL_CLK_REFCLK_EN BIT(5) + +#define CIO3PLL_DCO_NCTRL 0x2a38 +#define CIO3PLL_DCO_COARSEBIN_EFUSE0 GENMASK(6, 0) +#define CIO3PLL_DCO_COARSEBIN_EFUSE1 GENMASK(23, 17) + +#define CIO3PLL_FRACN_CAN 0x2aa4 +#define CIO3PLL_DLL_CAL_START_CAPCODE GENMASK(18, 17) + +#define CIO3PLL_DTC_VREG 0x2a20 +#define CIO3PLL_DTC_VREG_ADJUST GENMASK(16, 14) + +#define ACIOPHY_CFG0 0x08 +#define ACIOPHY_CFG0_COMMON_BIG_OV BIT(1) +#define ACIOPHY_CFG0_COMMON_SMALL_OV BIT(3) +#define ACIOPHY_CFG0_COMMON_CLAMP_OV BIT(5) +#define ACIOPHY_CFG0_RX_SMALL_OV GENMASK(9, 8) +#define ACIOPHY_CFG0_RX_BIG_OV GENMASK(13, 12) +#define ACIOPHY_CFG0_RX_CLAMP_OV GENMASK(17, 16) + +#define ACIOPHY_CROSSBAR 0x4c +#define ACIOPHY_CROSSBAR_PROTOCOL GENMASK(4, 0) +#define ACIOPHY_CROSSBAR_PROTOCOL_USB4 0x0 +#define ACIOPHY_CROSSBAR_PROTOCOL_USB4_SWAPPED 0x1 +#define ACIOPHY_CROSSBAR_PROTOCOL_USB3 0xa +#define ACIOPHY_CROSSBAR_PROTOCOL_USB3_SWAPPED 0xb +#define ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP 0x10 +#define ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP_SWAPPED 0x11 +#define ACIOPHY_CROSSBAR_PROTOCOL_DP 0x14 +#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA GENMASK(16, 5) +#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE 0x0000 +#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK100 0x100 +#define ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008 0x008 +#define ACIOPHY_CROSSBAR_DP_BOTH_PMA BIT(17) + +#define ACIOPHY_LANE_MODE 0x48 +#define ACIOPHY_LANE_MODE_RX0 GENMASK(2, 0) +#define ACIOPHY_LANE_MODE_TX0 GENMASK(5, 3) +#define ACIOPHY_LANE_MODE_RX1 GENMASK(8, 6) +#define ACIOPHY_LANE_MODE_TX1 GENMASK(11, 9) +#define ACIOPHY_LANE_MODE_USB4 0 +#define ACIOPHY_LANE_MODE_USB3 1 +#define ACIOPHY_LANE_MODE_DP 2 +#define ACIOPHY_LANE_MODE_OFF 3 + +#define ACIOPHY_TOP_BIST_CIOPHY_CFG1 0x84 +#define ACIOPHY_TOP_BIST_CIOPHY_CFG1_CLK_EN BIT(27) +#define ACIOPHY_TOP_BIST_CIOPHY_CFG1_BIST_EN BIT(28) + +#define ACIOPHY_TOP_BIST_OV_CFG 0x8c +#define ACIOPHY_TOP_BIST_OV_CFG_LN0_RESET_N_OV BIT(13) +#define ACIOPHY_TOP_BIST_OV_CFG_LN0_PWR_DOWN_OV BIT(25) + +#define ACIOPHY_TOP_BIST_READ_CTRL 0x90 +#define ACIOPHY_TOP_BIST_READ_CTRL_LN0_PHY_STATUS_RE BIT(2) + +#define ACIOPHY_TOP_PHY_STAT 0x9c +#define ACIOPHY_TOP_PHY_STAT_LN0_UNK0 BIT(0) +#define ACIOPHY_TOP_PHY_STAT_LN0_UNK23 BIT(23) + +#define ACIOPHY_TOP_BIST_PHY_CFG0 0xa8 +#define ACIOPHY_TOP_BIST_PHY_CFG0_LN0_RESET_N BIT(0) + +#define ACIOPHY_TOP_BIST_PHY_CFG1 0xac +#define ACIOPHY_TOP_BIST_PHY_CFG1_LN0_PWR_DOWN GENMASK(13, 10) + +#define ACIOPHY_SLEEP_CTRL 0x1b0 +#define ACIOPHY_SLEEP_CTRL_TX_BIG_OV GENMASK(3, 2) +#define ACIOPHY_SLEEP_CTRL_TX_SMALL_OV GENMASK(7, 6) +#define ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV GENMASK(11, 10) + +#define ACIOPHY_PLL_PCTL_FSM_CTRL1 0x1014 +#define ACIOPHY_PLL_APB_REQ_OV_SEL GENMASK(21, 13) +#define ACIOPHY_PLL_COMMON_CTRL 0x1028 +#define ACIOPHY_PLL_WAIT_FOR_CMN_READY_BEFORE_RESET_EXIT BIT(24) + +#define ATCPHY_POWER_CTRL 0x20000 +#define ATCPHY_POWER_STAT 0x20004 +#define ATCPHY_POWER_SLEEP_SMALL BIT(0) +#define ATCPHY_POWER_SLEEP_BIG BIT(1) +#define ATCPHY_POWER_CLAMP_EN BIT(2) +#define ATCPHY_POWER_APB_RESET_N BIT(3) +#define ATCPHY_POWER_PHY_RESET_N BIT(4) + +#define ATCPHY_MISC 0x20008 +#define ATCPHY_MISC_RESET_N BIT(0) +#define ATCPHY_MISC_LANE_SWAP BIT(2) + +#define ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0 0x7000 +#define DP_PMA_BYTECLK_RESET BIT(0) +#define DP_MAC_DIV20_CLK_SEL BIT(1) +#define DPTXPHY_PMA_LANE_RESET_N BIT(2) +#define DPTXPHY_PMA_LANE_RESET_N_OV BIT(3) +#define DPTX_PCLK1_SELECT GENMASK(6, 4) +#define DPTX_PCLK2_SELECT GENMASK(9, 7) +#define DPRX_PCLK_SELECT GENMASK(12, 10) +#define DPTX_PCLK1_ENABLE BIT(13) +#define DPTX_PCLK2_ENABLE BIT(14) +#define DPRX_PCLK_ENABLE BIT(15) + +#define ACIOPHY_DP_PCLK_STAT 0x7044 +#define ACIOPHY_AUSPLL_LOCK BIT(3) + +#define LN0_AUSPMA_RX_TOP 0x9000 +#define LN0_AUSPMA_RX_EQ 0xA000 +#define LN0_AUSPMA_RX_SHM 0xB000 +#define LN0_AUSPMA_TX_TOP 0xC000 +#define LN0_AUSPMA_TX_SHM 0xD000 + +#define LN1_AUSPMA_RX_TOP 0x10000 +#define LN1_AUSPMA_RX_EQ 0x11000 +#define LN1_AUSPMA_RX_SHM 0x12000 +#define LN1_AUSPMA_TX_TOP 0x13000 +#define LN1_AUSPMA_TX_SHM 0x14000 + +#define LN_AUSPMA_RX_TOP_PMAFSM 0x0010 +#define LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV BIT(0) +#define LN_AUSPMA_RX_TOP_PMAFSM_PCS_REQ BIT(9) + +#define LN_AUSPMA_RX_TOP_TJ_CFG_RX_TXMODE 0x00F0 +#define LN_RX_TXMODE BIT(0) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_CTLE_CTRL0 0x00 +#define LN_TX_CLK_EN BIT(20) +#define LN_TX_CLK_EN_OV BIT(21) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_AFE_CTRL1 0x04 +#define LN_RX_DIV20_RESET_N_OV BIT(29) +#define LN_RX_DIV20_RESET_N BIT(30) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL2 0x08 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL3 0x0C +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL4 0x10 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL5 0x14 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL6 0x18 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL7 0x1C +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL8 0x20 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL9 0x24 +#define LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL10 0x28 +#define LN_DTVREG_ADJUST GENMASK(31, 27) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11 0x2C +#define LN_DTVREG_BIG_EN BIT(23) +#define LN_DTVREG_BIG_EN_OV BIT(24) +#define LN_DTVREG_SML_EN BIT(25) +#define LN_DTVREG_SML_EN_OV BIT(26) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12 0x30 +#define LN_TX_BYTECLK_RESET_SYNC_CLR BIT(22) +#define LN_TX_BYTECLK_RESET_SYNC_CLR_OV BIT(23) +#define LN_TX_BYTECLK_RESET_SYNC_EN BIT(24) +#define LN_TX_BYTECLK_RESET_SYNC_EN_OV BIT(25) +#define LN_TX_HRCLK_SEL BIT(28) +#define LN_TX_HRCLK_SEL_OV BIT(29) +#define LN_TX_PBIAS_EN BIT(30) +#define LN_TX_PBIAS_EN_OV BIT(31) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13 0x34 +#define LN_TX_PRE_EN BIT(0) +#define LN_TX_PRE_EN_OV BIT(1) +#define LN_TX_PST1_EN BIT(2) +#define LN_TX_PST1_EN_OV BIT(3) +#define LN_DTVREG_ADJUST_OV BIT(15) + +#define LN_AUSPMA_RX_SHM_TJ_UNK_CTRL14A 0x38 +#define LN_AUSPMA_RX_SHM_TJ_UNK_CTRL14B 0x3C +#define LN_AUSPMA_RX_SHM_TJ_UNK_CTRL15A 0x40 +#define LN_AUSPMA_RX_SHM_TJ_UNK_CTRL15B 0x44 +#define LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16 0x48 +#define LN_RXTERM_EN BIT(21) +#define LN_RXTERM_EN_OV BIT(22) +#define LN_RXTERM_PULLUP_LEAK_EN BIT(23) +#define LN_RXTERM_PULLUP_LEAK_EN_OV BIT(24) +#define LN_TX_CAL_CODE GENMASK(29, 25) +#define LN_TX_CAL_CODE_OV BIT(30) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17 0x4C +#define LN_TX_MARGIN GENMASK(19, 15) +#define LN_TX_MARGIN_OV BIT(20) +#define LN_TX_MARGIN_LSB BIT(21) +#define LN_TX_MARGIN_LSB_OV BIT(22) +#define LN_TX_MARGIN_P1 GENMASK(26, 23) +#define LN_TX_MARGIN_P1_OV BIT(27) +#define LN_TX_MARGIN_P1_LSB GENMASK(29, 28) +#define LN_TX_MARGIN_P1_LSB_OV BIT(30) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18 0x50 +#define LN_TX_P1_CODE GENMASK(3, 0) +#define LN_TX_P1_CODE_OV BIT(4) +#define LN_TX_P1_LSB_CODE GENMASK(6, 5) +#define LN_TX_P1_LSB_CODE_OV BIT(7) +#define LN_TX_MARGIN_PRE GENMASK(10, 8) +#define LN_TX_MARGIN_PRE_OV BIT(11) +#define LN_TX_MARGIN_PRE_LSB GENMASK(13, 12) +#define LN_TX_MARGIN_PRE_LSB_OV BIT(14) +#define LN_TX_PRE_LSB_CODE GENMASK(16, 15) +#define LN_TX_PRE_LSB_CODE_OV BIT(17) +#define LN_TX_PRE_CODE GENMASK(21, 18) +#define LN_TX_PRE_CODE_OV BIT(22) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19 0x54 +#define LN_TX_TEST_EN BIT(21) +#define LN_TX_TEST_EN_OV BIT(22) +#define LN_TX_EN BIT(23) +#define LN_TX_EN_OV BIT(24) +#define LN_TX_CLK_DLY_CTRL_TAPGEN GENMASK(27, 25) +#define LN_TX_CLK_DIV2_EN BIT(28) +#define LN_TX_CLK_DIV2_EN_OV BIT(29) +#define LN_TX_CLK_DIV2_RST BIT(30) +#define LN_TX_CLK_DIV2_RST_OV BIT(31) + +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL20 0x58 +#define LN_AUSPMA_RX_SHM_TJ_RXA_UNK_CTRL21 0x5C +#define LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22 0x60 +#define LN_VREF_ADJUST_GRAY GENMASK(11, 7) +#define LN_VREF_ADJUST_GRAY_OV BIT(12) +#define LN_VREF_BIAS_SEL GENMASK(14, 13) +#define LN_VREF_BIAS_SEL_OV BIT(15) +#define LN_VREF_BOOST_EN BIT(16) +#define LN_VREF_BOOST_EN_OV BIT(17) +#define LN_VREF_EN BIT(18) +#define LN_VREF_EN_OV BIT(19) +#define LN_VREF_LPBKIN_DATA GENMASK(29, 28) +#define LN_VREF_TEST_RXLPBKDT_EN BIT(30) +#define LN_VREF_TEST_RXLPBKDT_EN_OV BIT(31) + +#define LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0 0x00 +#define LN_BYTECLK_RESET_SYNC_EN_OV BIT(2) +#define LN_BYTECLK_RESET_SYNC_EN BIT(3) +#define LN_BYTECLK_RESET_SYNC_CLR_OV BIT(4) +#define LN_BYTECLK_RESET_SYNC_CLR BIT(5) +#define LN_BYTECLK_RESET_SYNC_SEL_OV BIT(6) + +#define LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1 0x04 +#define LN_TXA_DIV2_EN_OV BIT(8) +#define LN_TXA_DIV2_EN BIT(9) +#define LN_TXA_DIV2_RESET_OV BIT(10) +#define LN_TXA_DIV2_RESET BIT(11) +#define LN_TXA_CLK_EN_OV BIT(22) +#define LN_TXA_CLK_EN BIT(23) + +#define LN_AUSPMA_TX_SHM_TXA_IMP_REG0 0x08 +#define LN_TXA_CAL_CTRL_OV BIT(0) +#define LN_TXA_CAL_CTRL GENMASK(18, 1) +#define LN_TXA_CAL_CTRL_BASE_OV BIT(19) +#define LN_TXA_CAL_CTRL_BASE GENMASK(23, 20) +#define LN_TXA_HIZ_OV BIT(29) +#define LN_TXA_HIZ BIT(30) + +#define LN_AUSPMA_TX_SHM_TXA_IMP_REG1 0x0C +#define LN_AUSPMA_TX_SHM_TXA_IMP_REG2 0x10 +#define LN_TXA_MARGIN_OV BIT(0) +#define LN_TXA_MARGIN GENMASK(18, 1) +#define LN_TXA_MARGIN_2R_OV BIT(19) +#define LN_TXA_MARGIN_2R BIT(20) + +#define LN_AUSPMA_TX_SHM_TXA_IMP_REG3 0x14 +#define LN_TXA_MARGIN_POST_OV BIT(0) +#define LN_TXA_MARGIN_POST GENMASK(10, 1) +#define LN_TXA_MARGIN_POST_2R_OV BIT(11) +#define LN_TXA_MARGIN_POST_2R BIT(12) +#define LN_TXA_MARGIN_POST_4R_OV BIT(13) +#define LN_TXA_MARGIN_POST_4R BIT(14) +#define LN_TXA_MARGIN_PRE_OV BIT(15) +#define LN_TXA_MARGIN_PRE GENMASK(21, 16) +#define LN_TXA_MARGIN_PRE_2R_OV BIT(22) +#define LN_TXA_MARGIN_PRE_2R BIT(23) +#define LN_TXA_MARGIN_PRE_4R_OV BIT(24) +#define LN_TXA_MARGIN_PRE_4R BIT(25) + +#define LN_AUSPMA_TX_SHM_TXA_UNK_REG0 0x18 +#define LN_AUSPMA_TX_SHM_TXA_UNK_REG1 0x1C +#define LN_AUSPMA_TX_SHM_TXA_UNK_REG2 0x20 + +#define LN_AUSPMA_TX_SHM_TXA_LDOCLK 0x24 +#define LN_LDOCLK_BYPASS_SML_OV BIT(8) +#define LN_LDOCLK_BYPASS_SML BIT(9) +#define LN_LDOCLK_BYPASS_BIG_OV BIT(10) +#define LN_LDOCLK_BYPASS_BIG BIT(11) +#define LN_LDOCLK_EN_SML_OV BIT(12) +#define LN_LDOCLK_EN_SML BIT(13) +#define LN_LDOCLK_EN_BIG_OV BIT(14) +#define LN_LDOCLK_EN_BIG BIT(15) + +/* LPDPTX registers */ +#define LPDPTX_AUX_CFG_BLK_AUX_CTRL 0x0000 +#define LPDPTX_BLK_AUX_CTRL_PWRDN BIT(4) +#define LPDPTX_BLK_AUX_RXOFFSET GENMASK(25, 22) + +#define LPDPTX_AUX_CFG_BLK_AUX_LDO_CTRL 0x0008 + +#define LPDPTX_AUX_CFG_BLK_AUX_MARGIN 0x000c +#define LPDPTX_MARGIN_RCAL_RXOFFSET_EN BIT(5) +#define LPDPTX_AUX_MARGIN_RCAL_TXSWING GENMASK(10, 6) + +#define LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG0 0x0204 +#define LPDPTX_CFG_PMA_AUX_SEL_LF_DATA BIT(15) + +#define LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG1 0x0208 +#define LPDPTX_CFG_PMA_PHYS_ADJ GENMASK(22, 20) +#define LPDPTX_CFG_PMA_PHYS_ADJ_OV BIT(19) + +#define LPDPTX_AUX_CONTROL 0x4000 +#define LPDPTX_AUX_PWN_DOWN 0x10 +#define LPDPTX_AUX_CLAMP_EN 0x04 +#define LPDPTX_SLEEP_B_BIG_IN 0x02 +#define LPDPTX_SLEEP_B_SML_IN 0x01 +#define LPDPTX_TXTERM_CODEMSB 0x400 +#define LPDPTX_TXTERM_CODE GENMASK(9, 5) + +/* pipehandler registers */ +#define PIPEHANDLER_OVERRIDE 0x00 +#define PIPEHANDLER_OVERRIDE_RXVALID BIT(0) +#define PIPEHANDLER_OVERRIDE_RXDETECT BIT(2) + +#define PIPEHANDLER_OVERRIDE_VALUES 0x04 +#define PIPEHANDLER_OVERRIDE_VAL_RXDETECT0 BIT(1) +#define PIPEHANDLER_OVERRIDE_VAL_RXDETECT1 BIT(2) +#define PIPEHANDLER_OVERRIDE_VAL_PHY_STATUS BIT(4) + +#define PIPEHANDLER_MUX_CTRL 0x0c +#define PIPEHANDLED_MUX_CTRL_CLK GENMASK(5, 3) +#define PIPEHANDLED_MUX_CTRL_DATA GENMASK(2, 0) +#define PIPEHANDLED_MUX_CTRL_CLK_OFF 0 +#define PIPEHANDLED_MUX_CTRL_CLK_USB3 1 +#define PIPEHANDLED_MUX_CTRL_CLK_USB4 2 +#define PIPEHANDLED_MUX_CTRL_CLK_DUMMY 4 + +#define PIPEHANDLED_MUX_CTRL_DATA_USB3 0 +#define PIPEHANDLED_MUX_CTRL_DATA_USB4 1 +#define PIPEHANDLED_MUX_CTRL_DATA_DUMMY 2 + +#define PIPEHANDLER_LOCK_REQ 0x10 +#define PIPEHANDLER_LOCK_ACK 0x14 +#define PIPEHANDLER_LOCK_EN BIT(0) + +#define PIPEHANDLER_AON_GEN 0x1C +#define PIPEHANDLER_AON_GEN_DWC3_FORCE_CLAMP_EN BIT(4) +#define PIPEHANDLER_AON_GEN_DWC3_RESET_N BIT(0) + +#define PIPEHANDLER_NONSELECTED_OVERRIDE 0x20 +#define PIPEHANDLER_NATIVE_RESET BIT(12) +#define PIPEHANDLER_DUMMY_PHY_EN BIT(15) +#define PIPEHANDLER_NATIVE_POWER_DOWN GENMASK(3, 0) + +#define PIPEHANDLER_UNK_2C 0x2c + +/* USB2 PHY regs */ +#define USB2PHY_USBCTL 0x00 +#define USB2PHY_USBCTL_RUN 2 +#define USB2PHY_USBCTL_ISOLATION 4 + +#define USB2PHY_CTL 0x04 +#define USB2PHY_CTL_RESET BIT(0) +#define USB2PHY_CTL_PORT_RESET BIT(1) +#define USB2PHY_CTL_APB_RESET_N BIT(2) +#define USB2PHY_CTL_SIDDQ BIT(3) + +#define USB2PHY_SIG 0x08 +#define USB2PHY_SIG_VBUSDET_FORCE_VAL BIT(0) +#define USB2PHY_SIG_VBUSDET_FORCE_EN BIT(1) +#define USB2PHY_SIG_VBUSVLDEXT_FORCE_VAL BIT(2) +#define USB2PHY_SIG_VBUSVLDEXT_FORCE_EN BIT(3) +#define USB2PHY_SIG_HOST (7 << 12) + +#define USB2PHY_MISCTUNE 0x1c +#define USB2PHY_MISCTUNE_APBCLK_GATE_OFF BIT(29) +#define USB2PHY_MISCTUNE_REFCLK_GATE_OFF BIT(30) + +enum atcphy_dp_link_rate { + ATCPHY_DP_LINK_RATE_RBR, + ATCPHY_DP_LINK_RATE_HBR, + ATCPHY_DP_LINK_RATE_HBR2, + ATCPHY_DP_LINK_RATE_HBR3, +}; + +enum atcphy_pipehandler_state { + ATCPHY_PIPEHANDLER_STATE_INVALID, + ATCPHY_PIPEHANDLER_STATE_DUMMY, + ATCPHY_PIPEHANDLER_STATE_USB3, + ATCPHY_PIPEHANDLER_STATE_USB4, +}; + +enum atcphy_mode { + APPLE_ATCPHY_MODE_OFF, + APPLE_ATCPHY_MODE_USB2, + APPLE_ATCPHY_MODE_USB3, + APPLE_ATCPHY_MODE_USB3_DP, + APPLE_ATCPHY_MODE_TBT, + APPLE_ATCPHY_MODE_USB4, + APPLE_ATCPHY_MODE_DP, +}; + +enum atcphy_lane { + APPLE_ATCPHY_LANE_0, + APPLE_ATCPHY_LANE_1, +}; + +struct atcphy_dp_link_rate_configuration { + u16 freqinit_count_target; + u16 fbdivn_frac_den; + u16 fbdivn_frac_num; + u16 pclk_div_sel; + u8 lfclk_ctrl; + u8 vclk_op_divn; + bool plla_clkout_vreg_bypass; + bool txa_ldoclk_bypass; + bool txa_div2_en; +}; + +struct atcphy_mode_configuration { + u32 crossbar; + u32 crossbar_dp_single_pma; + bool crossbar_dp_both_pma; + u32 lane_mode[2]; + bool dp_lane[2]; + bool set_swap; +}; + +struct apple_atcphy_hw { + unsigned int dp_only : 1; /* hard-wired to internal DP->HDMI converter */ +}; + +struct apple_atcphy { + struct device_node *np; + struct device *dev; + const struct apple_atcphy_hw *hw; + + /* tunables provided by firmware through the device tree */ + struct { + struct apple_tunable fuses; + struct apple_tunable axi2af; + struct apple_tunable common; + struct apple_tunable lane_usb3[2]; + struct apple_tunable lane_displayport[2]; + struct apple_tunable lane_usb4[2]; + } tunables; + + enum atcphy_mode mode; + enum atcphy_mode target_mode; + enum atcphy_pipehandler_state pipehandler_state; + bool swap_lanes; + int dp_link_rate; + bool pipehandler_up; + bool is_host_mode; + bool dwc3_running; + + struct { + void __iomem *core; + void __iomem *axi2af; + void __iomem *usb2phy; + void __iomem *pipehandler; + void __iomem *lpdptx; + } regs; + + struct device **pd_dev; + struct device_link **pd_link; + int pd_count; + + struct phy *phy_usb2; + struct phy *phy_usb3; + struct phy *phy_dp; + struct phy_provider *phy_provider; + struct reset_controller_dev rcdev; + struct typec_switch *sw; + struct typec_mux *mux; + + struct mutex lock; +}; + +static const struct { + const struct atcphy_mode_configuration normal; + const struct atcphy_mode_configuration swapped; + bool enable_dp_aux; + enum atcphy_pipehandler_state pipehandler_state; +} atcphy_modes[] =3D { + [APPLE_ATCPHY_MODE_OFF] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, /* doesn't matter since the SS lanes are off */ + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY, + }, + [APPLE_ATCPHY_MODE_USB2] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, /* doesn't matter since the SS lanes are off */ + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY, + }, + [APPLE_ATCPHY_MODE_USB3] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB3, ACIOPHY_LANE_MODE_OFF}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_OFF, ACIOPHY_LANE_MODE_USB3}, + .dp_lane =3D {false, false}, + .set_swap =3D true, + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_USB3, + }, + [APPLE_ATCPHY_MODE_USB3_DP] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB3, ACIOPHY_LANE_MODE_DP}, + .dp_lane =3D {false, true}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB3_DP_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_DP, ACIOPHY_LANE_MODE_USB3}, + .dp_lane =3D {true, false}, + .set_swap =3D true, + }, + .enable_dp_aux =3D true, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_USB3, + }, + [APPLE_ATCPHY_MODE_TBT] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB4, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB4, ACIOPHY_LANE_MODE_USB4}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB4_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB4, ACIOPHY_LANE_MODE_USB4}, + .dp_lane =3D {false, false}, + .set_swap =3D false, /* intentionally false */ + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY, + }, + [APPLE_ATCPHY_MODE_USB4] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB4, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB4, ACIOPHY_LANE_MODE_USB4}, + .dp_lane =3D {false, false}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_USB4_SWAPPED, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_NONE, + .crossbar_dp_both_pma =3D false, + .lane_mode =3D {ACIOPHY_LANE_MODE_USB4, ACIOPHY_LANE_MODE_USB4}, + .dp_lane =3D {false, false}, + .set_swap =3D false, /* intentionally false */ + }, + .enable_dp_aux =3D false, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_USB4, + }, + [APPLE_ATCPHY_MODE_DP] =3D { + .normal =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_DP, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK100, + .crossbar_dp_both_pma =3D true, + .lane_mode =3D {ACIOPHY_LANE_MODE_DP, ACIOPHY_LANE_MODE_DP}, + .dp_lane =3D {true, true}, + .set_swap =3D false, + }, + .swapped =3D { + .crossbar =3D ACIOPHY_CROSSBAR_PROTOCOL_DP, + .crossbar_dp_single_pma =3D ACIOPHY_CROSSBAR_DP_SINGLE_PMA_UNK008, + .crossbar_dp_both_pma =3D false, /* intentionally false */ + .lane_mode =3D {ACIOPHY_LANE_MODE_DP, ACIOPHY_LANE_MODE_DP}, + .dp_lane =3D {true, true}, + .set_swap =3D false, /* intentionally false */ + }, + .enable_dp_aux =3D true, + .pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY, + }, +}; + +static const struct atcphy_dp_link_rate_configuration dp_lr_config[] =3D { + [ATCPHY_DP_LINK_RATE_RBR] =3D { + .freqinit_count_target =3D 0x21c, + .fbdivn_frac_den =3D 0x0, + .fbdivn_frac_num =3D 0x0, + .pclk_div_sel =3D 0x13, + .lfclk_ctrl =3D 0x5, + .vclk_op_divn =3D 0x2, + .plla_clkout_vreg_bypass =3D true, + .txa_ldoclk_bypass =3D true, + .txa_div2_en =3D true, + }, + [ATCPHY_DP_LINK_RATE_HBR] =3D { + .freqinit_count_target =3D 0x1c2, + .fbdivn_frac_den =3D 0x3ffe, + .fbdivn_frac_num =3D 0x1fff, + .pclk_div_sel =3D 0x9, + .lfclk_ctrl =3D 0x5, + .vclk_op_divn =3D 0x2, + .plla_clkout_vreg_bypass =3D true, + .txa_ldoclk_bypass =3D true, + .txa_div2_en =3D false, + }, + [ATCPHY_DP_LINK_RATE_HBR2] =3D { + .freqinit_count_target =3D 0x1c2, + .fbdivn_frac_den =3D 0x3ffe, + .fbdivn_frac_num =3D 0x1fff, + .pclk_div_sel =3D 0x4, + .lfclk_ctrl =3D 0x5, + .vclk_op_divn =3D 0x0, + .plla_clkout_vreg_bypass =3D true, + .txa_ldoclk_bypass =3D true, + .txa_div2_en =3D false, + }, + [ATCPHY_DP_LINK_RATE_HBR3] =3D { + .freqinit_count_target =3D 0x2a3, + .fbdivn_frac_den =3D 0x3ffc, + .fbdivn_frac_num =3D 0x2ffd, + .pclk_div_sel =3D 0x4, + .lfclk_ctrl =3D 0x6, + .vclk_op_divn =3D 0x0, + .plla_clkout_vreg_bypass =3D false, + .txa_ldoclk_bypass =3D false, + .txa_div2_en =3D false, + }, +}; + +static void atcphy_configure_pipehandler_dummy(struct apple_atcphy *atcphy= ); +static void atcphy_configure_pipehandler(struct apple_atcphy *atcphy); +static void atcphy_usb2_power_on(struct apple_atcphy *atcphy); +static void atcphy_usb2_power_off(struct apple_atcphy *atcphy); + +static inline void mask32(void __iomem *reg, u32 mask, u32 set) +{ + u32 value =3D readl(reg); + + value &=3D ~mask; + value |=3D set; + writel(value, reg); +} + +static inline void core_mask32(struct apple_atcphy *atcphy, u32 reg, u32 m= ask, + u32 set) +{ + mask32(atcphy->regs.core + reg, mask, set); +} + +static inline void set32(void __iomem *reg, u32 set) +{ + mask32(reg, 0, set); +} + +static inline void core_set32(struct apple_atcphy *atcphy, u32 reg, u32 se= t) +{ + core_mask32(atcphy, reg, 0, set); +} + +static inline void clear32(void __iomem *reg, u32 clear) +{ + mask32(reg, clear, 0); +} + +static inline void core_clear32(struct apple_atcphy *atcphy, u32 reg, u32 = clear) +{ + core_mask32(atcphy, reg, clear, 0); +} + +static void atcphy_apply_tunables(struct apple_atcphy *atcphy, + enum atcphy_mode mode) +{ + const int lane0 =3D atcphy->swap_lanes ? 1 : 0; + const int lane1 =3D atcphy->swap_lanes ? 0 : 1; + + apple_apply_tunable(atcphy->regs.core, &atcphy->tunables.fuses); + apple_apply_tunable(atcphy->regs.axi2af, &atcphy->tunables.axi2af); + apple_apply_tunable(atcphy->regs.core, &atcphy->tunables.common); + + switch (mode) { + case APPLE_ATCPHY_MODE_USB3: + apple_apply_tunable(atcphy->regs.core, + &atcphy->tunables.lane_usb3[lane0]); + apple_apply_tunable(atcphy->regs.core, + &atcphy->tunables.lane_usb3[lane1]); + break; + + case APPLE_ATCPHY_MODE_USB3_DP: + apple_apply_tunable(atcphy->regs.core, + &atcphy->tunables.lane_usb3[lane0]); + apple_apply_tunable(atcphy->regs.core, + &atcphy->tunables.lane_displayport[lane1]); + break; + + case APPLE_ATCPHY_MODE_DP: + apple_apply_tunable(atcphy->regs.core, + &atcphy->tunables.lane_displayport[lane0]); + apple_apply_tunable(atcphy->regs.core, + &atcphy->tunables.lane_displayport[lane1]); + break; + + case APPLE_ATCPHY_MODE_TBT: + case APPLE_ATCPHY_MODE_USB4: + apple_apply_tunable(atcphy->regs.core, + &atcphy->tunables.lane_usb4[lane0]); + apple_apply_tunable(atcphy->regs.core, + &atcphy->tunables.lane_usb4[lane1]); + break; + + case APPLE_ATCPHY_MODE_OFF: + break; + case APPLE_ATCPHY_MODE_USB2: + break; + } +} + +static void atcphy_configure_lanes(struct apple_atcphy *atcphy, + enum atcphy_mode mode) +{ + const struct atcphy_mode_configuration *mode_cfg; + + if (atcphy->swap_lanes) + mode_cfg =3D &atcphy_modes[mode].swapped; + else + mode_cfg =3D &atcphy_modes[mode].normal; + + core_mask32(atcphy, ACIOPHY_LANE_MODE, ACIOPHY_LANE_MODE_RX0, + FIELD_PREP(ACIOPHY_LANE_MODE_RX0, mode_cfg->lane_mode[0])); + core_mask32(atcphy, ACIOPHY_LANE_MODE, ACIOPHY_LANE_MODE_TX0, + FIELD_PREP(ACIOPHY_LANE_MODE_TX0, mode_cfg->lane_mode[0])); + core_mask32(atcphy, ACIOPHY_LANE_MODE, ACIOPHY_LANE_MODE_RX1, + FIELD_PREP(ACIOPHY_LANE_MODE_RX1, mode_cfg->lane_mode[1])); + core_mask32(atcphy, ACIOPHY_LANE_MODE, ACIOPHY_LANE_MODE_TX1, + FIELD_PREP(ACIOPHY_LANE_MODE_TX1, mode_cfg->lane_mode[1])); + core_mask32(atcphy, ACIOPHY_CROSSBAR, ACIOPHY_CROSSBAR_PROTOCOL, + FIELD_PREP(ACIOPHY_CROSSBAR_PROTOCOL, mode_cfg->crossbar)); + + if (mode_cfg->set_swap) + core_set32(atcphy, ATCPHY_MISC, ATCPHY_MISC_LANE_SWAP); + else + core_clear32(atcphy, ATCPHY_MISC, ATCPHY_MISC_LANE_SWAP); + + core_mask32(atcphy, ACIOPHY_CROSSBAR, ACIOPHY_CROSSBAR_DP_SINGLE_PMA, + FIELD_PREP(ACIOPHY_CROSSBAR_DP_SINGLE_PMA, + mode_cfg->crossbar_dp_single_pma)); + if (mode_cfg->crossbar_dp_both_pma) + core_set32(atcphy, ACIOPHY_CROSSBAR, + ACIOPHY_CROSSBAR_DP_BOTH_PMA); + else + core_clear32(atcphy, ACIOPHY_CROSSBAR, + ACIOPHY_CROSSBAR_DP_BOTH_PMA); + + if (mode_cfg->dp_lane[0]) { + core_set32(atcphy, LN0_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV); + udelay(10); + core_clear32(atcphy, + LN0_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_REQ); + } else { + core_clear32(atcphy, + LN0_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV); + udelay(10); + } + + if (mode_cfg->dp_lane[1]) { + core_set32(atcphy, LN1_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV); + udelay(10); + core_clear32(atcphy, + LN1_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_REQ); + } else { + core_clear32(atcphy, + LN1_AUSPMA_RX_TOP + LN_AUSPMA_RX_TOP_PMAFSM, + LN_AUSPMA_RX_TOP_PMAFSM_PCS_OV); + udelay(10); + } +} + +static void atcphy_enable_dp_aux(struct apple_atcphy *atcphy) +{ + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTXPHY_PMA_LANE_RESET_N); + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTXPHY_PMA_LANE_RESET_N_OV); + + core_mask32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPRX_PCLK_SELECT, FIELD_PREP(DPRX_PCLK_SELECT, 1)); + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPRX_PCLK_ENABLE); + + core_mask32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTX_PCLK1_SELECT, FIELD_PREP(DPTX_PCLK1_SELECT, 1)); + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTX_PCLK1_ENABLE); + + core_mask32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTX_PCLK2_SELECT, FIELD_PREP(DPTX_PCLK2_SELECT, 1)); + core_set32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTX_PCLK2_ENABLE); + + core_set32(atcphy, ACIOPHY_PLL_COMMON_CTRL, + ACIOPHY_PLL_WAIT_FOR_CMN_READY_BEFORE_RESET_EXIT); + + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_CLAMP_EN); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_SLEEP_B_SML_IN); + udelay(10); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_SLEEP_B_BIG_IN); + udelay(10); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_CLAMP_EN); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_PWN_DOWN); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, + LPDPTX_TXTERM_CODEMSB); + mask32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_TXTERM_CODE, + FIELD_PREP(LPDPTX_TXTERM_CODE, 0x16)); + + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_LDO_CTRL, 0x1c00); + mask32(atcphy->regs.lpdptx + LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG1, + LPDPTX_CFG_PMA_PHYS_ADJ, FIELD_PREP(LPDPTX_CFG_PMA_PHYS_ADJ, 5)); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG1, + LPDPTX_CFG_PMA_PHYS_ADJ_OV); + + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_MARGIN, + LPDPTX_MARGIN_RCAL_RXOFFSET_EN); + + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_CTRL, + LPDPTX_BLK_AUX_CTRL_PWRDN); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_SHM_CFG_BLK_AUX_CTRL_REG0, + LPDPTX_CFG_PMA_AUX_SEL_LF_DATA); + mask32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_CTRL, + LPDPTX_BLK_AUX_RXOFFSET, FIELD_PREP(LPDPTX_BLK_AUX_RXOFFSET, 3)); + + mask32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_MARGIN, + LPDPTX_AUX_MARGIN_RCAL_TXSWING, + FIELD_PREP(LPDPTX_AUX_MARGIN_RCAL_TXSWING, 12)); + + atcphy->dp_link_rate =3D -1; +} + +static void atcphy_disable_dp_aux(struct apple_atcphy *atcphy) +{ + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_PWN_DOWN); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CFG_BLK_AUX_CTRL, + LPDPTX_BLK_AUX_CTRL_PWRDN); + set32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, LPDPTX_AUX_CLAMP_EN); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, + LPDPTX_SLEEP_B_SML_IN); + udelay(10); + clear32(atcphy->regs.lpdptx + LPDPTX_AUX_CONTROL, + LPDPTX_SLEEP_B_BIG_IN); + udelay(10); + + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTXPHY_PMA_LANE_RESET_N); + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPRX_PCLK_ENABLE); + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTX_PCLK1_ENABLE); + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DPTX_PCLK2_ENABLE); +} + +static int +atcphy_dp_configure_lane(struct apple_atcphy *atcphy, enum atcphy_lane lan= e, + const struct atcphy_dp_link_rate_configuration *cfg) +{ + void __iomem *tx_shm, *rx_shm, *rx_top; + unsigned int tx_cal_code; + + lockdep_assert_held(&atcphy->lock); + + switch (lane) { + case APPLE_ATCPHY_LANE_0: + tx_shm =3D atcphy->regs.core + LN0_AUSPMA_TX_SHM; + rx_shm =3D atcphy->regs.core + LN0_AUSPMA_RX_SHM; + rx_top =3D atcphy->regs.core + LN0_AUSPMA_RX_TOP; + break; + case APPLE_ATCPHY_LANE_1: + tx_shm =3D atcphy->regs.core + LN1_AUSPMA_TX_SHM; + rx_shm =3D atcphy->regs.core + LN1_AUSPMA_RX_SHM; + rx_top =3D atcphy->regs.core + LN1_AUSPMA_RX_TOP; + break; + default: + return -EINVAL; + } + + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_EN_SML); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_EN_SML_OV); + udelay(10); + + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_EN_BIG); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, LN_LDOCLK_EN_BIG_OV); + udelay(10); + + if (cfg->txa_ldoclk_bypass) { + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, + LN_LDOCLK_BYPASS_SML); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, + LN_LDOCLK_BYPASS_SML_OV); + udelay(10); + + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, + LN_LDOCLK_BYPASS_BIG); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, + LN_LDOCLK_BYPASS_BIG_OV); + udelay(10); + } else { + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, + LN_LDOCLK_BYPASS_SML); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, + LN_LDOCLK_BYPASS_SML_OV); + udelay(10); + + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, + LN_LDOCLK_BYPASS_BIG); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_LDOCLK, + LN_LDOCLK_BYPASS_BIG_OV); + udelay(10); + } + + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, + LN_BYTECLK_RESET_SYNC_SEL_OV); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, + LN_BYTECLK_RESET_SYNC_EN); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, + LN_BYTECLK_RESET_SYNC_EN_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, + LN_BYTECLK_RESET_SYNC_CLR); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG0, + LN_BYTECLK_RESET_SYNC_CLR_OV); + + if (cfg->txa_div2_en) + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, + LN_TXA_DIV2_EN); + else + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, + LN_TXA_DIV2_EN); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_DIV2_EN_OV); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_CLK_EN); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_CLK_EN_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, LN_TXA_DIV2_RESET); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_CFG_MAIN_REG1, + LN_TXA_DIV2_RESET_OV); + + mask32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_CAL_CTRL_BASE, + FIELD_PREP(LN_TXA_CAL_CTRL_BASE, 0xf)); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_CAL_CTRL_BASE_OV); + + tx_cal_code =3D FIELD_GET(AUS_UNK_A20_TX_CAL_CODE, + readl(atcphy->regs.core + AUS_UNK_A20)); + mask32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_CAL_CTRL, + FIELD_PREP(LN_TXA_CAL_CTRL, (1 << tx_cal_code) - 1)); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_CAL_CTRL_OV); + + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG2, LN_TXA_MARGIN); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG2, LN_TXA_MARGIN_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG2, LN_TXA_MARGIN_2R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG2, LN_TXA_MARGIN_2R_OV); + + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_2R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_2R_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_4R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_POST_4R_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_2R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_2R_OV); + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_4R); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG3, LN_TXA_MARGIN_PRE_4R_OV); + + clear32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_HIZ); + set32(tx_shm + LN_AUSPMA_TX_SHM_TXA_IMP_REG0, LN_TXA_HIZ_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_AFE_CTRL1, + LN_RX_DIV20_RESET_N); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_AFE_CTRL1, + LN_RX_DIV20_RESET_N_OV); + udelay(10); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_AFE_CTRL1, LN_RX_DIV20_RESET_N); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, + LN_TX_BYTECLK_RESET_SYNC_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, + LN_TX_BYTECLK_RESET_SYNC_EN_OV); + + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_TX_CAL_CODE, + FIELD_PREP(LN_TX_CAL_CODE, tx_cal_code)); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_TX_CAL_CODE_OV); + + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, + LN_TX_CLK_DLY_CTRL_TAPGEN, + FIELD_PREP(LN_TX_CLK_DLY_CTRL_TAPGEN, 3)); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL10, LN_DTVREG_ADJUST); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_DTVREG_ADJUST_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_RXTERM_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, LN_RXTERM_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_TEST_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_TEST_EN_OV); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, + LN_VREF_TEST_RXLPBKDT_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, + LN_VREF_TEST_RXLPBKDT_EN_OV); + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, + LN_VREF_LPBKIN_DATA, FIELD_PREP(LN_VREF_LPBKIN_DATA, 3)); + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BIAS_SEL, + FIELD_PREP(LN_VREF_BIAS_SEL, 2)); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, + LN_VREF_BIAS_SEL_OV); + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, + LN_VREF_ADJUST_GRAY, FIELD_PREP(LN_VREF_ADJUST_GRAY, 0x18)); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, + LN_VREF_ADJUST_GRAY_OV); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_EN_OV); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BOOST_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, + LN_VREF_BOOST_EN_OV); + udelay(10); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, LN_VREF_BOOST_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_VREF_CTRL22, + LN_VREF_BOOST_EN_OV); + udelay(10); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_TX_PRE_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_TX_PRE_EN_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_TX_PST1_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_TX_PST1_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_PBIAS_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_PBIAS_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, + LN_RXTERM_PULLUP_LEAK_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_SAVOS_CTRL16, + LN_RXTERM_PULLUP_LEAK_EN_OV); + + set32(rx_top + LN_AUSPMA_RX_TOP_TJ_CFG_RX_TXMODE, LN_RX_TXMODE); + + if (cfg->txa_div2_en) + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, + LN_TX_CLK_DIV2_EN); + else + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, + LN_TX_CLK_DIV2_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, + LN_TX_CLK_DIV2_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, + LN_TX_CLK_DIV2_RST); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, + LN_TX_CLK_DIV2_RST_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_HRCLK_SEL); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, LN_TX_HRCLK_SEL_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_LSB); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_LSB_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_P1); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, LN_TX_MARGIN_P1_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, + LN_TX_MARGIN_P1_LSB); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL17, + LN_TX_MARGIN_P1_LSB_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_P1_CODE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_P1_CODE_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_P1_LSB_CODE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_P1_LSB_CODE_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_MARGIN_PRE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_MARGIN_PRE_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, + LN_TX_MARGIN_PRE_LSB); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, + LN_TX_MARGIN_PRE_LSB_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_PRE_LSB_CODE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, + LN_TX_PRE_LSB_CODE_OV); + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_PRE_CODE); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TX_CTRL18, LN_TX_PRE_CODE_OV); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11, LN_DTVREG_SML_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11, LN_DTVREG_SML_EN_OV); + udelay(10); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11, LN_DTVREG_BIG_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL11, LN_DTVREG_BIG_EN_OV); + udelay(10); + + mask32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL10, LN_DTVREG_ADJUST, + FIELD_PREP(LN_DTVREG_ADJUST, 0xa)); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL13, LN_DTVREG_ADJUST_OV); + udelay(10); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_TERM_CTRL19, LN_TX_EN_OV); + udelay(10); + + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_CTLE_CTRL0, LN_TX_CLK_EN); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_CTLE_CTRL0, LN_TX_CLK_EN_OV); + + clear32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, + LN_TX_BYTECLK_RESET_SYNC_CLR); + set32(rx_shm + LN_AUSPMA_RX_SHM_TJ_RXA_DFE_CTRL12, + LN_TX_BYTECLK_RESET_SYNC_CLR_OV); + + return 0; +} + +static int atcphy_auspll_apb_command(struct apple_atcphy *atcphy, u32 comm= and) +{ + int ret; + u32 reg; + + reg =3D readl(atcphy->regs.core + AUSPLL_APB_CMD_OVERRIDE); + reg &=3D ~AUSPLL_APB_CMD_OVERRIDE_CMD; + reg |=3D FIELD_PREP(AUSPLL_APB_CMD_OVERRIDE_CMD, command); + reg |=3D AUSPLL_APB_CMD_OVERRIDE_REQ; + reg |=3D AUSPLL_APB_CMD_OVERRIDE_UNK28; + writel(reg, atcphy->regs.core + AUSPLL_APB_CMD_OVERRIDE); + + ret =3D readl_poll_timeout(atcphy->regs.core + AUSPLL_APB_CMD_OVERRIDE, + reg, (reg & AUSPLL_APB_CMD_OVERRIDE_ACK), 100, + 100000); + if (ret) + dev_warn( + atcphy->dev, + "AUSPLL APB command was not acked, continuing and hoping for the best a= nyway but this Type-C port will probably not work\n"); + + core_clear32(atcphy, AUSPLL_APB_CMD_OVERRIDE, + AUSPLL_APB_CMD_OVERRIDE_REQ); + + return 0; +} + +static int atcphy_dp_configure(struct apple_atcphy *atcphy, + enum atcphy_dp_link_rate lr) +{ + const struct atcphy_dp_link_rate_configuration *cfg =3D &dp_lr_config[lr]; + const struct atcphy_mode_configuration *mode_cfg; + int ret; + u32 reg; + + if (atcphy->dp_link_rate =3D=3D lr) + return 0; + + if (atcphy->swap_lanes) + mode_cfg =3D &atcphy_modes[atcphy->mode].swapped; + else + mode_cfg =3D &atcphy_modes[atcphy->mode].normal; + + ret =3D readl_poll_timeout(atcphy->regs.core + ACIOPHY_CMN_SHM_STS_REG0, + reg, + (reg & ACIOPHY_CMN_SHM_STS_REG0_CMD_READY), + 100, 100000); + if (ret) { + dev_err(atcphy->dev, + "ACIOPHY_CMN_SHM_STS_REG0_CMD_READY not set.\n"); + return ret; + } + + core_clear32(atcphy, AUSPLL_FREQ_CFG, AUSPLL_FREQ_REFCLK); + + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_FREQ_COUNT_TARGET, + FIELD_PREP(AUSPLL_FD_FREQ_COUNT_TARGET, + cfg->freqinit_count_target)); + core_clear32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_FBDIVN_HALF); + core_clear32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_REV_DIVN); + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KI_MAN, + FIELD_PREP(AUSPLL_FD_KI_MAN, 8)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KI_EXP, + FIELD_PREP(AUSPLL_FD_KI_EXP, 3)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KP_MAN, + FIELD_PREP(AUSPLL_FD_KP_MAN, 8)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KP_EXP, + FIELD_PREP(AUSPLL_FD_KP_EXP, 7)); + core_clear32(atcphy, AUSPLL_FREQ_DESC_A, AUSPLL_FD_KPKI_SCALE_HBW); + + core_mask32(atcphy, AUSPLL_FREQ_DESC_B, AUSPLL_FD_FBDIVN_FRAC_DEN, + FIELD_PREP(AUSPLL_FD_FBDIVN_FRAC_DEN, + cfg->fbdivn_frac_den)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_B, AUSPLL_FD_FBDIVN_FRAC_NUM, + FIELD_PREP(AUSPLL_FD_FBDIVN_FRAC_NUM, + cfg->fbdivn_frac_num)); + + core_clear32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_SDM_SSC_STEP); + core_clear32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_SDM_SSC_EN); + core_mask32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_PCLK_DIV_SEL, + FIELD_PREP(AUSPLL_FD_PCLK_DIV_SEL, cfg->pclk_div_sel)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_LFSDM_DIV, + FIELD_PREP(AUSPLL_FD_LFSDM_DIV, 1)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_LFCLK_CTRL, + FIELD_PREP(AUSPLL_FD_LFCLK_CTRL, cfg->lfclk_ctrl)); + core_mask32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_VCLK_OP_DIVN, + FIELD_PREP(AUSPLL_FD_VCLK_OP_DIVN, cfg->vclk_op_divn)); + core_set32(atcphy, AUSPLL_FREQ_DESC_C, AUSPLL_FD_VCLK_PRE_DIVN); + + core_mask32(atcphy, AUSPLL_CLKOUT_DIV, AUSPLL_CLKOUT_PLLA_REFBUFCLK_DI, + FIELD_PREP(AUSPLL_CLKOUT_PLLA_REFBUFCLK_DI, 7)); + + if (cfg->plla_clkout_vreg_bypass) + core_set32(atcphy, AUSPLL_CLKOUT_DTC_VREG, + AUSPLL_DTC_VREG_BYPASS); + else + core_clear32(atcphy, AUSPLL_CLKOUT_DTC_VREG, + AUSPLL_DTC_VREG_BYPASS); + + core_set32(atcphy, AUSPLL_BGR, AUSPLL_BGR_CTRL_AVAIL); + + core_set32(atcphy, AUSPLL_CLKOUT_MASTER, + AUSPLL_CLKOUT_MASTER_PCLK_DRVR_EN); + core_set32(atcphy, AUSPLL_CLKOUT_MASTER, + AUSPLL_CLKOUT_MASTER_PCLK2_DRVR_EN); + core_set32(atcphy, AUSPLL_CLKOUT_MASTER, + AUSPLL_CLKOUT_MASTER_REFBUFCLK_DRVR_EN); + + ret =3D atcphy_auspll_apb_command(atcphy, 0); + if (ret) + return ret; + + ret =3D readl_poll_timeout(atcphy->regs.core + ACIOPHY_DP_PCLK_STAT, reg, + (reg & ACIOPHY_AUSPLL_LOCK), 100, 100000); + if (ret) { + dev_err(atcphy->dev, "ACIOPHY_DP_PCLK did not lock.\n"); + return ret; + } + + ret =3D atcphy_auspll_apb_command(atcphy, 0x2800); + if (ret) + return ret; + + if (mode_cfg->dp_lane[0]) { + ret =3D atcphy_dp_configure_lane(atcphy, APPLE_ATCPHY_LANE_0, + cfg); + if (ret) + return ret; + } + + if (mode_cfg->dp_lane[1]) { + ret =3D atcphy_dp_configure_lane(atcphy, APPLE_ATCPHY_LANE_1, + cfg); + if (ret) + return ret; + } + + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DP_PMA_BYTECLK_RESET); + core_clear32(atcphy, ACIOPHY_LANE_DP_CFG_BLK_TX_DP_CTRL0, + DP_MAC_DIV20_CLK_SEL); + + atcphy->dp_link_rate =3D lr; + return 0; +} + +static int atcphy_power_off(struct apple_atcphy *atcphy) +{ + u32 reg; + int ret; + + atcphy_disable_dp_aux(atcphy); + + /* enable all reset lines */ + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_PHY_RESET_N); + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_CLAMP_EN); + core_clear32(atcphy, ATCPHY_MISC, + ATCPHY_MISC_RESET_N | ATCPHY_MISC_LANE_SWAP); + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_APB_RESET_N); + + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_SLEEP_BIG); + ret =3D readl_poll_timeout(atcphy->regs.core + ATCPHY_POWER_STAT, reg, + !(reg & ATCPHY_POWER_SLEEP_BIG), 100, 100000); + if (ret) { + dev_err(atcphy->dev, "failed to sleep atcphy \"big\"\n"); + return ret; + } + + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_SLEEP_SMALL); + ret =3D readl_poll_timeout(atcphy->regs.core + ATCPHY_POWER_STAT, reg, + !(reg & ATCPHY_POWER_SLEEP_SMALL), 100, + 100000); + if (ret) { + dev_err(atcphy->dev, "failed to sleep atcphy \"small\"\n"); + return ret; + } + + return 0; +} + +static int atcphy_power_on(struct apple_atcphy *atcphy) +{ + u32 reg; + int ret; + + core_set32(atcphy, ATCPHY_MISC, ATCPHY_MISC_RESET_N); + + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_SLEEP_SMALL); + ret =3D readl_poll_timeout(atcphy->regs.core + ATCPHY_POWER_STAT, reg, + reg & ATCPHY_POWER_SLEEP_SMALL, 100, 100000); + if (ret) { + dev_err(atcphy->dev, "failed to wakeup atcphy \"small\"\n"); + return ret; + } + + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_SLEEP_BIG); + ret =3D readl_poll_timeout(atcphy->regs.core + ATCPHY_POWER_STAT, reg, + reg & ATCPHY_POWER_SLEEP_BIG, 100, 100000); + if (ret) { + dev_err(atcphy->dev, "failed to wakeup atcphy \"big\"\n"); + return ret; + } + + core_clear32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_CLAMP_EN); + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_APB_RESET_N); + + return 0; +} + +static int atcphy_configure(struct apple_atcphy *atcphy, enum atcphy_mode = mode) +{ + int ret =3D 0; + + lockdep_assert_held(&atcphy->lock); + + if (mode =3D=3D APPLE_ATCPHY_MODE_OFF) { + ret =3D atcphy_power_off(atcphy); + atcphy->mode =3D mode; + return ret; + } + + ret =3D atcphy_power_on(atcphy); + if (ret) + return ret; + + atcphy_apply_tunables(atcphy, mode); + + core_set32(atcphy, AUSPLL_FSM_CTRL, 0x1fe000); + core_set32(atcphy, AUSPLL_APB_CMD_OVERRIDE, + AUSPLL_APB_CMD_OVERRIDE_UNK28); + + set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_SMALL_OV); + udelay(10); + set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_BIG_OV); + udelay(10); + set32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_COMMON_CLAMP_OV); + udelay(10); + + mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, + ACIOPHY_SLEEP_CTRL_TX_SMALL_OV, + FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_SMALL_OV, 3)); + udelay(10); + mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, + ACIOPHY_SLEEP_CTRL_TX_BIG_OV, + FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_BIG_OV, 3)); + udelay(10); + mask32(atcphy->regs.core + ACIOPHY_SLEEP_CTRL, + ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV, + FIELD_PREP(ACIOPHY_SLEEP_CTRL_TX_CLAMP_OV, 3)); + udelay(10); + + mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_BIG_OV, + FIELD_PREP(ACIOPHY_CFG0_RX_BIG_OV, 3)); + udelay(10); + mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_SMALL_OV, + FIELD_PREP(ACIOPHY_CFG0_RX_SMALL_OV, 3)); + udelay(10); + mask32(atcphy->regs.core + ACIOPHY_CFG0, ACIOPHY_CFG0_RX_CLAMP_OV, + FIELD_PREP(ACIOPHY_CFG0_RX_CLAMP_OV, 3)); + udelay(10); + + /* setup AUX channel if DP altmode is requested */ + if (atcphy_modes[mode].enable_dp_aux) + atcphy_enable_dp_aux(atcphy); + + /* enable clocks and configure lanes */ + core_set32(atcphy, CIO3PLL_CLK_CTRL, CIO3PLL_CLK_PCLK_EN); + core_set32(atcphy, CIO3PLL_CLK_CTRL, CIO3PLL_CLK_REFCLK_EN); + atcphy_configure_lanes(atcphy, mode); + + /* take the USB3 PHY out of reset */ + core_set32(atcphy, ATCPHY_POWER_CTRL, ATCPHY_POWER_PHY_RESET_N); + + atcphy->mode =3D mode; + + return 0; +} + +static int atcphy_pipehandler_lock(struct apple_atcphy *atcphy) +{ + int ret; + u32 reg; + + if (readl(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_REQ) & + PIPEHANDLER_LOCK_EN) { + dev_warn(atcphy->dev, "pipehandler already locked\n"); + return 0; + } + + set32(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_REQ, + PIPEHANDLER_LOCK_EN); + + ret =3D readl_poll_timeout(atcphy->regs.pipehandler + + PIPEHANDLER_LOCK_ACK, + reg, reg & PIPEHANDLER_LOCK_EN, 1000, 1000000); + if (ret) { + clear32(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_REQ, 1); + dev_warn( + atcphy->dev, + "pipehandler lock not acked and we can't do much about it. this type-c = port is probably dead until at least the next plug/unplug or possibly even = until the next reboot.\n"); + } + + return ret; +} + +static int atcphy_pipehandler_unlock(struct apple_atcphy *atcphy) +{ + int ret; + u32 reg; + + clear32(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_REQ, + PIPEHANDLER_LOCK_EN); + ret =3D readl_poll_timeout( + atcphy->regs.pipehandler + PIPEHANDLER_LOCK_ACK, reg, + !(reg & PIPEHANDLER_LOCK_EN), 1000, 1000000); + if (ret) { + dev_warn( + atcphy->dev, + "pipehandler lock release not acked and we can't do much about it. this= type-c port is probably dead until at least the next plug/unplug or possib= ly even until the next reboot.\n"); + } + + return ret; +} + +static void atcphy_usb2_power_on(struct apple_atcphy *atcphy) +{ + if (atcphy->is_host_mode) + set32(atcphy->regs.usb2phy + USB2PHY_SIG, USB2PHY_SIG_HOST); + else + clear32(atcphy->regs.usb2phy + USB2PHY_SIG, USB2PHY_SIG_HOST); + + set32(atcphy->regs.usb2phy + USB2PHY_SIG, + USB2PHY_SIG_VBUSDET_FORCE_VAL | USB2PHY_SIG_VBUSDET_FORCE_EN | + USB2PHY_SIG_VBUSVLDEXT_FORCE_VAL | + USB2PHY_SIG_VBUSVLDEXT_FORCE_EN); + + udelay(10); + + /* take the PHY out of its low power state */ + clear32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_SIDDQ); + udelay(10); + + /* release reset */ + clear32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_RESET); + udelay(10); + clear32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_PORT_RESET); + udelay(10); + set32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_APB_RESET_N); + udelay(10); + clear32(atcphy->regs.usb2phy + USB2PHY_MISCTUNE, + USB2PHY_MISCTUNE_APBCLK_GATE_OFF); + clear32(atcphy->regs.usb2phy + USB2PHY_MISCTUNE, + USB2PHY_MISCTUNE_REFCLK_GATE_OFF); + + writel(USB2PHY_USBCTL_RUN, atcphy->regs.usb2phy + USB2PHY_USBCTL); +} + +static void atcphy_usb2_power_off(struct apple_atcphy *atcphy) +{ + writel(USB2PHY_USBCTL_ISOLATION, atcphy->regs.usb2phy + USB2PHY_USBCTL); + + udelay(10); + /* switch the PHY to low power mode */ + set32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_SIDDQ); + udelay(10); + set32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_PORT_RESET); + udelay(10); + set32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_RESET); + udelay(10); + clear32(atcphy->regs.usb2phy + USB2PHY_CTL, USB2PHY_CTL_APB_RESET_N); + udelay(10); + + set32(atcphy->regs.usb2phy + USB2PHY_MISCTUNE, + USB2PHY_MISCTUNE_APBCLK_GATE_OFF); + set32(atcphy->regs.usb2phy + USB2PHY_MISCTUNE, + USB2PHY_MISCTUNE_REFCLK_GATE_OFF); +} + +static int atcphy_usb3_power_off(struct phy *phy) +{ + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + guard(mutex)(&atcphy->lock); + + atcphy_configure_pipehandler_dummy(atcphy); + atcphy->pipehandler_up =3D false; + + if (atcphy->target_mode !=3D atcphy->mode) + atcphy_configure(atcphy, atcphy->target_mode); + + return 0; +} + +static int atcphy_usb3_power_on(struct phy *phy) +{ + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + guard(mutex)(&atcphy->lock); + + return 0; +} + +static int atcphy_usb3_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + guard(mutex)(&atcphy->lock); + + if (!atcphy->pipehandler_up) + atcphy_configure_pipehandler(atcphy); + + return 0; +} + +static const struct phy_ops apple_atc_usb2_phy_ops =3D { + .owner =3D THIS_MODULE, + /* Nothing to do for now, USB2 config handled around DWC3 reset */ +}; + +static const struct phy_ops apple_atc_usb3_phy_ops =3D { + .owner =3D THIS_MODULE, + .power_on =3D atcphy_usb3_power_on, + .power_off =3D atcphy_usb3_power_off, + .set_mode =3D atcphy_usb3_set_mode, +}; + +static int atcphy_dpphy_set_mode(struct phy *phy, enum phy_mode mode, + int submode) +{ + /* nothing to do here since the setup already happened in mux_set */ + if (mode =3D=3D PHY_MODE_DP && submode =3D=3D 0) + return 0; + return -EINVAL; +} + +static int atcphy_dpphy_set_mode_dp_only(struct phy *phy, enum phy_mode mo= de, + int submode) +{ + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + guard(mutex)(&atcphy->lock); + + switch (mode) { + case PHY_MODE_DP: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_DP; + return atcphy_configure(atcphy, APPLE_ATCPHY_MODE_DP); + default: + if (atcphy->mode =3D=3D APPLE_ATCPHY_MODE_OFF) + return 0; + else + return atcphy_power_off(atcphy); + } +} + +static int atcphy_dpphy_validate(struct phy *phy, enum phy_mode mode, + int submode, union phy_configure_opts *opts_) +{ + struct phy_configure_opts_dp *opts =3D &opts_->dp; + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + + if (mode !=3D PHY_MODE_DP) + return -EINVAL; + if (submode !=3D 0) + return -EINVAL; + + switch (atcphy->mode) { + case APPLE_ATCPHY_MODE_USB3_DP: + opts->lanes =3D 2; + break; + case APPLE_ATCPHY_MODE_DP: + opts->lanes =3D 4; + break; + default: + opts->lanes =3D 0; + } + + return 0; +} + +static int atcphy_dpphy_configure(struct phy *phy, + union phy_configure_opts *opts_) +{ + struct phy_configure_opts_dp *opts =3D &opts_->dp; + struct apple_atcphy *atcphy =3D phy_get_drvdata(phy); + enum atcphy_dp_link_rate link_rate; + + if (opts->set_voltages) + return -EINVAL; + if (opts->set_lanes) + return -EINVAL; + + if (opts->set_rate) { + guard(mutex)(&atcphy->lock); + + switch (opts->link_rate) { + case 1620: + link_rate =3D ATCPHY_DP_LINK_RATE_RBR; + break; + case 2700: + link_rate =3D ATCPHY_DP_LINK_RATE_HBR; + break; + case 5400: + link_rate =3D ATCPHY_DP_LINK_RATE_HBR2; + break; + case 8100: + link_rate =3D ATCPHY_DP_LINK_RATE_HBR3; + break; + case 0: + return 0; + default: + dev_err(atcphy->dev, "Unsupported link rate: %d\n", + opts->link_rate); + return -EINVAL; + } + + return atcphy_dp_configure(atcphy, link_rate); + } + + return 0; +} + +static const struct phy_ops apple_atc_dp_phy_ops =3D { + .owner =3D THIS_MODULE, + .configure =3D atcphy_dpphy_configure, + .validate =3D atcphy_dpphy_validate, + .set_mode =3D atcphy_dpphy_set_mode, +}; + +static const struct phy_ops apple_atc_dp_only_phy_ops =3D { + .owner =3D THIS_MODULE, + .configure =3D atcphy_dpphy_configure, + .validate =3D atcphy_dpphy_validate, + .set_mode =3D atcphy_dpphy_set_mode_dp_only, +}; + +static struct phy *atcphy_xlate(struct device *dev, + const struct of_phandle_args *args) +{ + struct apple_atcphy *atcphy =3D dev_get_drvdata(dev); + + switch (args->args[0]) { + case PHY_TYPE_USB2: + return atcphy->phy_usb2; + case PHY_TYPE_USB3: + return atcphy->phy_usb3; + case PHY_TYPE_DP: + return atcphy->phy_dp; + } + return ERR_PTR(-ENODEV); +} + +static struct phy *atcphy_xlate_dp_only(struct device *dev, + const struct of_phandle_args *args) +{ + struct apple_atcphy *atcphy =3D dev_get_drvdata(dev); + + if (args->args[0] !=3D PHY_TYPE_DP) + return ERR_PTR(-ENODEV); + return atcphy->phy_dp; +} + +static int atcphy_probe_phy_dp_only(struct apple_atcphy *atcphy) +{ + atcphy->phy_dp =3D + devm_phy_create(atcphy->dev, NULL, &apple_atc_dp_only_phy_ops); + if (IS_ERR(atcphy->phy_dp)) + return PTR_ERR(atcphy->phy_dp); + phy_set_drvdata(atcphy->phy_dp, atcphy); + + atcphy->phy_provider =3D devm_of_phy_provider_register( + atcphy->dev, atcphy_xlate_dp_only); + if (IS_ERR(atcphy->phy_provider)) + return PTR_ERR(atcphy->phy_provider); + + return 0; +} + +static int atcphy_probe_phy(struct apple_atcphy *atcphy) +{ + struct { + struct phy **phy; + const struct phy_ops *ops; + } phys[] =3D { + { &atcphy->phy_usb2, &apple_atc_usb2_phy_ops }, + { &atcphy->phy_usb3, &apple_atc_usb3_phy_ops }, + { &atcphy->phy_dp, &apple_atc_dp_phy_ops }, + }; + + for (int i =3D 0; i < ARRAY_SIZE(phys); i++) { + *phys[i].phy =3D devm_phy_create(atcphy->dev, NULL, phys[i].ops); + if (IS_ERR(*phys[i].phy)) + return PTR_ERR(*phys[i].phy); + phy_set_drvdata(*phys[i].phy, atcphy); + } + + atcphy->phy_provider =3D + devm_of_phy_provider_register(atcphy->dev, atcphy_xlate); + if (IS_ERR(atcphy->phy_provider)) + return PTR_ERR(atcphy->phy_provider); + return 0; +} + +static void _atcphy_dwc3_reset_assert(struct apple_atcphy *atcphy) +{ + clear32(atcphy->regs.pipehandler + PIPEHANDLER_AON_GEN, + PIPEHANDLER_AON_GEN_DWC3_RESET_N); + set32(atcphy->regs.pipehandler + PIPEHANDLER_AON_GEN, + PIPEHANDLER_AON_GEN_DWC3_FORCE_CLAMP_EN); +} + +static int atcphy_dwc3_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct apple_atcphy *atcphy =3D + container_of(rcdev, struct apple_atcphy, rcdev); + + guard(mutex)(&atcphy->lock); + + _atcphy_dwc3_reset_assert(atcphy); + + if (atcphy->pipehandler_up) { + atcphy_configure_pipehandler_dummy(atcphy); + atcphy->pipehandler_up =3D false; + } + + atcphy_usb2_power_off(atcphy); + + atcphy->dwc3_running =3D false; + + return 0; +} + +static int atcphy_dwc3_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct apple_atcphy *atcphy =3D + container_of(rcdev, struct apple_atcphy, rcdev); + + guard(mutex)(&atcphy->lock); + + atcphy_usb2_power_on(atcphy); + + clear32(atcphy->regs.pipehandler + PIPEHANDLER_AON_GEN, + PIPEHANDLER_AON_GEN_DWC3_FORCE_CLAMP_EN); + set32(atcphy->regs.pipehandler + PIPEHANDLER_AON_GEN, + PIPEHANDLER_AON_GEN_DWC3_RESET_N); + + atcphy->dwc3_running =3D true; + + return 0; +} + +const struct reset_control_ops atcphy_dwc3_reset_ops =3D { + .assert =3D atcphy_dwc3_reset_assert, + .deassert =3D atcphy_dwc3_reset_deassert, +}; + +static int atcphy_reset_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + return 0; +} + +static int atcphy_probe_rcdev(struct apple_atcphy *atcphy) +{ + atcphy->rcdev.owner =3D THIS_MODULE; + atcphy->rcdev.nr_resets =3D 1; + atcphy->rcdev.ops =3D &atcphy_dwc3_reset_ops; + atcphy->rcdev.of_node =3D atcphy->dev->of_node; + atcphy->rcdev.of_reset_n_cells =3D 0; + atcphy->rcdev.of_xlate =3D atcphy_reset_xlate; + + return devm_reset_controller_register(atcphy->dev, &atcphy->rcdev); +} + +static int atcphy_sw_set(struct typec_switch_dev *sw, + enum typec_orientation orientation) +{ + struct apple_atcphy *atcphy =3D typec_switch_get_drvdata(sw); + guard(mutex)(&atcphy->lock); + + switch (orientation) { + case TYPEC_ORIENTATION_NONE: + break; + case TYPEC_ORIENTATION_NORMAL: + atcphy->swap_lanes =3D false; + break; + case TYPEC_ORIENTATION_REVERSE: + atcphy->swap_lanes =3D true; + break; + } + + return 0; +} + +static int atcphy_probe_switch(struct apple_atcphy *atcphy) +{ + struct typec_switch_desc sw_desc =3D { + .drvdata =3D atcphy, + .fwnode =3D atcphy->dev->fwnode, + .set =3D atcphy_sw_set, + }; + + return PTR_ERR_OR_ZERO(typec_switch_register(atcphy->dev, &sw_desc)); +} + +static int atcphy_pipehandler_check(struct apple_atcphy *atcphy) +{ + lockdep_assert_held(&atcphy->lock); + + if (readl(atcphy->regs.pipehandler + PIPEHANDLER_LOCK_ACK) & + PIPEHANDLER_LOCK_EN) { + dev_err(atcphy->dev, + "pipehandler already locked, trying unlock and hoping for the best\n"); + + int ret =3D atcphy_pipehandler_unlock(atcphy); + + if (ret) { + dev_err(atcphy->dev, + "Failed to unlock pipehandler, this port is probably dead until replug= \n"); + return -1; + } + } + return 0; +} + +static void atcphy_configure_pipehandler_usb3(struct apple_atcphy *atcphy) +{ + int ret; + u32 reg; + + if (atcphy_pipehandler_check(atcphy)) + return; + + if (atcphy->is_host_mode && atcphy->dwc3_running) { + /* Force disable link detection */ + clear32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE_VALUES, + PIPEHANDLER_OVERRIDE_VAL_RXDETECT0 | + PIPEHANDLER_OVERRIDE_VAL_RXDETECT1); + set32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, + PIPEHANDLER_OVERRIDE_RXVALID); + set32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, + PIPEHANDLER_OVERRIDE_RXDETECT); + + ret =3D atcphy_pipehandler_lock(atcphy); + if (ret) { + dev_err(atcphy->dev, "Failed to lock pipehandler"); + return; + } + + /* BIST dance */ + + core_set32(atcphy, ACIOPHY_TOP_BIST_PHY_CFG0, + ACIOPHY_TOP_BIST_PHY_CFG0_LN0_RESET_N); + core_set32(atcphy, ACIOPHY_TOP_BIST_OV_CFG, + ACIOPHY_TOP_BIST_OV_CFG_LN0_RESET_N_OV); + ret =3D readl_poll_timeout( + atcphy->regs.core + ACIOPHY_TOP_PHY_STAT, reg, + !(reg & ACIOPHY_TOP_PHY_STAT_LN0_UNK23), 100, 100000); + if (ret) + dev_err(atcphy->dev, + "timed out waiting for ACIOPHY_TOP_PHY_STAT_LN0_UNK23\n"); + + core_set32(atcphy, ACIOPHY_TOP_BIST_READ_CTRL, + ACIOPHY_TOP_BIST_READ_CTRL_LN0_PHY_STATUS_RE); + core_clear32(atcphy, ACIOPHY_TOP_BIST_READ_CTRL, + ACIOPHY_TOP_BIST_READ_CTRL_LN0_PHY_STATUS_RE); + + core_mask32(atcphy, ACIOPHY_TOP_BIST_PHY_CFG1, + ACIOPHY_TOP_BIST_PHY_CFG1_LN0_PWR_DOWN, + FIELD_PREP(ACIOPHY_TOP_BIST_PHY_CFG1_LN0_PWR_DOWN, + 3)); + + core_set32(atcphy, ACIOPHY_TOP_BIST_OV_CFG, + ACIOPHY_TOP_BIST_OV_CFG_LN0_PWR_DOWN_OV); + core_set32(atcphy, ACIOPHY_TOP_BIST_CIOPHY_CFG1, + ACIOPHY_TOP_BIST_CIOPHY_CFG1_CLK_EN); + core_set32(atcphy, ACIOPHY_TOP_BIST_CIOPHY_CFG1, + ACIOPHY_TOP_BIST_CIOPHY_CFG1_BIST_EN); + writel(0, atcphy->regs.core + ACIOPHY_TOP_BIST_CIOPHY_CFG1); + + ret =3D readl_poll_timeout( + atcphy->regs.core + ACIOPHY_TOP_PHY_STAT, reg, + (reg & ACIOPHY_TOP_PHY_STAT_LN0_UNK0), 100, 100000); + if (ret) + dev_warn( + atcphy->dev, + "timed out waiting for ACIOPHY_TOP_PHY_STAT_LN0_UNK0\n"); + + ret =3D readl_poll_timeout( + atcphy->regs.core + ACIOPHY_TOP_PHY_STAT, reg, + !(reg & ACIOPHY_TOP_PHY_STAT_LN0_UNK23), 100, 100000); + if (ret) + dev_warn( + atcphy->dev, + "timed out waiting for ACIOPHY_TOP_PHY_STAT_LN0_UNK23\n"); + + /* Clear reset for non-selected USB3 PHY (?) */ + + mask32(atcphy->regs.pipehandler + + PIPEHANDLER_NONSELECTED_OVERRIDE, + PIPEHANDLER_NATIVE_POWER_DOWN, 0x3); // TOOD: FIELD_PREP + clear32(atcphy->regs.pipehandler + + PIPEHANDLER_NONSELECTED_OVERRIDE, + PIPEHANDLER_NATIVE_RESET); + + /* More BIST stuff (?) */ + writel(0, atcphy->regs.core + ACIOPHY_TOP_BIST_OV_CFG); + core_set32(atcphy, ACIOPHY_TOP_BIST_CIOPHY_CFG1, + ACIOPHY_TOP_BIST_CIOPHY_CFG1_CLK_EN); + core_set32(atcphy, ACIOPHY_TOP_BIST_CIOPHY_CFG1, + ACIOPHY_TOP_BIST_CIOPHY_CFG1_BIST_EN); + } + + /* Configure PIPE mux to USB3 PHY */ + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, + PIPEHANDLED_MUX_CTRL_CLK_OFF)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_DATA, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_DATA, + PIPEHANDLED_MUX_CTRL_DATA_USB3)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, + PIPEHANDLED_MUX_CTRL_CLK_USB3)); + udelay(10); + + /* Remove link detection override */ + clear32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, + PIPEHANDLER_OVERRIDE_RXVALID); + clear32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, + PIPEHANDLER_OVERRIDE_RXDETECT); + + if (atcphy->is_host_mode && atcphy->dwc3_running) { + ret =3D atcphy_pipehandler_unlock(atcphy); + if (ret) { + dev_err(atcphy->dev, "Failed to unlock pipehandler"); + return; + } + } +} + +static void atcphy_configure_pipehandler_dummy(struct apple_atcphy *atcphy) +{ + int ret; + + if (atcphy_pipehandler_check(atcphy)) + return; + + /* Force disable link detection */ + clear32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE_VALUES, + PIPEHANDLER_OVERRIDE_VAL_RXDETECT0 | + PIPEHANDLER_OVERRIDE_VAL_RXDETECT1); + set32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, + PIPEHANDLER_OVERRIDE_RXVALID); + set32(atcphy->regs.pipehandler + PIPEHANDLER_OVERRIDE, + PIPEHANDLER_OVERRIDE_RXDETECT); + + if (atcphy->is_host_mode && atcphy->dwc3_running) { + ret =3D atcphy_pipehandler_lock(atcphy); + if (ret) { + dev_err(atcphy->dev, "Failed to lock pipehandler"); + return; + } + } + + /* Switch to dummy PHY */ + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, + PIPEHANDLED_MUX_CTRL_CLK_OFF)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_DATA, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_DATA, + PIPEHANDLED_MUX_CTRL_DATA_DUMMY)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, + PIPEHANDLED_MUX_CTRL_CLK_DUMMY)); + udelay(10); + + if (atcphy->is_host_mode && atcphy->dwc3_running) { + ret =3D atcphy_pipehandler_unlock(atcphy); + if (ret) { + dev_err(atcphy->dev, "Failed to unlock pipehandler"); + return; + } + } + + mask32(atcphy->regs.pipehandler + PIPEHANDLER_NONSELECTED_OVERRIDE, + PIPEHANDLER_NATIVE_POWER_DOWN, + FIELD_PREP(PIPEHANDLER_NATIVE_POWER_DOWN, 2)); + set32(atcphy->regs.pipehandler + PIPEHANDLER_NONSELECTED_OVERRIDE, + PIPEHANDLER_NATIVE_RESET); +} + +static void atcphy_configure_pipehandler(struct apple_atcphy *atcphy) +{ + lockdep_assert_held(&atcphy->lock); + + switch (atcphy_modes[atcphy->target_mode].pipehandler_state) { + case ATCPHY_PIPEHANDLER_STATE_INVALID: + dev_err(atcphy->dev, + "ATCPHY_PIPEHANDLER_STATE_INVALID state requested; falling through to U= SB2\n"); + fallthrough; + case ATCPHY_PIPEHANDLER_STATE_DUMMY: + atcphy_configure_pipehandler_dummy(atcphy); + break; + case ATCPHY_PIPEHANDLER_STATE_USB3: + atcphy_configure_pipehandler_usb3(atcphy); + atcphy->pipehandler_up =3D true; + break; + case ATCPHY_PIPEHANDLER_STATE_USB4: + dev_err(atcphy->dev, + "ATCPHY_PIPEHANDLER_STATE_USB4 not implemented; falling back to USB2\n"= ); + atcphy_configure_pipehandler_dummy(atcphy); + atcphy->pipehandler_up =3D true; + break; + } +} + +static void atcphy_setup_pipehandler(struct apple_atcphy *atcphy) +{ + lockdep_assert_held(&atcphy->lock); + WARN_ON(atcphy->pipehandler_state !=3D ATCPHY_PIPEHANDLER_STATE_INVALID); + + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, + PIPEHANDLED_MUX_CTRL_CLK_OFF)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_DATA, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_DATA, + PIPEHANDLED_MUX_CTRL_DATA_DUMMY)); + udelay(10); + mask32(atcphy->regs.pipehandler + PIPEHANDLER_MUX_CTRL, + PIPEHANDLED_MUX_CTRL_CLK, + FIELD_PREP(PIPEHANDLED_MUX_CTRL_CLK, + PIPEHANDLED_MUX_CTRL_CLK_DUMMY)); + udelay(10); + + atcphy->pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_DUMMY; +} + +static int atcphy_mux_set(struct typec_mux_dev *mux, + struct typec_mux_state *state) +{ + struct apple_atcphy *atcphy =3D typec_mux_get_drvdata(mux); + guard(mutex)(&atcphy->lock); + + atcphy->is_host_mode =3D state->data_role =3D=3D TYPEC_HOST; + + if (state->mode =3D=3D TYPEC_STATE_SAFE) { + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } else if (state->mode =3D=3D TYPEC_STATE_USB) { + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB3; + } else if (!state->alt && state->mode =3D=3D TYPEC_MODE_USB4) { + struct enter_usb_data *data =3D state->data; + u32 eudo_usb_mode =3D FIELD_GET(EUDO_USB_MODE_MASK, data->eudo); + + switch (eudo_usb_mode) { + case EUDO_USB_MODE_USB2: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB2; + break; + case EUDO_USB_MODE_USB3: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB3; + break; + case EUDO_USB_MODE_USB4: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB4; + break; + default: + dev_warn(atcphy->dev, + "Unsupported EUDO USB mode: 0x%x.\n", + eudo_usb_mode); + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } + } else if (state->alt && state->alt->svid =3D=3D USB_TYPEC_TBT_SID) { + atcphy->target_mode =3D APPLE_ATCPHY_MODE_TBT; + } else if (state->alt && state->alt->svid =3D=3D USB_TYPEC_DP_SID) { + switch (state->mode) { + case TYPEC_DP_STATE_C: + case TYPEC_DP_STATE_E: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_DP; + break; + case TYPEC_DP_STATE_D: + atcphy->target_mode =3D APPLE_ATCPHY_MODE_USB3_DP; + break; + default: + dev_warn( + atcphy->dev, + "Unsupported DP pin assignment: 0x%lx, your connected device will not = work.\n", + state->mode); + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } + } else if (state->alt) { + dev_warn( + atcphy->dev, + "Unknown alternate mode SVID: 0x%x, your connected device will not work= .\n", + state->alt->svid); + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } else { + dev_warn( + atcphy->dev, + "Unknown mode: 0x%lx, your connected device will not work.\n", + state->mode); + atcphy->target_mode =3D APPLE_ATCPHY_MODE_OFF; + } + + if (atcphy->mode =3D=3D atcphy->target_mode) + return 0; + + /* + * If the pipehandler is up the PHY has previously been up and we need + * to wait for dwc3 to shut down before we can reconfigure the PHY. + * Thus, defer reconfiguration to atcphy_usb3_power_off. + * The Type-C port controller will ensure this is called through a role + * switch to USB_ROLE_NONE (and then possibly to HOST/DEVICE if the + * target mode isn't off). + */ + if (!atcphy->pipehandler_up) + return atcphy_configure(atcphy, atcphy->target_mode); + return 0; +} + +static int atcphy_probe_mux(struct apple_atcphy *atcphy) +{ + struct typec_mux_desc mux_desc =3D { + .drvdata =3D atcphy, + .fwnode =3D atcphy->dev->fwnode, + .set =3D atcphy_mux_set, + }; + + return PTR_ERR_OR_ZERO(typec_mux_register(atcphy->dev, &mux_desc)); +} + +static int atcphy_load_tunables(struct apple_atcphy *atcphy) +{ + int ret; + struct { + const char *dt_name; + struct apple_tunable *tunable; + } tunables[] =3D { + { "apple,tunable-fuses", &atcphy->tunables.fuses }, + { "apple,tunable-axi2af", &atcphy->tunables.axi2af }, + { "apple,tunable-common", &atcphy->tunables.common }, + { "apple,tunable-lane0-usb", &atcphy->tunables.lane_usb3[0] }, + { "apple,tunable-lane1-usb", &atcphy->tunables.lane_usb3[1] }, + { "apple,tunable-lane0-cio", &atcphy->tunables.lane_usb4[0] }, + { "apple,tunable-lane1-cio", &atcphy->tunables.lane_usb4[1] }, + { "apple,tunable-lane0-dp", &atcphy->tunables.lane_displayport[0] }, + { "apple,tunable-lane1-dp", &atcphy->tunables.lane_displayport[1] }, + }; + + for (int i =3D 0; i < ARRAY_SIZE(tunables); i++) { + ret =3D devm_apple_parse_tunable(atcphy->dev, atcphy->np, + tunables[i].tunable, + tunables[i].dt_name); + if (ret) { + dev_err(atcphy->dev, "Failed to read tunable %s: %d\n", + tunables[i].dt_name, ret); + return ret; + } + } + + return 0; +} + +static void atcphy_detach_genpd(void *data) +{ + struct apple_atcphy *atcphy =3D data; + int i; + + if (atcphy->pd_count <=3D 1) + return; + + for (i =3D atcphy->pd_count - 1; i >=3D 0; i--) { + if (atcphy->pd_link[i]) + device_link_del(atcphy->pd_link[i]); + if (!IS_ERR_OR_NULL(atcphy->pd_dev[i])) + dev_pm_domain_detach(atcphy->pd_dev[i], true); + } +} + +static int atcphy_attach_genpd(struct apple_atcphy *atcphy) +{ + struct device *dev =3D atcphy->dev; + int i; + + atcphy->pd_count =3D of_count_phandle_with_args( + dev->of_node, "power-domains", "#power-domain-cells"); + if (atcphy->pd_count <=3D 1) + return 0; + + atcphy->pd_dev =3D devm_kcalloc(dev, atcphy->pd_count, + sizeof(*atcphy->pd_dev), GFP_KERNEL); + if (!atcphy->pd_dev) + return -ENOMEM; + + atcphy->pd_link =3D devm_kcalloc(dev, atcphy->pd_count, + sizeof(*atcphy->pd_link), GFP_KERNEL); + if (!atcphy->pd_link) + return -ENOMEM; + + for (i =3D 0; i < atcphy->pd_count; i++) { + atcphy->pd_dev[i] =3D dev_pm_domain_attach_by_id(dev, i); + if (IS_ERR(atcphy->pd_dev[i])) { + atcphy_detach_genpd(atcphy); + return PTR_ERR(atcphy->pd_dev[i]); + } + + atcphy->pd_link[i] =3D + device_link_add(dev, atcphy->pd_dev[i], + DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME | + DL_FLAG_RPM_ACTIVE); + if (!atcphy->pd_link[i]) { + atcphy_detach_genpd(atcphy); + return -EINVAL; + } + } + + return devm_add_action_or_reset(dev, atcphy_detach_genpd, atcphy); +} + +static int atcphy_probe_all(struct apple_atcphy *atcphy) +{ + int ret; + + ret =3D atcphy_probe_rcdev(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, "Probing rcdev failed"); + ret =3D atcphy_probe_mux(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, "Probing mux failed"); + ret =3D atcphy_probe_switch(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, "Probing switch failed"); + ret =3D atcphy_probe_phy(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, "Probing phy failed"); + + return 0; +} + +static int atcphy_probe_dp_only(struct apple_atcphy *atcphy) +{ + int ret; + + /* + * This PHY is internally hard-wired to a DisplayPort-to-HDMI + * converter with a constant lane orientation. We also don't + * need any of the USB or Thunderbolt features. + */ + atcphy->swap_lanes =3D false; + + ret =3D atcphy_probe_phy_dp_only(atcphy); + if (ret) + return dev_err_probe(atcphy->dev, ret, + "Probing dp-only phy failed"); + + return 0; +} + +static int atcphy_map_resources(struct platform_device *pdev, + struct apple_atcphy *atcphy) +{ + struct { + const char *name; + void __iomem **addr; + } resources[] =3D { + { "core", &atcphy->regs.core }, + { "lpdptx", &atcphy->regs.lpdptx }, + { "axi2af", &atcphy->regs.axi2af }, + { "usb2phy", &atcphy->regs.usb2phy }, + { "pipehandler", &atcphy->regs.pipehandler }, + }; + + for (int i =3D 0; i < ARRAY_SIZE(resources); i++) { + *resources[i].addr =3D devm_platform_ioremap_resource_byname( + pdev, resources[i].name); + if (IS_ERR(resources[i].addr)) + return dev_err_probe(atcphy->dev, + PTR_ERR(resources[i].addr), + "Unable to map %s regs", + resources[i].name); + } + + return 0; +} + +static int atcphy_probe(struct platform_device *pdev) +{ + struct apple_atcphy *atcphy; + struct device *dev =3D &pdev->dev; + int ret; + + atcphy =3D devm_kzalloc(&pdev->dev, sizeof(*atcphy), GFP_KERNEL); + if (!atcphy) + return -ENOMEM; + + atcphy->dev =3D dev; + atcphy->np =3D dev->of_node; + atcphy->hw =3D of_device_get_match_data(dev); + mutex_init(&atcphy->lock); + platform_set_drvdata(pdev, atcphy); + + ret =3D atcphy_attach_genpd(atcphy); + if (ret < 0) + return dev_err_probe(dev, ret, + "Failed to attach power domains"); + ret =3D atcphy_map_resources(pdev, atcphy); + if (ret) + return ret; + ret =3D atcphy_load_tunables(atcphy); + if (ret) + return ret; + + atcphy->mode =3D APPLE_ATCPHY_MODE_OFF; + atcphy->pipehandler_state =3D ATCPHY_PIPEHANDLER_STATE_INVALID; + + mutex_lock(&atcphy->lock); + /* Reset dwc3 on probe, let dwc3 (consumer) deassert it */ + _atcphy_dwc3_reset_assert(atcphy); + atcphy_power_off(atcphy); + atcphy_setup_pipehandler(atcphy); + + if (atcphy->hw->dp_only) + ret =3D atcphy_probe_dp_only(atcphy); + else + ret =3D atcphy_probe_all(atcphy); + mutex_unlock(&atcphy->lock); + + return ret; +} + +static const struct apple_atcphy_hw atcphy_t8103 =3D {}; + +static const struct apple_atcphy_hw atcphy_t6000_dp_only =3D { + .dp_only =3D true, +}; + +static const struct of_device_id atcphy_match[] =3D { + { + .compatible =3D "apple,t6000-atcphy", + .data =3D &atcphy_t8103, + }, + { + .compatible =3D "apple,t6000-atcphy-dp-only", + .data =3D &atcphy_t6000_dp_only, + }, + { + .compatible =3D "apple,t6020-atcphy", + .data =3D &atcphy_t8103, + }, + { + .compatible =3D "apple,t8103-atcphy", + .data =3D &atcphy_t8103, + }, + { + .compatible =3D "apple,t8112-atcphy", + .data =3D &atcphy_t8103, + }, + {}, +}; +MODULE_DEVICE_TABLE(of, atcphy_match); + +static struct platform_driver atcphy_driver =3D { + .driver =3D { + .name =3D "phy-apple-atc", + .of_match_table =3D atcphy_match, + }, + .probe =3D atcphy_probe, +}; +module_platform_driver(atcphy_driver); + +MODULE_AUTHOR("Sven Peter "); +MODULE_DESCRIPTION("Apple Type-C PHY driver"); +MODULE_LICENSE("GPL"); --=20 2.34.1 From nobody Sat Oct 4 00:26:52 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED0432FB625; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250821-atcphy-6-17-v1-22-172beda182b8@kernel.org> References: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> In-Reply-To: <20250821-atcphy-6-17-v1-0-172beda182b8@kernel.org> To: Greg Kroah-Hartman , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Felipe Balbi , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Vinod Koul , Kishon Vijay Abraham I , Thinh Nguyen , Heikki Krogerus , Philipp Zabel Cc: linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, asahi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, Sven Peter , Hector Martin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=10871; i=sven@kernel.org; h=from:subject:message-id; bh=2CrMi3bli5OVyaXQbvJOqLF2o0yRqYDCyXNV/LrPZAo=; b=owGbwMvMwCHmIlirolUq95LxtFoSQ8Zy2/OzC7ZdaXxlcb2xLs9uaovut4PuMzQEWvr2ad45K cgU+Uqlo5SFQYyDQVZMkWX7fnvTJw/fCC7ddOk9zBxWJpAhDFycAjCRGYkM/4x++UnHvOnl45ay UY7e7xysLRcvUaD29KR4zUGViVelOBkZvhw5WJ7X6scg+d5qxtH+lg/P7t63/xpZElb+Q6S8MMi eDwA= X-Developer-Key: i=sven@kernel.org; a=openpgp; fpr=A1E3E34A2B3C820DBC4955E5993B08092F131F93 X-Endpoint-Received: by B4 Relay for sven@kernel.org/default with auth_id=407 Add all nodes and connections required to make USB3 work on M1-based Apple machines. Co-developed-by: Hector Martin Signed-off-by: Hector Martin Signed-off-by: Sven Peter --- arch/arm64/boot/dts/apple/t8103-j274.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-j293.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-j313.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-j456.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-j457.dts | 12 +++ arch/arm64/boot/dts/apple/t8103-jxxx.dtsi | 137 ++++++++++++++++++++++++++= ++++ arch/arm64/boot/dts/apple/t8103.dtsi | 105 +++++++++++++++++++++++ 7 files changed, 302 insertions(+) diff --git a/arch/arm64/boot/dts/apple/t8103-j274.dts b/arch/arm64/boot/dts= /apple/t8103-j274.dts index 1c3e37f86d46d7b5d733717b47c4b57dc55e1201..968fe22163d4431fe5e70498546= 87e61e0ec50f1 100644 --- a/arch/arm64/boot/dts/apple/t8103-j274.dts +++ b/arch/arm64/boot/dts/apple/t8103-j274.dts @@ -29,6 +29,18 @@ &wifi0 { brcm,board-type =3D "apple,atlantisb"; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Back-left"; +}; + +&typec1 { + label =3D "USB-C Back-right"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-j293.dts b/arch/arm64/boot/dts= /apple/t8103-j293.dts index 5b3c42e9f0e6776241bf746d3458766e44e3639a..678f89c3d47fbf2d0705b46bb8f= eba3fa018ca7a 100644 --- a/arch/arm64/boot/dts/apple/t8103-j293.dts +++ b/arch/arm64/boot/dts/apple/t8103-j293.dts @@ -46,6 +46,18 @@ &wifi0 { brcm,board-type =3D "apple,honshu"; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Left-back"; +}; + +&typec1 { + label =3D "USB-C Left-front"; +}; + &i2c2 { status =3D "okay"; }; diff --git a/arch/arm64/boot/dts/apple/t8103-j313.dts b/arch/arm64/boot/dts= /apple/t8103-j313.dts index 97a4344d8dca685708aff136af92a1b316f3c3dd..bce9b911009e2b0caa9d8b2222c= d1e8c3215f3b9 100644 --- a/arch/arm64/boot/dts/apple/t8103-j313.dts +++ b/arch/arm64/boot/dts/apple/t8103-j313.dts @@ -41,3 +41,15 @@ &wifi0 { &fpwm1 { status =3D "okay"; }; + +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Left-back"; +}; + +&typec1 { + label =3D "USB-C Left-front"; +}; diff --git a/arch/arm64/boot/dts/apple/t8103-j456.dts b/arch/arm64/boot/dts= /apple/t8103-j456.dts index 58c8e43789b4861544e20c717124ede3327be010..9983e11cacdf19d0a92ede108ce= ac21b7a02d5da 100644 --- a/arch/arm64/boot/dts/apple/t8103-j456.dts +++ b/arch/arm64/boot/dts/apple/t8103-j456.dts @@ -47,6 +47,18 @@ hpm3: usb-pd@3c { }; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Back-right"; +}; + +&typec1 { + label =3D "USB-C Back-right-middle"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-j457.dts b/arch/arm64/boot/dts= /apple/t8103-j457.dts index 152f95fd49a2118093396838fbd8b6bd1b518f81..a622ff607d407519000d1526b72= 44419a59644a3 100644 --- a/arch/arm64/boot/dts/apple/t8103-j457.dts +++ b/arch/arm64/boot/dts/apple/t8103-j457.dts @@ -29,6 +29,18 @@ &wifi0 { brcm,board-type =3D "apple,santorini"; }; =20 +/* + * Provide labels for the USB type C ports. + */ + +&typec0 { + label =3D "USB-C Back-right"; +}; + +&typec1 { + label =3D "USB-C Back-left"; +}; + /* * Force the bus number assignments so that we can declare some of the * on-board devices and properties that are populated by the bootloader diff --git a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi b/arch/arm64/boot/dt= s/apple/t8103-jxxx.dtsi index 0c8206156bfefda8a32c869787b2e0c8e67a9d17..758b2196954bc139c201d252984= 44f59c7832ea5 100644 --- a/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi +++ b/arch/arm64/boot/dts/apple/t8103-jxxx.dtsi @@ -15,6 +15,8 @@ aliases { serial0 =3D &serial0; serial2 =3D &serial2; wifi0 =3D &wifi0; + atcphy0 =3D &atcphy0; + atcphy1 =3D &atcphy1; }; =20 chosen { @@ -53,6 +55,30 @@ hpm0: usb-pd@38 { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <106 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec0: connector { + compatible =3D "usb-c-connector"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec0_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_0_hs>; + }; + }; + port@1 { + reg =3D <1>; + typec0_connector_ss: endpoint { + remote-endpoint =3D <&atcphy0_typec_lanes>; + }; + }; + }; + }; }; =20 hpm1: usb-pd@3f { @@ -61,6 +87,117 @@ hpm1: usb-pd@3f { interrupt-parent =3D <&pinctrl_ap>; interrupts =3D <106 IRQ_TYPE_LEVEL_LOW>; interrupt-names =3D "irq"; + + typec1: connector { + compatible =3D "usb-c-connector"; + power-role =3D "dual"; + data-role =3D "dual"; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + typec1_connector_hs: endpoint { + remote-endpoint =3D <&dwc3_1_hs>; + }; + }; + + port@1 { + reg =3D <1>; + typec1_connector_ss: endpoint { + remote-endpoint =3D <&atcphy1_typec_lanes>; + }; + }; + }; + }; + }; +}; + +/* USB controllers */ +&dwc3_0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_0_hs: endpoint { + remote-endpoint =3D <&typec0_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_0_ss: endpoint { + remote-endpoint =3D <&atcphy0_usb3>; + }; + }; + }; +}; + +&dwc3_1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + dwc3_1_hs: endpoint { + remote-endpoint =3D <&typec1_connector_hs>; + }; + }; + + port@1 { + reg =3D <1>; + dwc3_1_ss: endpoint { + remote-endpoint =3D <&atcphy1_usb3>; + }; + }; + }; +}; + +/* Type-C PHYs */ +&atcphy0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy0_typec_lanes: endpoint { + remote-endpoint =3D <&typec0_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy0_usb3: endpoint { + remote-endpoint =3D <&dwc3_0_ss>; + }; + }; + }; +}; + +&atcphy1 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + atcphy1_typec_lanes: endpoint { + remote-endpoint =3D <&typec1_connector_ss>; + }; + }; + + port@1 { + reg =3D <1>; + atcphy1_usb3: endpoint { + remote-endpoint =3D <&dwc3_1_ss>; + }; + }; }; }; =20 diff --git a/arch/arm64/boot/dts/apple/t8103.dtsi b/arch/arm64/boot/dts/app= le/t8103.dtsi index 589ddc0397995ecf6fc11b135164229ab1ee7cf8..659a73fafccb04c1b944f6b7afe= b0e372d4bb748 100644 --- a/arch/arm64/boot/dts/apple/t8103.dtsi +++ b/arch/arm64/boot/dts/apple/t8103.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include #include #include =20 @@ -972,6 +973,110 @@ nvme@27bcc0000 { resets =3D <&ps_ans2>; }; =20 + dwc3_0: usb@382280000 { + compatible =3D "apple,t8103-dwc3", "snps,dwc3"; + reg =3D <0x3 0x82280000 0x0 0x100000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&dwc3_0_dart_0 0>, <&dwc3_0_dart_1 1>; + power-domains =3D <&ps_atc0_usb>; + resets =3D <&atcphy0>; + phys =3D <&atcphy0 PHY_TYPE_USB2>, <&atcphy0 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + dwc3_0_dart_0: iommu@382f00000 { + compatible =3D "apple,t8103-dart"; + reg =3D <0x3 0x82f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc0_usb>; + }; + + dwc3_0_dart_1: iommu@382f80000 { + compatible =3D "apple,t8103-dart"; + reg =3D <0x3 0x82f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc0_usb>; + }; + + atcphy0: phy@383000000 { + compatible =3D "apple,t8103-atcphy"; + reg =3D <0x3 0x83000000 0x0 0x4c000>, + <0x3 0x83050000 0x0 0x8000>, + <0x3 0x80000000 0x0 0x4000>, + <0x3 0x82a90000 0x0 0x4000>, + <0x3 0x82a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&ps_atc0_usb>; + //power-domains =3D <&ps_atc0_usb_aon>, <&ps_atc0_common>; + }; + + dwc3_1: usb@502280000 { + compatible =3D "apple,t8103-dwc3", "snps,dwc3"; + reg =3D <0x5 0x02280000 0x0 0x100000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + dr_mode =3D "otg"; + usb-role-switch; + role-switch-default-mode =3D "host"; + iommus =3D <&dwc3_1_dart_0 0>, <&dwc3_1_dart_1 1>; + power-domains =3D <&ps_atc1_usb>; + resets =3D <&atcphy1>; + phys =3D <&atcphy1 PHY_TYPE_USB2>, <&atcphy1 PHY_TYPE_USB3>; + phy-names =3D "usb2-phy", "usb3-phy"; + }; + + dwc3_1_dart_0: iommu@502f00000 { + compatible =3D "apple,t8103-dart"; + reg =3D <0x5 0x02f00000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc1_usb>; + }; + + dwc3_1_dart_1: iommu@502f80000 { + compatible =3D "apple,t8103-dart"; + reg =3D <0x5 0x02f80000 0x0 0x4000>; + interrupt-parent =3D <&aic>; + interrupts =3D ; + #iommu-cells =3D <1>; + power-domains =3D <&ps_atc1_usb>; + }; + + atcphy1: phy@503000000 { + compatible =3D "apple,t8103-atcphy"; + reg =3D <0x5 0x03000000 0x0 0x4c000>, + <0x5 0x03050000 0x0 0x8000>, + <0x5 0x0 0x0 0x4000>, + <0x5 0x02a90000 0x0 0x4000>, + <0x5 0x02a84000 0x0 0x4000>; + reg-names =3D "core", "lpdptx", "axi2af", "usb2phy", + "pipehandler"; + + #phy-cells =3D <1>; + #reset-cells =3D <0>; + + orientation-switch; + mode-switch; + power-domains =3D <&ps_atc1_usb>; + //power-domains =3D <&ps_atc1_usb_aon>, <&ps_atc1_common>; + }; + pcie0_dart_0: iommu@681008000 { compatible =3D "apple,t8103-dart"; reg =3D <0x6 0x81008000 0x0 0x4000>; --=20 2.34.1