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Wed, 20 Aug 2025 13:23:31 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:9b1:f84b:89f6:b00e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c0754f3b7esm8471059f8f.30.2025.08.20.13.23.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 13:23:30 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Geert Uytterhoeven , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Magnus Damm , Wolfram Sang Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 5/6] watchdog: rzv2h: Add support for RZ/T2H Date: Wed, 20 Aug 2025 21:23:21 +0100 Message-ID: <20250820202322.2051969-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250820202322.2051969-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250820202322.2051969-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for the RZ/T2H watchdog timer. The RZ/T2H requires control of the watchdog counter using the WDT Debug Control Register (WDTDCR), which allows explicitly stopping and starting the counter. This behavior differs from RZ/V2H, which doesn't have WDTDCR, so the driver is extended to handle this requirement. To support this, a new `wdtdcr` flag is introduced in the `rzv2h_of_data` structure. When set, the driver maps the WDTDCR register and uses it to control the watchdog counter in the start, stop, and restart callbacks. Additionally, the clock divisor and count source for RZ/T2H are defined to match its hardware configuration. Signed-off-by: Lad Prabhakar Reviewed-by: Wolfram Sang Reviewed-by: Guenter Roeck --- v3->v4: - No changes. v2->v3: - Updated commit message `doesn't use WDTDCR` to `doesn't have WDTDCR`. - Updated the comment in rzv2h_wdt_start to clarify the clock divisor and timeout period select bits for RZ/T2H. - Updated rzt2h_wdt_of_data to include tops and timeout_cycles for RZ/T2H. =20 - Added reviewed-by from Wolfram. v1->v2: - No changes. --- drivers/watchdog/rzv2h_wdt.c | 84 ++++++++++++++++++++++++++++++++++-- 1 file changed, 81 insertions(+), 3 deletions(-) diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c index e71d1e108f69..ee3ed5a6d98e 100644 --- a/drivers/watchdog/rzv2h_wdt.c +++ b/drivers/watchdog/rzv2h_wdt.c @@ -21,11 +21,17 @@ #define WDTSR 0x04 /* WDT Status Register RW, 16 */ #define WDTRCR 0x06 /* WDT Reset Control Register RW, 8 */ =20 +/* This register is only available on RZ/T2H and RZ/N2H SoCs */ +#define WDTDCR 0x00 /* WDT Debug Control Register RW, 32 */ + #define WDTCR_TOPS_1024 0x00 +#define WDTCR_TOPS_4096 0x01 #define WDTCR_TOPS_16384 0x03 =20 #define WDTCR_CKS_CLK_1 0x00 +#define WDTCR_CKS_CLK_4 0x10 #define WDTCR_CKS_CLK_256 0x50 +#define WDTCR_CKS_CLK_8192 0x80 =20 #define WDTCR_RPES_0 0x300 #define WDTCR_RPES_75 0x000 @@ -35,6 +41,8 @@ =20 #define WDTRCR_RSTIRQS BIT(7) =20 +#define WDTDCR_WDTSTOPCTRL BIT(0) + #define WDT_DEFAULT_TIMEOUT 60U =20 static bool nowayout =3D WATCHDOG_NOWAYOUT; @@ -54,10 +62,12 @@ struct rzv2h_of_data { u8 tops; u16 timeout_cycles; enum rzv2h_wdt_count_source count_source; + bool wdtdcr; }; =20 struct rzv2h_wdt_priv { void __iomem *base; + void __iomem *wdtdcr; struct clk *pclk; struct clk *oscclk; struct reset_control *rstc; @@ -79,6 +89,20 @@ static int rzv2h_wdt_ping(struct watchdog_device *wdev) return 0; } =20 +static void rzt2h_wdt_wdtdcr_count_stop(struct rzv2h_wdt_priv *priv) +{ + u32 reg =3D readl(priv->wdtdcr + WDTDCR); + + writel(reg | WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR); +} + +static void rzt2h_wdt_wdtdcr_count_start(struct rzv2h_wdt_priv *priv) +{ + u32 reg =3D readl(priv->wdtdcr + WDTDCR); + + writel(reg & ~WDTDCR_WDTSTOPCTRL, priv->wdtdcr + WDTDCR); +} + static void rzv2h_wdt_setup(struct watchdog_device *wdev, u16 wdtcr) { struct rzv2h_wdt_priv *priv =3D watchdog_get_drvdata(wdev); @@ -114,14 +138,21 @@ static int rzv2h_wdt_start(struct watchdog_device *wd= ev) =20 /* * WDTCR - * - CKS[7:4] - Clock Division Ratio Select - 0101b: oscclk/256 + * - CKS[7:4] - Clock Division Ratio Select + * - 0101b: oscclk/256 for RZ/V2H(P) + * - 1000b: pclkl/8192 for RZ/T2H * - RPSS[13:12] - Window Start Position Select - 11b: 100% * - RPES[9:8] - Window End Position Select - 11b: 0% - * - TOPS[1:0] - Timeout Period Select - 11b: 16384 cycles (3FFFh) + * - TOPS[1:0] - Timeout Period Select + * - 11b: 16384 cycles (3FFFh) for RZ/V2H(P) + * - 01b: 4096 cycles (0FFFh) for RZ/T2H */ rzv2h_wdt_setup(wdev, of_data->cks_max | WDTCR_RPSS_100 | WDTCR_RPES_0 | of_data->tops); =20 + if (priv->of_data->wdtdcr) + rzt2h_wdt_wdtdcr_count_start(priv); + /* * Down counting starts after writing the sequence 00h -> FFh to the * WDTRR register. Hence, call the ping operation after loading the count= er. @@ -140,6 +171,9 @@ static int rzv2h_wdt_stop(struct watchdog_device *wdev) if (ret) return ret; =20 + if (priv->of_data->wdtdcr) + rzt2h_wdt_wdtdcr_count_stop(priv); + ret =3D pm_runtime_put(wdev->parent); if (ret < 0) return ret; @@ -192,7 +226,9 @@ static int rzv2h_wdt_restart(struct watchdog_device *wd= ev, =20 /* * WDTCR - * - CKS[7:4] - Clock Division Ratio Select - 0000b: oscclk/1 + * - CKS[7:4] - Clock Division Ratio Select + * - 0000b: oscclk/1 for RZ/V2H(P) + * - 0100b: pclkl/4 for RZ/T2H * - RPSS[13:12] - Window Start Position Select - 00b: 25% * - RPES[9:8] - Window End Position Select - 00b: 75% * - TOPS[1:0] - Timeout Period Select - 00b: 1024 cycles (03FFh) @@ -200,6 +236,9 @@ static int rzv2h_wdt_restart(struct watchdog_device *wd= ev, rzv2h_wdt_setup(wdev, priv->of_data->cks_min | WDTCR_RPSS_25 | WDTCR_RPES_75 | WDTCR_TOPS_1024); =20 + if (priv->of_data->wdtdcr) + rzt2h_wdt_wdtdcr_count_start(priv); + rzv2h_wdt_ping(wdev); =20 /* wait for underflow to trigger... */ @@ -216,6 +255,28 @@ static const struct watchdog_ops rzv2h_wdt_ops =3D { .restart =3D rzv2h_wdt_restart, }; =20 +static int rzt2h_wdt_wdtdcr_init(struct platform_device *pdev, + struct rzv2h_wdt_priv *priv) +{ + int ret; + + priv->wdtdcr =3D devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(priv->wdtdcr)) + return PTR_ERR(priv->wdtdcr); + + ret =3D pm_runtime_resume_and_get(&pdev->dev); + if (ret) + return ret; + + rzt2h_wdt_wdtdcr_count_stop(priv); + + ret =3D pm_runtime_put(&pdev->dev); + if (ret < 0) + return ret; + + return 0; +} + static int rzv2h_wdt_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -265,6 +326,12 @@ static int rzv2h_wdt_probe(struct platform_device *pde= v) if (ret) return ret; =20 + if (priv->of_data->wdtdcr) { + ret =3D rzt2h_wdt_wdtdcr_init(pdev, priv); + if (ret) + return dev_err_probe(dev, ret, "WDTDCR init failed\n"); + } + priv->wdev.min_timeout =3D 1; priv->wdev.timeout =3D WDT_DEFAULT_TIMEOUT; priv->wdev.info =3D &rzv2h_wdt_ident; @@ -281,6 +348,16 @@ static int rzv2h_wdt_probe(struct platform_device *pde= v) return devm_watchdog_register_device(dev, &priv->wdev); } =20 +static const struct rzv2h_of_data rzt2h_wdt_of_data =3D { + .cks_min =3D WDTCR_CKS_CLK_4, + .cks_max =3D WDTCR_CKS_CLK_8192, + .cks_div =3D 8192, + .tops =3D WDTCR_TOPS_4096, + .timeout_cycles =3D 4096, + .count_source =3D COUNT_SOURCE_PCLK, + .wdtdcr =3D true, +}; + static const struct rzv2h_of_data rzv2h_wdt_of_data =3D { .cks_min =3D WDTCR_CKS_CLK_1, .cks_max =3D WDTCR_CKS_CLK_256, @@ -292,6 +369,7 @@ static const struct rzv2h_of_data rzv2h_wdt_of_data =3D= { =20 static const struct of_device_id rzv2h_wdt_ids[] =3D { { .compatible =3D "renesas,r9a09g057-wdt", .data =3D &rzv2h_wdt_of_data }, + { .compatible =3D "renesas,r9a09g077-wdt", .data =3D &rzt2h_wdt_of_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzv2h_wdt_ids); --=20 2.51.0