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Wed, 20 Aug 2025 13:23:27 -0700 (PDT) Received: from iku.Home ([2a06:5906:61b:2d00:9b1:f84b:89f6:b00e]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c0754f3b7esm8471059f8f.30.2025.08.20.13.23.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 13:23:26 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Wim Van Sebroeck , Guenter Roeck , Rob Herring , Geert Uytterhoeven , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Magnus Damm , Wolfram Sang Cc: linux-watchdog@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v4 2/6] watchdog: rzv2h: Obtain clock-divider and timeout values from OF match data Date: Wed, 20 Aug 2025 21:23:18 +0100 Message-ID: <20250820202322.2051969-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250820202322.2051969-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250820202322.2051969-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Update the rzv2h_wdt driver to fetch clock configuration and timeout parameters from device tree match data rather than relying on hardcoded constants. Introduce a new structure rzv2h_of_data that encapsulates minimum and maximum clock select values (cks_min and cks_max), clock divider (cks_div), timeout cycle count (timeout_cycles), and the timeout period select bits (tops). These values are provided through the OF match table and retrieved via of_device_get_match_data() during probe. This change allows dynamic configuration of the watchdog timer for different SoCs, such as the RZ/T2H, which require different settings. Signed-off-by: Lad Prabhakar Reviewed-by: Wolfram Sang Reviewed-by: Guenter Roeck --- v3->v4: - No changes. v2->v3: - Updated struct rzv2h_of_data to include tops and timeout_cycles. - Updated max_hw_heartbeat_ms calculation to use the new struct fields. - Updated commit message to clarify that the change is to obtain clock-divider and timeout values from OF match data. - Added reviewed-by from Wolfram. v1->v2: - No changes. --- drivers/watchdog/rzv2h_wdt.c | 35 ++++++++++++++++++++++++++--------- 1 file changed, 26 insertions(+), 9 deletions(-) diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c index 8defd0241213..755067800ebb 100644 --- a/drivers/watchdog/rzv2h_wdt.c +++ b/drivers/watchdog/rzv2h_wdt.c @@ -35,9 +35,6 @@ =20 #define WDTRCR_RSTIRQS BIT(7) =20 -#define MAX_TIMEOUT_CYCLES 16384 -#define CLOCK_DIV_BY_256 256 - #define WDT_DEFAULT_TIMEOUT 60U =20 static bool nowayout =3D WATCHDOG_NOWAYOUT; @@ -45,12 +42,21 @@ module_param(nowayout, bool, 0); MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (defau= lt=3D" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")"); =20 +struct rzv2h_of_data { + u8 cks_min; + u8 cks_max; + u16 cks_div; + u8 tops; + u16 timeout_cycles; +}; + struct rzv2h_wdt_priv { void __iomem *base; struct clk *pclk; struct clk *oscclk; struct reset_control *rstc; struct watchdog_device wdev; + const struct rzv2h_of_data *of_data; }; =20 static int rzv2h_wdt_ping(struct watchdog_device *wdev) @@ -84,6 +90,7 @@ static void rzv2h_wdt_setup(struct watchdog_device *wdev,= u16 wdtcr) static int rzv2h_wdt_start(struct watchdog_device *wdev) { struct rzv2h_wdt_priv *priv =3D watchdog_get_drvdata(wdev); + const struct rzv2h_of_data *of_data =3D priv->of_data; int ret; =20 ret =3D pm_runtime_resume_and_get(wdev->parent); @@ -106,8 +113,8 @@ static int rzv2h_wdt_start(struct watchdog_device *wdev) * - RPES[9:8] - Window End Position Select - 11b: 0% * - TOPS[1:0] - Timeout Period Select - 11b: 16384 cycles (3FFFh) */ - rzv2h_wdt_setup(wdev, WDTCR_CKS_CLK_256 | WDTCR_RPSS_100 | - WDTCR_RPES_0 | WDTCR_TOPS_16384); + rzv2h_wdt_setup(wdev, of_data->cks_max | WDTCR_RPSS_100 | + WDTCR_RPES_0 | of_data->tops); =20 /* * Down counting starts after writing the sequence 00h -> FFh to the @@ -184,7 +191,7 @@ static int rzv2h_wdt_restart(struct watchdog_device *wd= ev, * - RPES[9:8] - Window End Position Select - 00b: 75% * - TOPS[1:0] - Timeout Period Select - 00b: 1024 cycles (03FFh) */ - rzv2h_wdt_setup(wdev, WDTCR_CKS_CLK_1 | WDTCR_RPSS_25 | + rzv2h_wdt_setup(wdev, priv->of_data->cks_min | WDTCR_RPSS_25 | WDTCR_RPES_75 | WDTCR_TOPS_1024); =20 rzv2h_wdt_ping(wdev); @@ -213,6 +220,8 @@ static int rzv2h_wdt_probe(struct platform_device *pdev) if (!priv) return -ENOMEM; =20 + priv->of_data =3D of_device_get_match_data(dev); + priv->base =3D devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(priv->base)) return PTR_ERR(priv->base); @@ -230,8 +239,8 @@ static int rzv2h_wdt_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(priv->rstc), "failed to get cpg reset"); =20 - priv->wdev.max_hw_heartbeat_ms =3D (MILLI * MAX_TIMEOUT_CYCLES * CLOCK_DI= V_BY_256) / - clk_get_rate(priv->oscclk); + priv->wdev.max_hw_heartbeat_ms =3D (MILLI * priv->of_data->timeout_cycles= * + priv->of_data->cks_div) / clk_get_rate(priv->oscclk); dev_dbg(dev, "max hw timeout of %dms\n", priv->wdev.max_hw_heartbeat_ms); =20 ret =3D devm_pm_runtime_enable(dev); @@ -254,8 +263,16 @@ static int rzv2h_wdt_probe(struct platform_device *pde= v) return devm_watchdog_register_device(dev, &priv->wdev); } =20 +static const struct rzv2h_of_data rzv2h_wdt_of_data =3D { + .cks_min =3D WDTCR_CKS_CLK_1, + .cks_max =3D WDTCR_CKS_CLK_256, + .cks_div =3D 256, + .tops =3D WDTCR_TOPS_16384, + .timeout_cycles =3D 16384, +}; + static const struct of_device_id rzv2h_wdt_ids[] =3D { - { .compatible =3D "renesas,r9a09g057-wdt", }, + { .compatible =3D "renesas,r9a09g057-wdt", .data =3D &rzv2h_wdt_of_data }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, rzv2h_wdt_ids); --=20 2.51.0