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Wed, 20 Aug 2025 06:32:53 -0700 From: Mark Bloch To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , , Gal Pressman , Alexei Lazar , Shahar Shitrit , Dragos Tatulea , Mark Bloch , Huy Nguyen , Parav Pandit , Saeed Mahameed Subject: [PATCH V2 net 7/8] net/mlx5e: Query FW for buffer ownership Date: Wed, 20 Aug 2025 16:32:08 +0300 Message-ID: <20250820133209.389065-8-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820133209.389065-1-mbloch@nvidia.com> References: <20250820133209.389065-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE3F:EE_|PH0PR12MB8098:EE_ X-MS-Office365-Filtering-Correlation-Id: 89053f60-f518-45a9-0c01-08dddfee2139 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?1//ZNnEbbS3i47VkwVVWocuWbOfgiutSKNyt7UHyc0ucJdAXH3rkS6vF+Sg5?= =?us-ascii?Q?FtW1pesVq2c4wzjnatU3I9EDqvdURJMWMf5ciGs16n7tmwSHgmXIJHJCwocX?= =?us-ascii?Q?mtNIG78PulFNtEr7M+Im0Mbix4sMwMk9zOKKDWcZIs3TzYDvDRtNiURKrcmQ?= =?us-ascii?Q?J6RzSn/3gcAHt4d0XUWsNVix3AWagDsVNfG5gtfiuH2UP4Pdi6ZP1g9AbU0/?= =?us-ascii?Q?ZBkpqDETuYOD8T7k8iARcl6uUpHuYT+8JTgFEc/qG+PnR10mn4clHVnqU223?= =?us-ascii?Q?253T8M+OKv8SXLdfiI2e3dDqR6TZl3dOirbdppZFrib2XNXj3SjmTFgPVQHP?= =?us-ascii?Q?+OpxHf3pumfbUYWVDcQthl4Souu29MqRCUG29wukc22Tnu5FNnj23Y+BnjhT?= =?us-ascii?Q?ER040nMJzZgjaOuHS6IUyHe8d7YGvrN6/pmrM7po86y6wy9iJaP5i6I1ZLj0?= =?us-ascii?Q?RBGXyoUGydCjBNyn9FxQiFodcBm9BXGBGCfDmSyQbDF3omGOtYit07Mo8y3/?= =?us-ascii?Q?mulhIVwP+e9AOSeCDa+jNczCWO2llfuSLMVrLO2iTcxwbfUtr2JKpj/zVU8T?= =?us-ascii?Q?E7fnWgXz/gyJnMn+MohbYPaJNLG7HvrXFn5Ish2uynv+fsQ45GKzhBQ2zuDH?= =?us-ascii?Q?LSjZyDIsy4ngKodIycZm8wQJQ2lbaxSfPdLvDiXBKmCuQUOkccNH4piWjq/c?= =?us-ascii?Q?JHqVCdEZcMBzEDOa+aL3W+Ratn7a+pCuNINiAiqaq4N4IlFvGckQh4NvnN+j?= =?us-ascii?Q?JnQPoQNEQSkqKPBva4+ZAX2wAjpJA5ITnrEQxmxH8Bi3/qOnpefehhFthnE4?= =?us-ascii?Q?wNOvPslv/tAQHeHfV3xSNCLX/QG2Hw1xuyh79qYSwXYvvAGzSKF/g5qlf3+K?= =?us-ascii?Q?K162zhH09/Z3d2ZJmgfJ7BV4a9EeU3sa+p1L1bRWkHtpZqOmgE1EzHl59HBF?= =?us-ascii?Q?4kpAq+iaR/39ETE8EuWfRwKYdDzKShnMdh08vz4lRGtCC7uhbJsUmEoOmNwz?= =?us-ascii?Q?JWot5wUUxCb1VR6xBVLh8PJHewP47FzwXoxz6nAYIbuPZPzx4gvZBe3BzhsT?= =?us-ascii?Q?rVkCxJw2PQ7kSH/WTYDYfe0/J4M9foU9bmXZEUzCqawEojpPJcIon4pWQ+qM?= =?us-ascii?Q?GgArM+KQC0XUEJrr/SQuYWCGlKQlqqqM2qUQ1/w06RUkLQLzaKpoFvw7KYu1?= =?us-ascii?Q?1QsidfSAJqdCB3I94gmyc8cL0mgTZ5dNvNxfVinKh3T2FAKWhN6/kv1j15Lv?= =?us-ascii?Q?bFyY9iAnhZey7TOraLGRV6aG8MrBAvZnqtneYQTWAgNnbyl93RnQ/dx0zYly?= =?us-ascii?Q?SV68BIoz3B8tqqwOstLvCcPTlpNSQM4IbrBrd+PKZfYmm7E2o/LplX5e4aLt?= =?us-ascii?Q?+GvYStcM5yJtflNknncDnfkpvJnX+CceSo1OKYSkofFPJTJP73FJKown0sn9?= =?us-ascii?Q?+NUwn8AnQw0o8T4UF+7eyT+MP3V4xWT4dbiHgRQjJ5NZvWRAXSdjANj/kDQg?= =?us-ascii?Q?EXRAs1ZJBjVMlhzm1UPslny1l3QSNRfY6aZP?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Aug 2025 13:33:20.7727 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 89053f60-f518-45a9-0c01-08dddfee2139 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE3F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8098 Content-Type: text/plain; charset="utf-8" From: Alexei Lazar The SW currently saves local buffer ownership when setting the buffer. This means that the SW assumes it has ownership of the buffer after the command is set. If setting the buffer fails and we remain in FW ownership, the local buffer ownership state incorrectly remains as SW-owned. This leads to incorrect behavior in subsequent PFC commands, causing failures. Instead of saving local buffer ownership in SW, query the FW for buffer ownership when setting the buffer. This ensures that the buffer ownership state is accurately reflected, avoiding the issues caused by incorrect ownership states. Fixes: ecdf2dadee8e ("net/mlx5e: Receive buffer support for DCBX") Signed-off-by: Alexei Lazar Reviewed-by: Shahar Shitrit Reviewed-by: Dragos Tatulea Signed-off-by: Mark Bloch --- .../ethernet/mellanox/mlx5/core/en/dcbnl.h | 1 - .../ethernet/mellanox/mlx5/core/en_dcbnl.c | 12 ++++++++--- .../ethernet/mellanox/mlx5/core/mlx5_core.h | 2 ++ .../net/ethernet/mellanox/mlx5/core/port.c | 20 +++++++++++++++++++ 4 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en/dcbnl.h b/drivers/n= et/ethernet/mellanox/mlx5/core/en/dcbnl.h index b59aee75de94..2c98a5299df3 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en/dcbnl.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/en/dcbnl.h @@ -26,7 +26,6 @@ struct mlx5e_dcbx { u8 cap; =20 /* Buffer configuration */ - bool manual_buffer; u32 cable_len; u32 xoff; u16 port_buff_cell_sz; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c b/drivers/n= et/ethernet/mellanox/mlx5/core/en_dcbnl.c index 5fe016e477b3..d166c0d5189e 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/en_dcbnl.c @@ -362,6 +362,7 @@ static int mlx5e_dcbnl_ieee_getpfc(struct net_device *d= ev, static int mlx5e_dcbnl_ieee_setpfc(struct net_device *dev, struct ieee_pfc *pfc) { + u8 buffer_ownership =3D MLX5_BUF_OWNERSHIP_UNKNOWN; struct mlx5e_priv *priv =3D netdev_priv(dev); struct mlx5_core_dev *mdev =3D priv->mdev; u32 old_cable_len =3D priv->dcbx.cable_len; @@ -389,7 +390,14 @@ static int mlx5e_dcbnl_ieee_setpfc(struct net_device *= dev, =20 if (MLX5_BUFFER_SUPPORTED(mdev)) { pfc_new.pfc_en =3D (changed & MLX5E_PORT_BUFFER_PFC) ? pfc->pfc_en : cur= r_pfc_en; - if (priv->dcbx.manual_buffer) + ret =3D mlx5_query_port_buffer_ownership(mdev, + &buffer_ownership); + if (ret) + netdev_err(dev, + "%s, Failed to get buffer ownership: %d\n", + __func__, ret); + + if (buffer_ownership =3D=3D MLX5_BUF_OWNERSHIP_SW_OWNED) ret =3D mlx5e_port_manual_buffer_config(priv, changed, dev->mtu, &pfc_new, NULL, NULL); @@ -982,7 +990,6 @@ static int mlx5e_dcbnl_setbuffer(struct net_device *dev, if (!changed) return 0; =20 - priv->dcbx.manual_buffer =3D true; err =3D mlx5e_port_manual_buffer_config(priv, changed, dev->mtu, NULL, buffer_size, prio2buffer); return err; @@ -1252,7 +1259,6 @@ void mlx5e_dcbnl_initialize(struct mlx5e_priv *priv) priv->dcbx.cap |=3D DCB_CAP_DCBX_HOST; =20 priv->dcbx.port_buff_cell_sz =3D mlx5e_query_port_buffers_cell_size(priv); - priv->dcbx.manual_buffer =3D false; priv->dcbx.cable_len =3D MLX5E_DEFAULT_CABLE_LEN; =20 mlx5e_ets_init(priv); diff --git a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h b/drivers/= net/ethernet/mellanox/mlx5/core/mlx5_core.h index b6d53db27cd5..9d3504f5abfa 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h @@ -367,6 +367,8 @@ int mlx5_query_port_dcbx_param(struct mlx5_core_dev *md= ev, u32 *out); int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in); int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state); int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state); +int mlx5_query_port_buffer_ownership(struct mlx5_core_dev *mdev, + u8 *buffer_ownership); int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio); int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio); =20 diff --git a/drivers/net/ethernet/mellanox/mlx5/core/port.c b/drivers/net/e= thernet/mellanox/mlx5/core/port.c index 549f1066d2a5..2d7adf7444ba 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/port.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/port.c @@ -968,6 +968,26 @@ int mlx5_query_trust_state(struct mlx5_core_dev *mdev,= u8 *trust_state) return err; } =20 +int mlx5_query_port_buffer_ownership(struct mlx5_core_dev *mdev, + u8 *buffer_ownership) +{ + u32 out[MLX5_ST_SZ_DW(pfcc_reg)] =3D {}; + int err; + + if (!MLX5_CAP_PCAM_FEATURE(mdev, buffer_ownership)) { + *buffer_ownership =3D MLX5_BUF_OWNERSHIP_UNKNOWN; + return 0; + } + + err =3D mlx5_query_pfcc_reg(mdev, out, sizeof(out)); + if (err) + return err; + + *buffer_ownership =3D MLX5_GET(pfcc_reg, out, buf_ownership); + + return 0; +} + int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio) { int sz =3D MLX5_ST_SZ_BYTES(qpdpm_reg); --=20 2.34.1