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Wed, 20 Aug 2025 06:32:37 -0700 From: Mark Bloch To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" , CC: Tariq Toukan , Leon Romanovsky , "Saeed Mahameed" , , , , Gal Pressman , Carolina Jubran , Cosmin Ratiu , Mark Bloch , Mohamad Haj Yahia , Saeed Mahameed Subject: [PATCH V2 net 4/8] net/mlx5: Destroy vport QoS element when no configuration remains Date: Wed, 20 Aug 2025 16:32:05 +0300 Message-ID: <20250820133209.389065-5-mbloch@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820133209.389065-1-mbloch@nvidia.com> References: <20250820133209.389065-1-mbloch@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE38:EE_|CH1PPF946CC24FA:EE_ X-MS-Office365-Filtering-Correlation-Id: 4adc8db9-8f87-40ed-ec70-08dddfee17c7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|36860700013|376014|7416014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?tVQSSI4yhgbtQ91v17KwHE1W0o/cTQS/QV0EbKLpxWhVrfoyE/OyyLYJhZ45?= =?us-ascii?Q?RS7hSq7N15bebrOYHF49vYZULLA0g1H94KKASDexw6asO2UJ2UEYwPQiP1KB?= =?us-ascii?Q?psIPeCYwrPFNK/jK+qlZB/qwpKucqJhreVmaLPBMe0t06JuJvVz4K/pPTY8i?= =?us-ascii?Q?/I1K+q1Qn5fzIFx3vGwkf0BUlhZqrnSqIZBFe9+XiTU1X42O7vqRA5E/qDFX?= =?us-ascii?Q?Sp5CRbtKOdkaC4LL+P5d4IRaC05HzvXrTplAXr5tCg2jxlgkrD72rmx//jIM?= =?us-ascii?Q?GOkwNeqHbdWHzpy7fjP78gQf7tFXZ5rsk5UJ0j1xyv9Zaxf+x0RWNmMsgf6e?= =?us-ascii?Q?FBDTWPpMUQlklyxPieP7np6wSQ/q0GfiXDP5ULUnNVB6k5Ag9eTxgt40aOAu?= =?us-ascii?Q?K26av0fj/uT57GBKhhEyhOwQGFMmgNjxirYUC9/L+AsvQ8O8JNNl8Bpb4xSr?= =?us-ascii?Q?ExOKTkFXmAPLlSfo3incKUQukcxnGJ8XGs84QLmX118XbH7QMcPLdNMYB1St?= =?us-ascii?Q?iZaI9oOKtnehnG40euWfNci7VQj+wVdeoXXdUcvAiWWC+pBk2jzuQqhojQne?= =?us-ascii?Q?eJZTiZUsspLxXTdNM2iZq/sVQFCWZB0kvVPPZn0M1mN7UDINJLJxAdIJZJ6Q?= =?us-ascii?Q?c33dqszaKXx8MT1oxLt0X6qO3LIFmSmD3MkSk4sOeLTn1aV72tuHVBN0nUqw?= =?us-ascii?Q?ANKJWh4ALDOCqVb4PAKUNHwcfugPpGOJqwXUuOdw+hUc36mwV3Dk/rnWNkcJ?= =?us-ascii?Q?DgrTSF7RvKKDK3fB4ZXKn+rqy9+9clunDQbvbkwdzoY39IcKEa/3fN3JvhIZ?= =?us-ascii?Q?NmMOj4qFeFKOh7ZR60DPGo4uVEqqoLMmrkJ5FPlO3fLc4488xnqybirWd1bb?= =?us-ascii?Q?lXKYfichh0ObWED/8usNTxeholezzU5h9ZkTYlRFlWNzO1vyPOcmVlNLiory?= =?us-ascii?Q?FEIu/AQgWS3N0p61dIx5o1ku9CKDNiEy64oIF1xzh7X8M7D7CHxFcv7rZc1r?= =?us-ascii?Q?OlMhxOMD50yGrHId2+Jvinax2kPXOxZHrI4qjr9XTcteafdsg2vdsenbJjUg?= =?us-ascii?Q?CJBWxA9Au57c09DklmWVFQEGWN50VJo6YiGf73qTYmealtxrPpqE9NYcQByv?= =?us-ascii?Q?pQXHmjKh0DoS26K0ST5OfydbrDz3FM+DTqPZHeG2cUsq1Gh15rUMr7yRZiwn?= =?us-ascii?Q?2ce7offrG02sKRCEVYdZJdLaMQWgK+flVoEtghZ7QL12VlvT05TAgr/CHL8E?= =?us-ascii?Q?ykCmyIlGIbtmcgxWudSUZPVQxvTL3DHLkVapS3Qzz0BoDgbFz0OWpbNMkIxt?= =?us-ascii?Q?sm/QJc4o5ZVESUhT54Fe0tcJ/fO7axpSyfKvY+9ZAmsz5CIQoKZh83cMPMf9?= =?us-ascii?Q?pjG7Xyl9nvYAwChL22AR1uDhRwzsQlAkvN7XQ/FAXcajQA+TrdjqO8/7RxnF?= =?us-ascii?Q?OtdNG2wTlSmFOOm2Uqb9n9O0Xy7iBMiUy4/AKcUKxiX+QFjRK11gPHnWLlGd?= =?us-ascii?Q?4VjA2SEPNr4ItYAljmmSQ0L+8lxTM5zH1Dnd?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014)(7416014);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Aug 2025 13:33:04.8963 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4adc8db9-8f87-40ed-ec70-08dddfee17c7 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE38.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH1PPF946CC24FA Content-Type: text/plain; charset="utf-8" From: Carolina Jubran If a VF has been configured and the user later clears all QoS settings, the vport element remains in the firmware QoS tree. This leads to inconsistent behavior compared to VFs that were never configured, since the FW assumes that unconfigured VFs are outside the QoS hierarchy. As a result, the bandwidth share across VFs may differ, even though none of them appear to have any configuration. Align the driver behavior with the FW expectation by destroying the vport QoS element when all configurations are removed. Fixes: c9497c98901c ("net/mlx5: Add support for setting VF min rate") Fixes: cf7e73770d1b ("net/mlx5: Manage TC arbiter nodes and implement full = support for tc-bw") Signed-off-by: Carolina Jubran Reviewed-by: Cosmin Ratiu Signed-off-by: Mark Bloch Reviewed-by: Przemek Kitszel --- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 57 ++++++++++++++++--- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/ne= t/ethernet/mellanox/mlx5/core/esw/qos.c index 4ed5968f1638..452a948a3e6d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -1127,6 +1127,19 @@ static int mlx5_esw_qos_vport_enable(struct mlx5_vpo= rt *vport, enum sched_node_t return err; } =20 +static void mlx5_esw_qos_vport_disable_locked(struct mlx5_vport *vport) +{ + struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; + + esw_assert_qos_lock_held(esw); + if (!vport->qos.sched_node) + return; + + esw_qos_vport_disable(vport, NULL); + mlx5_esw_qos_vport_qos_free(vport); + esw_qos_put(esw); +} + void mlx5_esw_qos_vport_disable(struct mlx5_vport *vport) { struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; @@ -1140,9 +1153,7 @@ void mlx5_esw_qos_vport_disable(struct mlx5_vport *vp= ort) parent =3D vport->qos.sched_node->parent; WARN(parent, "Disabling QoS on port before detaching it from node"); =20 - esw_qos_vport_disable(vport, NULL); - mlx5_esw_qos_vport_qos_free(vport); - esw_qos_put(esw); + mlx5_esw_qos_vport_disable_locked(vport); unlock: esw_qos_unlock(esw); } @@ -1642,6 +1653,21 @@ static bool esw_qos_tc_bw_disabled(u32 *tc_bw) return true; } =20 +static void esw_vport_qos_prune_empty(struct mlx5_vport *vport) +{ + struct mlx5_esw_sched_node *vport_node =3D vport->qos.sched_node; + + esw_assert_qos_lock_held(vport->dev->priv.eswitch); + if (!vport_node) + return; + + if (vport_node->parent || vport_node->max_rate || + vport_node->min_rate || !esw_qos_tc_bw_disabled(vport_node->tc_bw)) + return; + + mlx5_esw_qos_vport_disable_locked(vport); +} + int mlx5_esw_qos_init(struct mlx5_eswitch *esw) { if (esw->qos.domain) @@ -1675,6 +1701,10 @@ int mlx5_esw_devlink_rate_leaf_tx_share_set(struct d= evlink_rate *rate_leaf, void =20 esw_qos_lock(esw); err =3D mlx5_esw_qos_set_vport_min_rate(vport, tx_share, extack); + if (err) + goto out; + esw_vport_qos_prune_empty(vport); +out: esw_qos_unlock(esw); return err; } @@ -1696,6 +1726,10 @@ int mlx5_esw_devlink_rate_leaf_tx_max_set(struct dev= link_rate *rate_leaf, void * =20 esw_qos_lock(esw); err =3D mlx5_esw_qos_set_vport_max_rate(vport, tx_max, extack); + if (err) + goto out; + esw_vport_qos_prune_empty(vport); +out: esw_qos_unlock(esw); return err; } @@ -1733,6 +1767,7 @@ int mlx5_esw_devlink_rate_leaf_tc_bw_set(struct devli= nk_rate *rate_leaf, if (vport_node->type =3D=3D SCHED_NODE_TYPE_TC_ARBITER_TSAR) err =3D esw_qos_vport_update(vport, SCHED_NODE_TYPE_VPORT, vport_node->parent, extack); + esw_vport_qos_prune_empty(vport); goto unlock; } =20 @@ -1893,14 +1928,20 @@ int mlx5_esw_devlink_rate_leaf_parent_set(struct de= vlink_rate *devlink_rate, void *priv, void *parent_priv, struct netlink_ext_ack *extack) { - struct mlx5_esw_sched_node *node; + struct mlx5_esw_sched_node *node =3D parent ? parent_priv : NULL; struct mlx5_vport *vport =3D priv; + int err; =20 - if (!parent) - return mlx5_esw_qos_vport_update_parent(vport, NULL, extack); + err =3D mlx5_esw_qos_vport_update_parent(vport, node, extack); + if (!err) { + struct mlx5_eswitch *esw =3D vport->dev->priv.eswitch; + + esw_qos_lock(esw); + esw_vport_qos_prune_empty(vport); + esw_qos_unlock(esw); + } =20 - node =3D parent_priv; - return mlx5_esw_qos_vport_update_parent(vport, node, extack); + return err; } =20 static bool esw_qos_is_node_empty(struct mlx5_esw_sched_node *node) --=20 2.34.1