From nobody Sat Oct 4 06:37:12 2025 Received: from mail.grinn-global.com (mail.grinn-global.com [77.55.128.204]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1662A283144; Wed, 20 Aug 2025 12:10:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=77.55.128.204 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755691842; cv=none; b=puWhyzL+0Yi6pVz584rWUGB5Le7Fgau3NZZSWOWkfGuUDxMXJUJ2Rk+2bwqRZ44nRjsgKob+mEtdW7QU09GB7XAFsrfmoC77TuJUwatnu7uxN5aASMVLExHcfecCAjMFTL0fGqUnDlknlV9QtXA+bdCVEmODGzJa6bpOMEd7ccc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755691842; c=relaxed/simple; bh=Mb4ejxp/K2dVX4J7W4L3dRwSUv0Wf+t+j9bvWBoBMu4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lEjeqKyQsWy3GSbYUfQVx1ZqIi3U6955tkdO1eNxodeWowhfohBlzZDk8NPyg2m2Myko6WpCf1PdVas/W3Cyxaqn3D9HfsbgJ0KPSWmFV2k/CfBoO1kLo2Rd56EaDnLPK5VArhdEz/gOrvkafQUqoSbLeVYAEOOJQ/jkNAGa40U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=grinn-global.com; spf=pass smtp.mailfrom=grinn-global.com; arc=none smtp.client-ip=77.55.128.204 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=grinn-global.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=grinn-global.com X-Virus-Scanned: by amavisd-new using ClamAV (16) X-Spam-Flag: NO X-Spam-Score: -1 X-Spam-Level: Received: from mateusz.int.grinn-global.com (f90-187.icpnet.pl [46.228.90.187]) by server220076.nazwa.pl (Postfix) with ESMTP id B7E8D1BDE28; Wed, 20 Aug 2025 14:10:33 +0200 (CEST) From: Mateusz Koza To: angelogioacchino.delregno@collabora.com, robh@kernel.org Cc: krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, marcin.czarnecki@grinn-global.com, b.bilas@grinn-global.com, mateusz.koza@grinn-global.com, andrew@lunn.ch Subject: [PATCH v3 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 Date: Wed, 20 Aug 2025 14:09:02 +0200 Message-ID: <20250820120905.993189-2-mateusz.koza@grinn-global.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250820120905.993189-1-mateusz.koza@grinn-global.com> References: <20250820120905.993189-1-mateusz.koza@grinn-global.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-NA-AI-Spam-Probability: 0.61 X-NA-AI-Is-Spam: no Content-Type: text/plain; charset="utf-8" Add support for Grinn GenioSBC-700. The Grinn GenioSBC-700 is a single-board computer based on the MediaTek Genio 700 SoC. Its device tree is split into separate SoM (.dtsi) and SBC (.dtsi) files, which are combined in the SoC-specific .dts file. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Signed-off-by: Mateusz Koza Reviewed-by: Andrew Lunn --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8390-grinn-genio-700-sbc.dts | 19 + .../dts/mediatek/mt8390-grinn-genio-sbc.dtsi | 674 ++++++++++++++++++ .../dts/mediatek/mt8390-grinn-genio-som.dtsi | 209 ++++++ 4 files changed, 903 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc= .dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/me= diatek/Makefile index 1dcea8b9aed9..7383d75d8041 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -104,6 +104,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8365-evk-hdmi.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-genio-700-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8390-grinn-genio-700-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) +=3D mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts b/= arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts new file mode 100644 index 000000000000..a37507a5a5d0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ +/dts-v1/; + +#include "mt8188.dtsi" +#include "mt8390-grinn-genio-som.dtsi" +#include "mt8390-grinn-genio-sbc.dtsi" + +/ { + model =3D "Grinn GenioSBC-700"; + compatible =3D "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188= "; + memory@40000000 { + device_type =3D "memory"; + reg =3D <0 0x40000000 1 0x00000000>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi b/arc= h/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi new file mode 100644 index 000000000000..22765b9a6d20 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +#include + +/ { + chassis-type =3D "embedded"; + aliases { + ethernet0 =3D ð + i2c0 =3D &i2c0; + i2c2 =3D &i2c2; + i2c3 =3D &i2c3; + i2c5 =3D &i2c5; + i2c6 =3D &i2c6; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:921600n8"; + }; + + firmware { + optee { + compatible =3D "linaro,optee-tz"; + method =3D "smc"; + }; + }; + + reserved-memory { + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg =3D <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg =3D <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible =3D "shared-dma-pool"; + reg =3D <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + connector { + compatible =3D "hdmi-connector"; + label =3D "hdmi"; + type =3D "a"; + ddc-i2c-bus =3D <&hdmi_ddc>; + hdmi-pwr-supply =3D <&hdmi_phy>; + + port { + hdmi_connector_in: endpoint { + remote-endpoint =3D <&hdmi0_out>; + }; + }; + }; + + reg_sbc_vsys: regulator-vsys { + compatible =3D "regulator-fixed"; + regulator-name =3D "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + reg_fixed_5v: regulator-0 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed_5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + enable-active-high; + regulator-always-on; + vin-supply =3D <®_sbc_vsys>; + }; + + reg_fixed_4v2: regulator-1 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed_4v2"; + regulator-min-microvolt =3D <4200000>; + regulator-max-microvolt =3D <4200000>; + enable-active-high; + regulator-always-on; + vin-supply =3D <®_sbc_vsys>; + }; + + reg_fixed_3v3: regulator-2 { + compatible =3D "regulator-fixed"; + regulator-name =3D "fixed_3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + enable-active-high; + regulator-always-on; + vin-supply =3D <®_sbc_vsys>; + }; +}; + +&pio { + gpio-line-names =3D + /* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4", + /* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9", + /* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "", + /* 15 - 19 */ "", "", "", "", "", + /* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "", + /* 25 - 29 */ "", "", "", "", "", + /* 30 - 34 */ "RPI_GPIO30", "", "", "", "", + /* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "", + /* 40 - 44 */ "", "", "", "", "", + /* 45 - 49 */ "", "", "", "", "", + /* 50 - 54 */ "", "", "", "", "", + /* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59", + /* 60 - 64 */ "RPI_GPIO60", "", "", "", "", + /* 65 - 69 */ "", "", "", "", "RPI_GPIO69", + /* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74", + /* 75 - 79 */ "", "", "", "", "RPI_GPIO79", + /* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "", + /* 85 - 89 */ "", "", "", "", "", + /* 90 - 94 */ "", "", "", "", "", + /* 95 - 99 */ "", "", "", "", "", + /*100 - 104 */ "", "", "", "", "", + /*105 - 109 */ "", "", "", "", "", + /*110 - 114 */ "", "", "", "", "", + /*115 - 119 */ "", "", "", "", "", + /*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPI= O124"; + + i2c0_pins: i2c0-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux =3D , + ; + bias-pull-up; + }; + }; + + pcie_pins_default: pcie-default { + mux { + pinmux =3D , + , + ; + bias-pull-up; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + + pins-mdio { + pinmux =3D , + ; + drive-strength =3D <8>; + input-enable; + }; + + pins-power { + pinmux =3D , + ; + output-high; + }; + + pins-rxd { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + + pins-txd { + pinmux =3D , + , + , + ; + drive-strength =3D <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux =3D , + , + , + ; + }; + + pins-mdio { + pinmux =3D , + ; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux =3D , + , + , + ; + }; + + pins-txd { + pinmux =3D , + , + , + ; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux =3D , + , + , + ; + bias-disable; + }; + }; + + hdmi_vreg_pins: hdmi-vreg-pins { + pins-pwr { + pinmux =3D ; + bias-disable; + }; + }; + + hdmi_pins: hdmi-pins { + pins-hotplug { + pinmux =3D ; + bias-pull-down; + }; + + pins-cec { + pinmux =3D ; + bias-disable; + }; + + pins-ddc { + pinmux =3D , + ; + drive-strength =3D <10>; + }; + }; + + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux =3D , + , + , + ; + }; + }; +}; + +ð { + phy-mode =3D "rgmii-id"; + phy-handle =3D <ðernet_phy0>; + snps,reset-active-low; + snps,reset-delays-us =3D <0 11000 200000>; + mediatek,tx-delay-ps =3D <30>; + pinctrl-names =3D "default", "sleep"; + pinctrl-0 =3D <ð_default_pins>; + pinctrl-1 =3D <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio =3D <&pio 147 GPIO_ACTIVE_LOW>; + status =3D "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@3 { + reg =3D <3>; + compatible =3D "ethernet-phy-ieee802.3-c22"; + eee-broken-1000t; + interrupts-extended =3D <&pio 148 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c0_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c2 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c2_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c3 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c3_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c5 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c5_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&i2c6 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c6_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&uart0 { + pinctrl-0 =3D <&uart0_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart1 { + pinctrl-0 =3D <&uart1_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&uart2 { + pinctrl-0 =3D <&uart2_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + +&pcie { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&pcie_pins_default>; + status =3D "okay"; +}; + +&pciephy { + status =3D "okay"; +}; + +&spi2 { + pinctrl-0 =3D <&spi2_pins>; + pinctrl-names =3D "default"; + mediatek,pad-select =3D <0>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; +}; + +&vdosys1 { + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + vdosys1_ep_ext: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <ðdr0_in>; + }; + }; +}; + +ðdr0 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + ethdr0_in: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&vdosys1_ep_ext>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + ethdr0_out: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&merge5_in>; + }; + }; + }; +}; + +&merge5 { + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <0>; + + merge5_in: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <ðdr0_out>; + }; + }; + + port@1 { + #address-cells =3D <1>; + #size-cells =3D <0>; + reg =3D <1>; + + merge5_out: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&dpi1_in>; + }; + }; + }; +}; + +&dpi1 { + status =3D "okay"; +}; + +&dpi1_in { + remote-endpoint =3D <&merge5_out>; +}; + +&dpi1_out { + remote-endpoint =3D <&hdmi0_in>; +}; + +&hdmi { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_pins>; + status =3D "okay"; +}; + +&hdmi0_in { + remote-endpoint =3D <&dpi1_out>; +}; + +&hdmi0_out { + remote-endpoint =3D <&hdmi_connector_in>; +}; + +&hdmi_phy { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&hdmi_vreg_pins>; + status =3D "okay"; +}; + +&u3phy0 { + status =3D "okay"; +}; + +&u3phy1 { + status =3D "okay"; +}; + +&u3phy2 { + status =3D "okay"; +}; + +&xhci1 { + status =3D "okay"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hub_2_0: hub@1 { + compatible =3D "usb451,8027"; + reg =3D <1>; + peer-hub =3D <&hub_3_0>; + reset-gpios =3D <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply =3D <®_fixed_3v3>; + }; + + hub_3_0: hub@2 { + compatible =3D "usb451,8025"; + reg =3D <2>; + peer-hub =3D <&hub_2_0>; + reset-gpios =3D <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply =3D <®_fixed_3v3>; + }; +}; + +&xhci2 { + status =3D "okay"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + hub@1 { + compatible =3D "microchip,usb2513bi"; + reg =3D <1>; + vdd-supply =3D <®_fixed_3v3>; + }; +}; + +&ssusb0 { + status =3D "okay"; + dr_mode =3D "peripheral"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; +}; + +&ssusb1 { + status =3D "okay"; + dr_mode =3D "host"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + maximum-speed =3D "super-speed"; +}; + +&ssusb2 { + status =3D "okay"; + dr_mode =3D "host"; + vusb33-supply =3D <&mt6359_vusb_ldo_reg>; + maximum-speed =3D "high-speed"; +}; + +&scp_c0 { + firmware-name =3D "mediatek/mt8188/scp.img"; + memory-region =3D <&scp_mem>; + status =3D "okay"; +}; + +&gpu { + mali-supply =3D <&mt6359_vproc2_buck_reg>; + status =3D "okay"; +}; + +&adsp { + memory-region =3D <&adsp_dma_mem>, <&adsp_mem>; + status =3D "okay"; +}; + +&afe { + memory-region =3D <&afe_dma_mem>; + status =3D "okay"; +}; + +&sound { + compatible =3D "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; + model =3D "mt8390-evk"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&audio_default_pins>; + audio-routing =3D + "Headphone", "Headphone L", + "Headphone", "Headphone R", + "AP DMIC", "AUDGLB", + "AP DMIC", "MIC_BIAS_0", + "AP DMIC", "MIC_BIAS_2", + "DMIC_INPUT", "AP DMIC"; + + mediatek,adsp =3D <&adsp>; + status =3D "okay"; + + dai-link-0 { + link-name =3D "ETDM3_OUT_BE"; + + codec { + sound-dai =3D <&hdmi 0>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi b/arc= h/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi new file mode 100644 index 000000000000..d88481beff9d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza + */ + +#include "mt6359.dtsi" +#include + +/ { + aliases { + i2c1 =3D &i2c1; + mmc0 =3D &mmc0; + }; +}; + +&i2c1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&i2c1_pins>; + clock-frequency =3D <400000>; + status =3D "okay"; +}; + +&mfg0 { + domain-supply =3D <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply =3D <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + status =3D "okay"; + pinctrl-names =3D "default", "state_uhs"; + pinctrl-0 =3D <&mmc0_default_pins>; + pinctrl-1 =3D <&mmc0_uhs_pins>; + bus-width =3D <8>; + max-frequency =3D <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay =3D <0x1481b>; + vmmc-supply =3D <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply =3D <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name =3D "vcn18_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name =3D "vcn33_2_pmu"; + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name =3D "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name =3D "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name =3D "vpa_pmu"; + regulator-max-microvolt =3D <3100000>; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name =3D "vgpu"; + regulator-min-microvolt =3D <550000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + +&mt6359_vpu_buck_reg { + regulator-name =3D "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name =3D "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name =3D "vsim1_pmu"; + regulator-enable-ramp-delay =3D <480>; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name =3D "vsram_gpu"; + regulator-min-microvolt =3D <750000>; + regulator-max-microvolt =3D <800000>; + regulator-coupled-with =3D <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread =3D <6250>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name =3D "vufs18_pmu"; + regulator-always-on; +}; + +&pio { + + i2c1_pins: i2c1-pins { + pins { + pinmux =3D , + ; + bias-pull-up =3D ; + drive-strength-microamp =3D <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <6>; + bias-pull-up =3D ; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-cmd-dat { + pinmux =3D , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + + pins-ds { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-down =3D ; + }; + + pins-rst { + pinmux =3D ; + drive-strength =3D <8>; + bias-pull-up =3D ; + }; + }; +}; + +&pmic { + interrupt-parent =3D <&pio>; + interrupts =3D <222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible =3D "mediatek,mt6359-keys"; + mediatek,long-press-mode =3D <1>; + power-off-time-sec =3D <0>; + + power-key { + linux,keycodes =3D ; + wakeup-source; + }; + }; +}; --=20 2.43.0