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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afded4ca695sm161769566b.90.2025.08.20.04.42.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 04:42:59 -0700 (PDT) From: Svyatoslav Ryhel To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Svyatoslav Ryhel , "Jiri Slaby (SUSE)" , Jonathan Cameron , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= Cc: linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/6] thermal: tegra: soctherm-fuse: prepare calibration for Tegra114 support Date: Wed, 20 Aug 2025 14:42:28 +0300 Message-ID: <20250820114231.150441-4-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250820114231.150441-1-clamor95@gmail.com> References: <20250820114231.150441-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Tegra114 has a different fuse calibration register layout and address compared to other Tegra SoCs, requiring SOCTHERM shift, mask, register address, and nominal calibration values to be configurable. Additionally, a use_lower_precision option was implemented to account for the Tegra114's 0.5C thermal data output, which differs from the 1C precision of newer SoCs. Signed-off-by: Svyatoslav Ryhel --- drivers/thermal/tegra/soctherm-fuse.c | 31 ++++++++++++++++------- drivers/thermal/tegra/soctherm.h | 8 +++++- drivers/thermal/tegra/tegra124-soctherm.c | 6 +++++ drivers/thermal/tegra/tegra132-soctherm.c | 6 +++++ drivers/thermal/tegra/tegra210-soctherm.c | 6 +++++ 5 files changed, 47 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/tegra/soctherm-fuse.c b/drivers/thermal/tegra/= soctherm-fuse.c index 190f95280e0b..d27876dd9b2a 100644 --- a/drivers/thermal/tegra/soctherm-fuse.c +++ b/drivers/thermal/tegra/soctherm-fuse.c @@ -9,15 +9,10 @@ =20 #include "soctherm.h" =20 -#define NOMINAL_CALIB_FT 105 -#define NOMINAL_CALIB_CP 25 - #define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK 0x1fff #define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK (0x1fff << 13) #define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT 13 =20 -#define FUSE_TSENSOR_COMMON 0x180 - /* * Tegra210: Layout of bits in FUSE_TSENSOR_COMMON: * 3 2 1 0 @@ -26,7 +21,7 @@ * | BASE_FT | BASE_CP | SHFT_FT | SHIFT_CP | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * - * Tegra12x, etc: + * Tegra124: * In chips prior to Tegra210, this fuse was incorrectly sized as 26 bits, * and didn't hold SHIFT_CP in [31:26]. Therefore these missing six bits * were obtained via the FUSE_SPARE_REALIGNMENT_REG register [5:0]. @@ -44,6 +39,13 @@ * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ * |---------------------------------------------------| SHIFT_CP | * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * + * Tegra114: Layout of bits in FUSE_TSENSOR_COMMON aka FUSE_VSENSOR_CALIB: + * 3 2 1 0 + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ + * | SHFT_FT | BASE_FT | SHIFT_CP | BASE_CP | + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+ */ =20 #define CALIB_COEFFICIENT 1000000LL @@ -77,7 +79,7 @@ int tegra_calc_shared_calib(const struct tegra_soctherm_f= use *tfuse, s32 shifted_cp, shifted_ft; int err; =20 - err =3D tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val); + err =3D tegra_fuse_readl(tfuse->fuse_common_reg, &val); if (err) return err; =20 @@ -96,10 +98,21 @@ int tegra_calc_shared_calib(const struct tegra_soctherm= _fuse *tfuse, return err; } =20 + shifted_cp =3D (val & tfuse->fuse_shift_cp_mask) >> + tfuse->fuse_shift_cp_shift; shifted_cp =3D sign_extend32(val, 5); =20 - shared->actual_temp_cp =3D 2 * NOMINAL_CALIB_CP + shifted_cp; - shared->actual_temp_ft =3D 2 * NOMINAL_CALIB_FT + shifted_ft; + shared->actual_temp_cp =3D 2 * tfuse->nominal_calib_cp + shifted_cp; + shared->actual_temp_ft =3D 2 * tfuse->nominal_calib_ft + shifted_ft; + + /* + * Tegra114 provides fuse thermal corrections in 0.5C while newer + * SoCs provide data in 1C + */ + if (tfuse->use_lower_precision) { + shared->actual_temp_cp /=3D 2; + shared->actual_temp_ft /=3D 2; + } =20 return 0; } diff --git a/drivers/thermal/tegra/soctherm.h b/drivers/thermal/tegra/socth= erm.h index 70501e73d586..f8d76ae716fe 100644 --- a/drivers/thermal/tegra/soctherm.h +++ b/drivers/thermal/tegra/soctherm.h @@ -56,6 +56,9 @@ #define SENSOR_TEMP2_MEM_TEMP_MASK (0xffff << 16) #define SENSOR_TEMP2_PLLX_TEMP_MASK 0xffff =20 +#define FUSE_VSENSOR_CALIB 0x08c +#define FUSE_TSENSOR_COMMON 0x180 + /** * struct tegra_tsensor_group - SOC_THERM sensor group data * @name: short name of the temperature sensor group @@ -109,9 +112,12 @@ struct tsensor_group_thermtrips { =20 struct tegra_soctherm_fuse { u32 fuse_base_cp_mask, fuse_base_cp_shift; + u32 fuse_shift_cp_mask, fuse_shift_cp_shift; u32 fuse_base_ft_mask, fuse_base_ft_shift; u32 fuse_shift_ft_mask, fuse_shift_ft_shift; - u32 fuse_spare_realignment; + u32 fuse_common_reg, fuse_spare_realignment; + u32 nominal_calib_cp, nominal_calib_ft; + bool use_lower_precision; }; =20 struct tsensor_shared_calib { diff --git a/drivers/thermal/tegra/tegra124-soctherm.c b/drivers/thermal/te= gra/tegra124-soctherm.c index 20ad27f4d1a1..e0a40ca2a6ac 100644 --- a/drivers/thermal/tegra/tegra124-soctherm.c +++ b/drivers/thermal/tegra/tegra124-soctherm.c @@ -200,11 +200,17 @@ static const struct tegra_tsensor tegra124_tsensors[]= =3D { static const struct tegra_soctherm_fuse tegra124_soctherm_fuse =3D { .fuse_base_cp_mask =3D 0x3ff, .fuse_base_cp_shift =3D 0, + .fuse_shift_cp_mask =3D 0x1f, + .fuse_shift_cp_shift =3D 0, .fuse_base_ft_mask =3D 0x7ff << 10, .fuse_base_ft_shift =3D 10, .fuse_shift_ft_mask =3D 0x1f << 21, .fuse_shift_ft_shift =3D 21, + .fuse_common_reg =3D FUSE_TSENSOR_COMMON, .fuse_spare_realignment =3D 0x1fc, + .nominal_calib_cp =3D 25, + .nominal_calib_ft =3D 105, + .use_lower_precision =3D false, }; =20 const struct tegra_soctherm_soc tegra124_soctherm =3D { diff --git a/drivers/thermal/tegra/tegra132-soctherm.c b/drivers/thermal/te= gra/tegra132-soctherm.c index b76308fdad9e..138d76c67114 100644 --- a/drivers/thermal/tegra/tegra132-soctherm.c +++ b/drivers/thermal/tegra/tegra132-soctherm.c @@ -200,11 +200,17 @@ static struct tegra_tsensor tegra132_tsensors[] =3D { static const struct tegra_soctherm_fuse tegra132_soctherm_fuse =3D { .fuse_base_cp_mask =3D 0x3ff, .fuse_base_cp_shift =3D 0, + .fuse_shift_cp_mask =3D 0x1f, + .fuse_shift_cp_shift =3D 0, .fuse_base_ft_mask =3D 0x7ff << 10, .fuse_base_ft_shift =3D 10, .fuse_shift_ft_mask =3D 0x1f << 21, .fuse_shift_ft_shift =3D 21, + .fuse_common_reg =3D FUSE_TSENSOR_COMMON, .fuse_spare_realignment =3D 0x1fc, + .nominal_calib_cp =3D 25, + .nominal_calib_ft =3D 105, + .use_lower_precision =3D false, }; =20 const struct tegra_soctherm_soc tegra132_soctherm =3D { diff --git a/drivers/thermal/tegra/tegra210-soctherm.c b/drivers/thermal/te= gra/tegra210-soctherm.c index d0ff793f18c5..1127b4d28087 100644 --- a/drivers/thermal/tegra/tegra210-soctherm.c +++ b/drivers/thermal/tegra/tegra210-soctherm.c @@ -201,11 +201,17 @@ static const struct tegra_tsensor tegra210_tsensors[]= =3D { static const struct tegra_soctherm_fuse tegra210_soctherm_fuse =3D { .fuse_base_cp_mask =3D 0x3ff << 11, .fuse_base_cp_shift =3D 11, + .fuse_shift_cp_mask =3D 0x1f, + .fuse_shift_cp_shift =3D 0, .fuse_base_ft_mask =3D 0x7ff << 21, .fuse_base_ft_shift =3D 21, .fuse_shift_ft_mask =3D 0x1f << 6, .fuse_shift_ft_shift =3D 6, + .fuse_common_reg =3D FUSE_TSENSOR_COMMON, .fuse_spare_realignment =3D 0, + .nominal_calib_cp =3D 25, + .nominal_calib_ft =3D 105, + .use_lower_precision =3D false, }; =20 static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] =3D { --=20 2.48.1