From nobody Sat Oct 4 05:03:17 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 225162737F6; Wed, 20 Aug 2025 08:34:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755678856; cv=none; b=oEnsj/R3RQ9iGjj0H+rcvZybqQV2PJXTdcYoP7FO+REMPCimXQXzsjO5SNUJeuKJKHUk4KbbstqAtnulWGjJfNPplZhn0elatpTCKiGUqfnPQCq3EqNWU64jjeLLgTK7HSS2zddML521t8zYpHGpw97b4b/Jy6TIrUcp7zr7Xjs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755678856; c=relaxed/simple; bh=of8447HiVJqRdz4rv0HNn1rtX19Kf8ihqdRTHGviwlw=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lXJL4rorQNQMeNlFNGc6mKEJJU/Ich+n6K7uTwij0XYg8b8HPDZ4aRIZ+Fztr/LLjkw4Wmh1Gh/6BNW7xThjR87smC95DHz3J90AQUojbVfg1aigZd9eK+i9LRggiYm7OFKSu1dTQHIa9cr3cup9bStKlAPCwByB0W99EF3KNak= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=mHqr3Kz4; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="mHqr3Kz4" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57K8Y8H7207845; Wed, 20 Aug 2025 03:34:08 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755678848; bh=vUBXrqvedfpHBtOjp4aTmMMFWcJbSWrEMa3VFNLD1mY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mHqr3Kz4/YqUjVRw5hJfQwR3HgK2s8pnnU7wXfk5pM/PgUW+WGcXl0OUU4bH64dP9 zXKOVKdTzGYnoFkbnjREX7Z3vFbJRMSgJx1ODtoMCHY+jwhfWydW1ao+jsP0JuLJar kUhcAxNaWhyvsmlncMds5pNPU585pssFl3oZgqOA= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57K8Y87q1661123 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 20 Aug 2025 03:34:08 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 20 Aug 2025 03:34:07 -0500 Received: from lelvem-mr06.itg.ti.com (10.180.75.8) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 20 Aug 2025 03:34:07 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.233.249]) by lelvem-mr06.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57K8Y6dJ4133686; Wed, 20 Aug 2025 03:34:07 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH 1/4] arm64: dts: ti: k3-am62a-main: Fix pinctrl properties Date: Wed, 20 Aug 2025 14:03:28 +0530 Message-ID: <20250820083331.3412378-2-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820083331.3412378-1-p-bhagat@ti.com> References: <20250820083331.3412378-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" From: Vibhore Vardhan Correct reg length to match end address - start address for main PADCFG registers. Signed-off-by: Vibhore Vardhan Signed-off-by: Paresh Bhagat --- arch/arm64/boot/dts/ti/k3-am62a-main.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi b/arch/arm64/boot/dt= s/ti/k3-am62a-main.dtsi index 9cad79d7bbc1..260279702c01 100644 --- a/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62a-main.dtsi @@ -267,7 +267,7 @@ secure_proxy_sa3: mailbox@43600000 { =20 main_pmx0: pinctrl@f4000 { compatible =3D "pinctrl-single"; - reg =3D <0x00 0xf4000 0x00 0x2ac>; + reg =3D <0x00 0xf4000 0x00 0x25c>; #pinctrl-cells =3D <1>; pinctrl-single,register-width =3D <32>; pinctrl-single,function-mask =3D <0xffffffff>; --=20 2.34.1 From nobody Sat Oct 4 05:03:17 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A72F272803; Wed, 20 Aug 2025 08:34:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755678861; cv=none; b=HdxO1A1Yze1y/d1dtFPcVRgQ5KMoeUR5o2P1Ql5yga8h/LEJ4K5Vk3xHZIruqreHSm91ospdi3a7Tu8gCOoxojNJJ8rBqpeKqz+FSSHChQvvFSYoVSa4SWxShKn+ndWWam6iHiN0Xj4ScJcVYy3Q7ykRs0BgUn+XZ2szg738O18= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755678861; c=relaxed/simple; bh=IQRVkcCITSm3szIByAT9qLys24vtINUmw91Mle4w8K0=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Py86f5dUhjGHRaLD+T/XJ1YdqT/HTAz5AWaLfCRj1Gjm+wbqX1NMRALqtTexW74/I4cmqtwZY1Si33ddVjYHg8Ybc3O+xNQfvF2iLjHdx01t9wZ1NnCvcOY4kzxWQoHtQnY+yy0h/ETMFiQxVkKjQZfZq8xMHGfc14KbmMuTspQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=x8jhm7mD; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="x8jhm7mD" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57K8YC90210348; Wed, 20 Aug 2025 03:34:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755678852; bh=weQAueA4hmHDZvKZ3RiNTiHK/0dkmQeiIX+hZC1f8hY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=x8jhm7mDmimU1mlTp2Nk/m8SdzpGf+9VjE6zf+vjM+FSNzTONMA1yIuPchUrcERbo xAruAkqfB5anHtK2512UsZDW1L82XPXxsMV8iRQQjXEwiOwsjhAWEMD7fGJivsyaMx fNcZeIwmEPv7BB3RCrkY8XbB0EJjRSBKJVxbJnHM= Received: from DFLE108.ent.ti.com (dfle108.ent.ti.com [10.64.6.29]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57K8YC2P1223587 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 20 Aug 2025 03:34:12 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 20 Aug 2025 03:34:11 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 20 Aug 2025 03:34:11 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.233.249]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57K8YABb228442; Wed, 20 Aug 2025 03:34:11 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH 2/4] arm64: dts: ti: k3-am62d2-evm: Enable USB support Date: Wed, 20 Aug 2025 14:03:29 +0530 Message-ID: <20250820083331.3412378-3-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820083331.3412378-1-p-bhagat@ti.com> References: <20250820083331.3412378-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add pinmux configuration for USB1 interface and enable the node for functionality. Also enable data transfer on USB0, on existing power delivery configuration. Signed-off-by: Paresh Bhagat Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am62d2-evm.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts b/arch/arm64/boot/dts= /ti/k3-am62d2-evm.dts index daea18b0bc61..9704c2d97f43 100644 --- a/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-am62d2-evm.dts @@ -367,6 +367,12 @@ usr_led_pins_default: usr-led-default-pins { AM62DX_IOPAD(0x0244, PIN_INPUT, 7) /* (D18) MMC1_SDWP.GPIO1_49 */ >; }; + + main_usb1_pins_default: main-usb1-default-pins { + pinctrl-single,pins =3D < + AM62DX_IOPAD(0x0258, PIN_OUTPUT, 0) /* (D19) USB1_DRVVBUS */ + >; + }; }; =20 &mcu_gpio0 { @@ -499,6 +505,11 @@ &main_uart0 { status =3D "okay"; }; =20 +&usbss0 { + status =3D "okay"; + ti,vbus-divider; +}; + &usb0 { usb-role-switch; =20 @@ -509,6 +520,16 @@ usb0_hs_ep: endpoint { }; }; =20 +&usbss1 { + status =3D "okay"; +}; + +&usb1 { + dr_mode =3D "host"; + pinctrl-names =3D "default"; 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Wed, 20 Aug 2025 03:34:20 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH 3/4] cpufreq: dt-platdev: Blacklist ti,am62d2 SoC Date: Wed, 20 Aug 2025 14:03:30 +0530 Message-ID: <20250820083331.3412378-4-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820083331.3412378-1-p-bhagat@ti.com> References: <20250820083331.3412378-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add ti,am62d2 SoC to the blacklist as the ti-cpufreq driver will handle creating the cpufreq-dt platform device after it completes and ensure it is not created twice. Signed-off-by: Paresh Bhagat --- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq= -dt-platdev.c index 1a9d9d008002..cd1816a12bb9 100644 --- a/drivers/cpufreq/cpufreq-dt-platdev.c +++ b/drivers/cpufreq/cpufreq-dt-platdev.c @@ -189,6 +189,7 @@ static const struct of_device_id blocklist[] __initcons= t =3D { { .compatible =3D "ti,omap3", }, { .compatible =3D "ti,am625", }, { .compatible =3D "ti,am62a7", }, + { .compatible =3D "ti,am62d2", }, { .compatible =3D "ti,am62p5", }, =20 { .compatible =3D "qcom,ipq5332", }, --=20 2.34.1 From nobody Sat Oct 4 05:03:17 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EE5D02DA769; Wed, 20 Aug 2025 08:34:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755678872; cv=none; b=qpBxsgP6PsK2TJFhCyV3GxnZcgYSFQFOSi6/fKc8e3MgJ8BRhMmmLZsNPHcDWfPZBlDW5vWBNn9CkMY0jxiSj8HQH83M06nKoT/+3g2pOydbiETQj+Yy0W8KNkiNGTYvgftJiQzsHTBK0ujrN4WfZGE5RxdnMnHuTvZ1X4JMjlQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755678872; c=relaxed/simple; bh=+RHqySFbfhv8ZIPc+OLu0zUIEfW5E7dLbQ/D4r26FoU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dcodw2T9JuG3/EUqLZbUcZzw0p1VpohWrplnRa0WuLlJrcGe98nfy1uCMmw25KwVOdgwvXreizgwkDtwL3o3CgjBm85YeCV/VI2GylM9eE55jGeuyIKv3oBDF0cOtK9XvosbiWcS182gJgA75su4XGj/ugbjvmJMsFenQLErAgY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=QeXNjW1g; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="QeXNjW1g" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 57K8YQOS3154246; Wed, 20 Aug 2025 03:34:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1755678866; bh=GY39GJdCPvM3cH171BB9k5yHQ1eCoIKMtZb6pSuuJdI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=QeXNjW1g28W063AuPqO/PMaJfq6Cc1uTF8IvAGPIT2dxrAXz6EsiwmaFrGOOdR++j btuC2c0D9+vPciRmH1Q/k4YUVLZv1sb2M/qDbliT9AW/1Ma1WoxKxoK/CZqsvwld/o 09EfoctzcVddNnMqitcrW+oamC316hWSGH1pLdAc= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 57K8YPSr1920213 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Wed, 20 Aug 2025 03:34:25 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Wed, 20 Aug 2025 03:34:25 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Wed, 20 Aug 2025 03:34:25 -0500 Received: from localhost (ula0502350.dhcp.ti.com [172.24.233.249]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 57K8YOBM228618; Wed, 20 Aug 2025 03:34:25 -0500 From: Paresh Bhagat To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH 4/4] cpufreq: ti: Add support for AM62D2 Date: Wed, 20 Aug 2025 14:03:31 +0530 Message-ID: <20250820083331.3412378-5-p-bhagat@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820083331.3412378-1-p-bhagat@ti.com> References: <20250820083331.3412378-1-p-bhagat@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Add support for TI K3 AM62D2 SoC to read speed and revision values from hardware and pass to OPP layer. AM62D shares the same configuations as AM62A so use existing am62a7_soc_data. Signed-off-by: Paresh Bhagat --- drivers/cpufreq/ti-cpufreq.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 5a5147277cd0..9a912d309315 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -310,6 +310,7 @@ static const struct soc_device_attribute k3_cpufreq_soc= [] =3D { { .family =3D "AM62X", .revision =3D "SR1.0" }, { .family =3D "AM62AX", .revision =3D "SR1.0" }, { .family =3D "AM62PX", .revision =3D "SR1.0" }, + { .family =3D "AM62DX", .revision =3D "SR1.0" }, { /* sentinel */ } }; =20 @@ -457,6 +458,7 @@ static const struct of_device_id ti_cpufreq_of_match[] = __maybe_unused =3D { { .compatible =3D "ti,omap36xx", .data =3D &omap36xx_soc_data, }, { .compatible =3D "ti,am625", .data =3D &am625_soc_data, }, { .compatible =3D "ti,am62a7", .data =3D &am62a7_soc_data, }, + { .compatible =3D "ti,am62d2", .data =3D &am62a7_soc_data, }, { .compatible =3D "ti,am62p5", .data =3D &am62p5_soc_data, }, /* legacy */ { .compatible =3D "ti,omap3430", .data =3D &omap34xx_soc_data, }, --=20 2.34.1