From nobody Sat Oct 4 04:59:55 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EFA8237A4F; Wed, 20 Aug 2025 07:58:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755676700; cv=none; b=nM+jOQka9T0IM3wB+PghW5Q0ENupOy7+umz96cOsyozPIcRXtNWcza2hdUuLWu4rxWj3ZfqeDeJo6plZgRleqdtDsG/V4hVbKIx3Uv2SMPLxSRKpO7CLYN3R06k2jv1yYVTiie3eamJ5Ojjdmkw79kPcwa9ytRt5k0KILFoB02I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755676700; c=relaxed/simple; bh=VswK+T6lrXX8TBMHScYShK1aPc7/uYZrwhvm7c2S5a8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=lZLV7Du7mqPkAAUgDbu7P4ReBiJ2rEodqFCpUO904MU1PM1Z6IWxSOscSCt4QubxX1wF4zkQxdAE/dzsvbJo4UcYoopevGMnhinw5dyF9UAPLZRATC9P59+r1GWJRHKj9xC86yHlnkc0OJDODc8mmT7n+ZbxAwrPfeYXKfGqnR4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=TyroSmEu; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="TyroSmEu" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57K7ONlA019376; Wed, 20 Aug 2025 09:57:35 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= OufJCp1rsW8Y0CwW3FwQWRlgvOGtMFrmPlUPtX/3tvI=; b=TyroSmEuVdY6idAu OUnsV10dWfwzxPh5fPhQ6+8E8xUWkWZP6832cHrI2t1ViE7R29zInci/QfN8HW3T hWWol3Mr2JDufPAq/7kWOCHOEYSiEk22TmSapyaoWsSwgg9HSr+GMNTyUc8IiqLy DpJbC63vdoGNdCvYlfXR7GemBqlMbdHIogrJ8yygrOSTDR60tetEPVxzVUlxo7QA SLBvfNzmzhQ9TtDy36T5zTDLAk00KmGsZQn1sA8kwieVVE5/sXfhg/q4Av/cosTW NFHnCX1/QhnRb+Aa14jFIQjZX9nFJz7xzarnAAmv+hX8xx2EKV2q3c2AYQ2u0vJw 5Zk2eA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48n7548wy4-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 20 Aug 2025 09:57:35 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id E76E540046; Wed, 20 Aug 2025 09:56:03 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 7D32C475830; Wed, 20 Aug 2025 09:54:42 +0200 (CEST) Received: from localhost (10.130.77.120) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 20 Aug 2025 09:54:42 +0200 From: Christian Bruel To: , , , , , , , , , , , , , , , , , , , CC: , , , , , , , Subject: [PATCH v13 01/11] Documentation: pinctrl: Describe PM helper functions for standard states. Date: Wed, 20 Aug 2025 09:54:01 +0200 Message-ID: <20250820075411.1178729-2-christian.bruel@foss.st.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250820075411.1178729-1-christian.bruel@foss.st.com> References: <20250820075411.1178729-1-christian.bruel@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-20_03,2025-08-20_01,2025-03-28_01 Content-Type: text/plain; charset="utf-8" Clarify documentation for predefined standard state names 'default', 'init', 'sleep', 'idle' and their associated PM API. Reviewed-by: Linus Walleij Signed-off-by: Christian Bruel --- Documentation/driver-api/pin-control.rst | 57 +++++++++++++++++++++++- 1 file changed, 55 insertions(+), 2 deletions(-) diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/drive= r-api/pin-control.rst index 27ea1236307e..204cc3e162e2 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -1162,8 +1162,55 @@ pinmux core. Pin control requests from drivers =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D =20 -When a device driver is about to probe the device core will automatically -attempt to issue ``pinctrl_get_select_default()`` on these devices. +When a device driver is about to probe, the device core attaches the +standard states if they are defined in the device tree by calling +``pinctrl_bind_pins()`` on these devices. +Possible standard state names are: "default", "init", "sleep" and "idle". + +- if ``default`` is defined in the device tree, it is selected before + device probe. + +- if ``init`` and ``default`` are defined in the device tree, the "init" + state is selected before the driver probe and the "default" state is + selected after the driver probe. + +- the ``sleep`` and ``idle`` states are for power management and can only + be selected with the PM API bellow. + +PM interfaces +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +PM runtime suspend/resume might need to execute the same init sequence as +during probe. Since the predefined states are already attached to the +device, the driver can activate these states explicitly with the +following helper functions: + +- ``pinctrl_pm_select_default_state()`` +- ``pinctrl_pm_select_init_state()`` +- ``pinctrl_pm_select_sleep_state()`` +- ``pinctrl_pm_select_idle_state()`` + +For example, if resuming the device depend on certain pinmux states + +.. code-block:: c + + foo_suspend() + { + /* suspend device */ + ... + + pinctrl_pm_select_sleep_state(dev); + } + + foo_resume() + { + pinctrl_pm_select_init_state(dev); + + /* resuming device */ + ... + + pinctrl_pm_select_default_state(dev); + } + This way driver writers do not need to add any of the boilerplate code of the type found below. However when doing fine-grained state selection and not using the "default" state, you may have to do some device driver @@ -1185,6 +1232,12 @@ operation and going to sleep, moving from the ``PINC= TRL_STATE_DEFAULT`` to ``PINCTRL_STATE_SLEEP`` at runtime, re-biasing or even re-muxing pins to s= ave current in sleep mode. =20 +Another case is when the pinctrl needs to switch to a certain mode during +probe and then revert to the default state at the end of probe. For example +a PINMUX may need to be configured as a GPIO during probe. In this case, u= se +``PINCTRL_STATE_INIT`` to switch state before probe, then move to +``PINCTRL_STATE_DEFAULT`` at the end of probe for normal operation. + A driver may request a certain control state to be activated, usually just= the default state like this: =20 --=20 2.34.1 From nobody Sat Oct 4 04:59:55 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27F2E2D6E6D; Wed, 20 Aug 2025 07:58:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755676702; cv=none; b=REZIo1vmfP2i9qWNu5bCpqa8XEeT7OfBj9Qm7xhDEqxG+hH5gT5tMjnR6tUEK6FLSB67TQJcR7N5/9V93zpDtpqe2FrlfotFFqyfXdMAovAPWZZp2KmhPGTRLqi/OKRRglGWZO/MUTZVqN9PXJ4UQRkvivlNflVObwVq5AVVfko= ARC-Message-Signature: i=1; a=rsa-sha256; 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charset="utf-8" If a platform requires an initial pinctrl state during probing, this helper function provides the client with access to the same initial state. eg: xxx_suspend_noirq ... pinctrl_pm_select_sleep_state xxx resume_noirq pinctrl_pm_select_init_state ... pinctrl_pm_select_default_state Reviewed-by: Linus Walleij Signed-off-by: Christian Bruel --- drivers/pinctrl/core.c | 13 +++++++++++++ include/linux/pinctrl/consumer.h | 10 ++++++++++ 2 files changed, 23 insertions(+) diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c index 73b78d6eac67..c5dbf4e9db84 100644 --- a/drivers/pinctrl/core.c +++ b/drivers/pinctrl/core.c @@ -1655,6 +1655,19 @@ int pinctrl_pm_select_default_state(struct device *d= ev) } EXPORT_SYMBOL_GPL(pinctrl_pm_select_default_state); =20 +/** + * pinctrl_pm_select_init_state() - select init pinctrl state for PM + * @dev: device to select init state for + */ +int pinctrl_pm_select_init_state(struct device *dev) +{ + if (!dev->pins) + return 0; + + return pinctrl_select_bound_state(dev, dev->pins->init_state); +} +EXPORT_SYMBOL_GPL(pinctrl_pm_select_init_state); + /** * pinctrl_pm_select_sleep_state() - select sleep pinctrl state for PM * @dev: device to select sleep state for diff --git a/include/linux/pinctrl/consumer.h b/include/linux/pinctrl/consu= mer.h index 73de70362b98..63ce16191eb9 100644 --- a/include/linux/pinctrl/consumer.h +++ b/include/linux/pinctrl/consumer.h @@ -48,6 +48,7 @@ int pinctrl_select_default_state(struct device *dev); =20 #ifdef CONFIG_PM int pinctrl_pm_select_default_state(struct device *dev); +int pinctrl_pm_select_init_state(struct device *dev); int pinctrl_pm_select_sleep_state(struct device *dev); int pinctrl_pm_select_idle_state(struct device *dev); #else @@ -55,6 +56,10 @@ static inline int pinctrl_pm_select_default_state(struct= device *dev) { return 0; } +static inline int pinctrl_pm_select_init_state(struct device *dev) +{ + return 0; +} static inline int pinctrl_pm_select_sleep_state(struct device *dev) { return 0; @@ -143,6 +148,11 @@ static inline int pinctrl_pm_select_default_state(stru= ct device *dev) return 0; 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charset="utf-8" Document the bindings for STM32MP25 PCIe Controller configured in root complex mode with one root port. Supports 4 INTx and MSI interrupts from the ARM GICv2m controller. STM32 PCIe may be in a power domain which is the case for the STM32MP25 based boards. Supports WAKE# from wake-gpios Signed-off-by: Christian Bruel Reviewed-by: Rob Herring (Arm) Acked-by: Manivannan Sadhasivam --- .../bindings/pci/st,stm32-pcie-common.yaml | 33 ++++++ .../bindings/pci/st,stm32-pcie-host.yaml | 112 ++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-com= mon.yaml create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-hos= t.yaml diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yam= l b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml new file mode 100644 index 000000000000..5adbff259204 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-common.yaml @@ -0,0 +1,33 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STM32MP25 PCIe RC/EP controller + +maintainers: + - Christian Bruel + +description: + STM32MP25 PCIe RC/EP common properties + +properties: + clocks: + maxItems: 1 + description: PCIe system clock + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + access-controllers: + maxItems: 1 + +required: + - clocks + - resets + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml = b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml new file mode 100644 index 000000000000..443bfe2cdc98 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-host.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 PCIe Root Complex + +maintainers: + - Christian Bruel + +description: + PCIe root complex controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-rc + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: config + + msi-parent: + maxItems: 1 + +patternProperties: + '^pcie@[0-2],0$': + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + wake-gpios: + description: GPIO used as WAKE# input signal + maxItems: 1 + + required: + - phys + - ranges + + unevaluatedProperties: false + +required: + - interrupt-map + - interrupt-map-mask + - ranges + - dma-ranges + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + pcie@48400000 { + compatible =3D "st,stm32mp25-pcie-rc"; + device_type =3D "pci"; + reg =3D <0x48400000 0x400000>, + <0x10000000 0x10000>; + reg-names =3D "dbi", "config"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HI= GH>, + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH= >, + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH= >, + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH= >; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; + dma-ranges =3D <0x42000000 0x0 0x80000000 0x80000000 0x0 0x8000000= 0>; + clocks =3D <&rcc CK_BUS_PCIE>; + resets =3D <&rcc PCIE_R>; + msi-parent =3D <&v2m0>; + access-controllers =3D <&rifsc 68>; + power-domains =3D <&CLUSTER_PD>; + + pcie@0,0 { + device_type =3D "pci"; + reg =3D <0x0 0x0 0x0 0x0 0x0>; + phys =3D <&combophy PHY_TYPE_PCIE>; + wake-gpios =3D <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; 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charset="utf-8" Add driver for the STM32MP25 SoC PCIe Gen1 2.5 GT/s and Gen2 5GT/s controller based on the DesignWare PCIe core. Supports MSI via GICv2m, Single Virtual Channel, Single Function Supports WAKE# GPIO. Signed-off-by: Christian Bruel --- drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-stm32.c | 360 ++++++++++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.h | 15 + 4 files changed, 388 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-stm32.c create mode 100644 drivers/pci/controller/dwc/pcie-stm32.h diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index deafc512b079..a8174817fd5b 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -423,6 +423,18 @@ config PCIE_SPEAR13XX help Say Y here if you want PCIe support on SPEAr13XX SoCs. =20 +config PCIE_STM32_HOST + tristate "STMicroelectronics STM32MP25 PCIe Controller (host mode)" + depends on ARCH_STM32 || COMPILE_TEST + depends on PCI_MSI + select PCIE_DW_HOST + help + Enables Root Complex (RC) support for the DesignWare core based PCIe + controller found in STM32MP25 SoC. + + This driver can also be built as a module. If so, the module + will be called pcie-stm32. + config PCI_DRA7XX tristate =20 diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 6919d27798d1..1307a87b1cf0 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_PCIE_UNIPHIER) +=3D pcie-uniphier.o obj-$(CONFIG_PCIE_UNIPHIER_EP) +=3D pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) +=3D pcie-visconti.o obj-$(CONFIG_PCIE_RCAR_GEN4) +=3D pcie-rcar-gen4.o +obj-$(CONFIG_PCIE_STM32_HOST) +=3D pcie-stm32.o =20 # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-stm32.c b/drivers/pci/controll= er/dwc/pcie-stm32.c new file mode 100644 index 000000000000..964fa6f674c8 --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32.c @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32MP25 PCIe root complex driver. + * + * Copyright (C) 2025 STMicroelectronics + * Author: Christian Bruel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pcie-designware.h" +#include "pcie-stm32.h" +#include "../../pci.h" + +struct stm32_pcie { + struct dw_pcie pci; + struct regmap *regmap; + struct reset_control *rst; + struct phy *phy; + struct clk *clk; + struct gpio_desc *perst_gpio; + struct gpio_desc *wake_gpio; +}; + +static void stm32_pcie_deassert_perst(struct stm32_pcie *stm32_pcie) +{ + if (stm32_pcie->perst_gpio) { + msleep(PCIE_T_PVPERL_MS); + gpiod_set_value(stm32_pcie->perst_gpio, 0); + } + + msleep(PCIE_RESET_CONFIG_WAIT_MS); +} + +static void stm32_pcie_assert_perst(struct stm32_pcie *stm32_pcie) +{ + gpiod_set_value(stm32_pcie->perst_gpio, 1); +} + +static int stm32_pcie_start_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie =3D to_stm32_pcie(pci); + + return regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_LTSSM_EN, + STM32MP25_PCIECR_LTSSM_EN); +} + +static void stm32_pcie_stop_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie =3D to_stm32_pcie(pci); + + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_LTSSM_EN, 0); +} + +static int stm32_pcie_suspend_noirq(struct device *dev) +{ + struct stm32_pcie *stm32_pcie =3D dev_get_drvdata(dev); + int ret; + + ret =3D dw_pcie_suspend_noirq(&stm32_pcie->pci); + if (ret) + return ret; + + stm32_pcie_assert_perst(stm32_pcie); + + clk_disable_unprepare(stm32_pcie->clk); + + if (!device_wakeup_path(dev)) + phy_exit(stm32_pcie->phy); + + return pinctrl_pm_select_sleep_state(dev); +} + +static int stm32_pcie_resume_noirq(struct device *dev) +{ + struct stm32_pcie *stm32_pcie =3D dev_get_drvdata(dev); + int ret; + + /* + * The core clock is gated with CLKREQ# from the COMBOPHY REFCLK, + * thus if no device is present, must deassert it with a GPIO from + * pinctrl pinmux before accessing the DBI registers. + */ + ret =3D pinctrl_pm_select_init_state(dev); + if (ret) { + dev_err(dev, "Failed to activate pinctrl pm state: %d\n", ret); + return ret; + } + + if (!device_wakeup_path(dev)) { + ret =3D phy_init(stm32_pcie->phy); + if (ret) { + pinctrl_pm_select_default_state(dev); + return ret; + } + } + + ret =3D clk_prepare_enable(stm32_pcie->clk); + if (ret) + goto err_phy_exit; + + stm32_pcie_deassert_perst(stm32_pcie); + + ret =3D dw_pcie_resume_noirq(&stm32_pcie->pci); + if (ret) + goto err_disable_clk; + + pinctrl_pm_select_default_state(dev); + + return 0; + +err_disable_clk: + stm32_pcie_assert_perst(stm32_pcie); + clk_disable_unprepare(stm32_pcie->clk); + +err_phy_exit: + phy_exit(stm32_pcie->phy); + pinctrl_pm_select_default_state(dev); + + return ret; +} + +static const struct dev_pm_ops stm32_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(stm32_pcie_suspend_noirq, + stm32_pcie_resume_noirq) +}; + +static const struct dw_pcie_host_ops stm32_pcie_host_ops =3D { +}; + +static const struct dw_pcie_ops dw_pcie_ops =3D { + .start_link =3D stm32_pcie_start_link, + .stop_link =3D stm32_pcie_stop_link +}; + +static int stm32_add_pcie_port(struct stm32_pcie *stm32_pcie) +{ + struct device *dev =3D stm32_pcie->pci.dev; + unsigned int wake_irq; + int ret; + + ret =3D phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE); + if (ret) + return ret; + + ret =3D phy_init(stm32_pcie->phy); + if (ret) + return ret; + + ret =3D regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_TYPE_MASK, + STM32MP25_PCIECR_RC); + if (ret) + goto err_phy_exit; + + stm32_pcie_deassert_perst(stm32_pcie); + + if (stm32_pcie->wake_gpio) { + wake_irq =3D gpiod_to_irq(stm32_pcie->wake_gpio); + ret =3D dev_pm_set_dedicated_wake_irq(dev, wake_irq); + if (ret) { + dev_err(dev, "Failed to enable wakeup irq %d\n", ret); + goto err_assert_perst; + } + irq_set_irq_type(wake_irq, IRQ_TYPE_EDGE_FALLING); + } + + return 0; + +err_assert_perst: + stm32_pcie_assert_perst(stm32_pcie); + +err_phy_exit: + phy_exit(stm32_pcie->phy); + + return ret; +} + +static void stm32_remove_pcie_port(struct stm32_pcie *stm32_pcie) +{ + dev_pm_clear_wake_irq(stm32_pcie->pci.dev); + + stm32_pcie_assert_perst(stm32_pcie); + + phy_exit(stm32_pcie->phy); +} + +static int stm32_pcie_parse_port(struct stm32_pcie *stm32_pcie) +{ + struct device *dev =3D stm32_pcie->pci.dev; + struct device_node *root_port; + + root_port =3D of_get_next_available_child(dev->of_node, NULL); + + stm32_pcie->phy =3D devm_of_phy_get(dev, root_port, NULL); + if (IS_ERR(stm32_pcie->phy)) { + of_node_put(root_port); + return dev_err_probe(dev, PTR_ERR(stm32_pcie->phy), + "Failed to get pcie-phy\n"); + } + + stm32_pcie->perst_gpio =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(ro= ot_port), + "reset", GPIOD_OUT_HIGH, NULL); + if (IS_ERR(stm32_pcie->perst_gpio)) { + if (PTR_ERR(stm32_pcie->perst_gpio) !=3D -ENOENT) { + of_node_put(root_port); + return dev_err_probe(dev, PTR_ERR(stm32_pcie->perst_gpio), + "Failed to get reset GPIO\n"); + } + stm32_pcie->perst_gpio =3D NULL; + } + + stm32_pcie->wake_gpio =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(roo= t_port), + "wake", GPIOD_IN, NULL); + + if (IS_ERR(stm32_pcie->wake_gpio)) { + if (PTR_ERR(stm32_pcie->wake_gpio) !=3D -ENOENT) { + of_node_put(root_port); + return dev_err_probe(dev, PTR_ERR(stm32_pcie->wake_gpio), + "Failed to get wake GPIO\n"); + } + stm32_pcie->wake_gpio =3D NULL; + } + + of_node_put(root_port); + + return 0; +} + +static int stm32_pcie_probe(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie; + struct device *dev =3D &pdev->dev; + int ret; + + stm32_pcie =3D devm_kzalloc(dev, sizeof(*stm32_pcie), GFP_KERNEL); + if (!stm32_pcie) + return -ENOMEM; + + stm32_pcie->pci.dev =3D dev; + stm32_pcie->pci.ops =3D &dw_pcie_ops; + stm32_pcie->pci.pp.ops =3D &stm32_pcie_host_ops; + + stm32_pcie->regmap =3D syscon_regmap_lookup_by_compatible("st,stm32mp25-s= yscfg"); + if (IS_ERR(stm32_pcie->regmap)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->regmap), + "No syscfg specified\n"); + + stm32_pcie->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(stm32_pcie->clk)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->clk), + "Failed to get PCIe clock source\n"); + + stm32_pcie->rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(stm32_pcie->rst)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->rst), + "Failed to get PCIe reset\n"); + + ret =3D stm32_pcie_parse_port(stm32_pcie); + if (ret) + return ret; + + platform_set_drvdata(pdev, stm32_pcie); + + ret =3D stm32_add_pcie_port(stm32_pcie); + if (ret) + return ret; + + reset_control_assert(stm32_pcie->rst); + reset_control_deassert(stm32_pcie->rst); + + ret =3D clk_prepare_enable(stm32_pcie->clk); + if (ret) { + dev_err(dev, "Core clock enable failed %d\n", ret); + goto err_remove_port; + } + + ret =3D pm_runtime_set_active(dev); + if (ret < 0) { + clk_disable_unprepare(stm32_pcie->clk); + stm32_remove_pcie_port(stm32_pcie); + return dev_err_probe(dev, ret, "Failed to activate runtime PM\n"); + } + + pm_runtime_no_callbacks(dev); + + ret =3D devm_pm_runtime_enable(dev); + if (ret < 0) { + clk_disable_unprepare(stm32_pcie->clk); + stm32_remove_pcie_port(stm32_pcie); + return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); + } + + ret =3D dw_pcie_host_init(&stm32_pcie->pci.pp); + if (ret) + goto err_disable_clk; + + if (stm32_pcie->wake_gpio) + device_init_wakeup(dev, true); + + return 0; + +err_disable_clk: + clk_disable_unprepare(stm32_pcie->clk); + +err_remove_port: + stm32_remove_pcie_port(stm32_pcie); + + return ret; +} + +static void stm32_pcie_remove(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie =3D platform_get_drvdata(pdev); + struct dw_pcie_rp *pp =3D &stm32_pcie->pci.pp; + + if (stm32_pcie->wake_gpio) + device_init_wakeup(&pdev->dev, false); + + dw_pcie_host_deinit(pp); + + clk_disable_unprepare(stm32_pcie->clk); + + stm32_remove_pcie_port(stm32_pcie); + + pm_runtime_put_noidle(&pdev->dev); +} + +static const struct of_device_id stm32_pcie_of_match[] =3D { + { .compatible =3D "st,stm32mp25-pcie-rc" }, + {}, +}; + +static struct platform_driver stm32_pcie_driver =3D { + .probe =3D stm32_pcie_probe, + .remove =3D stm32_pcie_remove, + .driver =3D { + .name =3D "stm32-pcie", + .of_match_table =3D stm32_pcie_of_match, + .pm =3D &stm32_pcie_pm_ops, + .probe_type =3D PROBE_PREFER_ASYNCHRONOUS, + }, +}; + +module_platform_driver(stm32_pcie_driver); + +MODULE_AUTHOR("Christian Bruel "); +MODULE_DESCRIPTION("STM32MP25 PCIe Controller driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, stm32_pcie_of_match); diff --git a/drivers/pci/controller/dwc/pcie-stm32.h b/drivers/pci/controll= er/dwc/pcie-stm32.h new file mode 100644 index 000000000000..387112c4e42c --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * ST PCIe driver definitions for STM32-MP25 SoC + * + * Copyright (C) 2025 STMicroelectronics - All Rights Reserved + * Author: Christian Bruel + */ + +#define to_stm32_pcie(x) dev_get_drvdata((x)->dev) + +#define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8) +#define STM32MP25_PCIECR_LTSSM_EN BIT(2) +#define STM32MP25_PCIECR_RC BIT(10) + +#define SYSCFG_PCIECR 0x6000 --=20 2.34.1 From nobody Sat Oct 4 04:59:55 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24C802D8791; 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charset="utf-8" STM32MP25 PCIe Controller is based on the DesignWare core configured as end point mode from the SYSCFG register. Signed-off-by: Christian Bruel Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/st,stm32-pcie-ep.yaml | 73 +++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.= yaml diff --git a/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml b/= Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml new file mode 100644 index 000000000000..b076ada4f332 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/st,stm32-pcie-ep.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/st,stm32-pcie-ep.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics STM32MP25 PCIe Endpoint + +maintainers: + - Christian Bruel + +description: + PCIe endpoint controller based on the Synopsys DesignWare PCIe core. + +allOf: + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# + - $ref: /schemas/pci/st,stm32-pcie-common.yaml# + +properties: + compatible: + const: st,stm32mp25-pcie-ep + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: Data Bus Interface (DBI) shadow registers. + - description: Internal Address Translation Unit (iATU) registers. + - description: PCIe configuration registers. + + reg-names: + items: + - const: dbi + - const: dbi2 + - const: atu + - const: addr_space + + reset-gpios: + description: GPIO controlled connection to PERST# signal + maxItems: 1 + + phys: + maxItems: 1 + +required: + - phys + - reset-gpios + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + pcie-ep@48400000 { + compatible =3D "st,stm32mp25-pcie-ep"; + reg =3D <0x48400000 0x400000>, + <0x48500000 0x100000>, + <0x48700000 0x80000>, + <0x10000000 0x10000000>; + reg-names =3D "dbi", "dbi2", "atu", "addr_space"; + clocks =3D <&rcc CK_BUS_PCIE>; + phys =3D <&combophy PHY_TYPE_PCIE>; + resets =3D <&rcc PCIE_R>; + pinctrl-names =3D "default", "init"; + pinctrl-0 =3D <&pcie_pins_a>; + pinctrl-1 =3D <&pcie_init_pins_a>; + reset-gpios =3D <&gpioj 8 GPIO_ACTIVE_LOW>; + access-controllers =3D <&rifsc 68>; + power-domains =3D <&CLUSTER_PD>; + }; --=20 2.34.1 From nobody Sat Oct 4 04:59:55 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FA012D9795; Wed, 20 Aug 2025 07:59:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755676796; 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charset="utf-8" Add driver to configure the STM32MP25 SoC PCIe Gen1 2.5GT/s or Gen2 5GT/s controller based on the DesignWare PCIe core in endpoint mode. Uses the common reference clock provided by the host. The PCIe core_clk receives the pipe0_clk from the ComboPHY as input, and the ComboPHY PLL must be locked for pipe0_clk to be ready. Consequently, PCIe core registers cannot be accessed until the ComboPHY is fully initialised and REFCLK is enabled and ready. Signed-off-by: Christian Bruel --- drivers/pci/controller/dwc/Kconfig | 12 + drivers/pci/controller/dwc/Makefile | 1 + drivers/pci/controller/dwc/pcie-stm32-ep.c | 384 +++++++++++++++++++++ drivers/pci/controller/dwc/pcie-stm32.h | 1 + 4 files changed, 398 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-stm32-ep.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index a8174817fd5b..34abc859c107 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -435,6 +435,18 @@ config PCIE_STM32_HOST This driver can also be built as a module. If so, the module will be called pcie-stm32. =20 +config PCIE_STM32_EP + tristate "STMicroelectronics STM32MP25 PCIe Controller (endpoint mode)" + depends on ARCH_STM32 || COMPILE_TEST + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Enables Endpoint (EP) support for the DesignWare core based PCIe + controller found in STM32MP25 SoC. + + This driver can also be built as a module. If so, the module + will be called pcie-stm32-ep. + config PCI_DRA7XX tristate =20 diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/d= wc/Makefile index 1307a87b1cf0..7ae28f3b0fb3 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) +=3D pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) +=3D pcie-visconti.o obj-$(CONFIG_PCIE_RCAR_GEN4) +=3D pcie-rcar-gen4.o obj-$(CONFIG_PCIE_STM32_HOST) +=3D pcie-stm32.o +obj-$(CONFIG_PCIE_STM32_EP) +=3D pcie-stm32-ep.o =20 # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/contr= oller/dwc/pcie-stm32-ep.c new file mode 100644 index 000000000000..1f46bcf0c79f --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c @@ -0,0 +1,384 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * STMicroelectronics STM32MP25 PCIe endpoint driver. + * + * Copyright (C) 2025 STMicroelectronics + * Author: Christian Bruel + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pcie-designware.h" +#include "pcie-stm32.h" + +enum stm32_pcie_ep_link_status { + STM32_PCIE_EP_LINK_DISABLED, + STM32_PCIE_EP_LINK_ENABLED, +}; + +struct stm32_pcie { + struct dw_pcie pci; + struct regmap *regmap; + struct reset_control *rst; + struct phy *phy; + struct clk *clk; + struct gpio_desc *perst_gpio; + enum stm32_pcie_ep_link_status link_status; + unsigned int perst_irq; +}; + +static void stm32_pcie_ep_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + enum pci_barno bar; + + for (bar =3D 0; bar < PCI_STD_NUM_BARS; bar++) + dw_pcie_ep_reset_bar(pci, bar); +} + +static int stm32_pcie_enable_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie =3D to_stm32_pcie(pci); + + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_LTSSM_EN, + STM32MP25_PCIECR_LTSSM_EN); + + return dw_pcie_wait_for_link(pci); +} + +static void stm32_pcie_disable_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie =3D to_stm32_pcie(pci); + + regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, STM32MP25_PCIECR_LT= SSM_EN, 0); +} + +static int stm32_pcie_start_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie =3D to_stm32_pcie(pci); + int ret; + + if (stm32_pcie->link_status =3D=3D STM32_PCIE_EP_LINK_ENABLED) { + dev_dbg(pci->dev, "Link is already enabled\n"); + return 0; + } + + dev_dbg(pci->dev, "Enable link\n"); + + ret =3D stm32_pcie_enable_link(pci); + if (ret) { + dev_err(pci->dev, "PCIe cannot establish link: %d\n", ret); + return ret; + } + + enable_irq(stm32_pcie->perst_irq); + + stm32_pcie->link_status =3D STM32_PCIE_EP_LINK_ENABLED; + + return 0; +} + +static void stm32_pcie_stop_link(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie =3D to_stm32_pcie(pci); + + if (stm32_pcie->link_status =3D=3D STM32_PCIE_EP_LINK_DISABLED) { + dev_dbg(pci->dev, "Link is already disabled\n"); + return; + } + + dev_dbg(pci->dev, "Disable link\n"); + + disable_irq(stm32_pcie->perst_irq); + + stm32_pcie_disable_link(pci); + + stm32_pcie->link_status =3D STM32_PCIE_EP_LINK_DISABLED; +} + +static int stm32_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + unsigned int type, u16 interrupt_num) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_IRQ_INTX: + return dw_pcie_ep_raise_intx_irq(ep, func_no); + case PCI_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(pci->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } +} + +static const struct pci_epc_features stm32_pcie_epc_features =3D { + .msi_capable =3D true, + .align =3D SZ_64K, +}; + +static const struct pci_epc_features* +stm32_pcie_get_features(struct dw_pcie_ep *ep) +{ + return &stm32_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops stm32_pcie_ep_ops =3D { + .init =3D stm32_pcie_ep_init, + .raise_irq =3D stm32_pcie_raise_irq, + .get_features =3D stm32_pcie_get_features, +}; + +static const struct dw_pcie_ops dw_pcie_ops =3D { + .start_link =3D stm32_pcie_start_link, + .stop_link =3D stm32_pcie_stop_link, +}; + +static int stm32_pcie_enable_resources(struct stm32_pcie *stm32_pcie) +{ + int ret; + + ret =3D phy_init(stm32_pcie->phy); + if (ret) + return ret; + + ret =3D clk_prepare_enable(stm32_pcie->clk); + if (ret) + phy_exit(stm32_pcie->phy); + + return ret; +} + +static void stm32_pcie_disable_resources(struct stm32_pcie *stm32_pcie) +{ + clk_disable_unprepare(stm32_pcie->clk); + + phy_exit(stm32_pcie->phy); +} + +static void stm32_pcie_perst_assert(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie =3D to_stm32_pcie(pci); + struct dw_pcie_ep *ep =3D &stm32_pcie->pci.ep; + struct device *dev =3D pci->dev; + + dev_dbg(dev, "PERST asserted by host\n"); + + pci_epc_deinit_notify(ep->epc); + + stm32_pcie_disable_resources(stm32_pcie); + + pm_runtime_put_sync(dev); +} + +static void stm32_pcie_perst_deassert(struct dw_pcie *pci) +{ + struct stm32_pcie *stm32_pcie =3D to_stm32_pcie(pci); + struct device *dev =3D pci->dev; + struct dw_pcie_ep *ep =3D &pci->ep; + int ret; + + dev_dbg(dev, "PERST de-asserted by host\n"); + + ret =3D pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_err(dev, "Failed to resume runtime PM: %d\n", ret); + return; + } + + ret =3D stm32_pcie_enable_resources(stm32_pcie); + if (ret) { + dev_err(dev, "Failed to enable resources: %d\n", ret); + goto err_pm_put_sync; + } + + /* + * Need to reprogram the configuration space registers here because the + * DBI registers were incorrectly reset by the PHY RCC during phy_init(). + */ + ret =3D dw_pcie_ep_init_registers(ep); + if (ret) { + dev_err(dev, "Failed to complete initialization: %d\n", ret); + goto err_disable_resources; + } + + pci_epc_init_notify(ep->epc); + + return; + +err_disable_resources: + stm32_pcie_disable_resources(stm32_pcie); + +err_pm_put_sync: + pm_runtime_put_sync(dev); +} + +static irqreturn_t stm32_pcie_ep_perst_irq_thread(int irq, void *data) +{ + struct stm32_pcie *stm32_pcie =3D data; + struct dw_pcie *pci =3D &stm32_pcie->pci; + u32 perst; + + perst =3D gpiod_get_value(stm32_pcie->perst_gpio); + if (perst) + stm32_pcie_perst_assert(pci); + else + stm32_pcie_perst_deassert(pci); + + irq_set_irq_type(gpiod_to_irq(stm32_pcie->perst_gpio), + (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW)); + + return IRQ_HANDLED; +} + +static int stm32_add_pcie_ep(struct stm32_pcie *stm32_pcie, + struct platform_device *pdev) +{ + struct dw_pcie_ep *ep =3D &stm32_pcie->pci.ep; + struct device *dev =3D &pdev->dev; + int ret; + + ret =3D regmap_update_bits(stm32_pcie->regmap, SYSCFG_PCIECR, + STM32MP25_PCIECR_TYPE_MASK, + STM32MP25_PCIECR_EP); + if (ret) + return ret; + + reset_control_assert(stm32_pcie->rst); + reset_control_deassert(stm32_pcie->rst); + + ep->ops =3D &stm32_pcie_ep_ops; + + ret =3D dw_pcie_ep_init(ep); + if (ret) { + dev_err(dev, "Failed to initialize ep: %d\n", ret); + return ret; + } + + ret =3D stm32_pcie_enable_resources(stm32_pcie); + if (ret) { + dev_err(dev, "Failed to enable resources: %d\n", ret); + dw_pcie_ep_deinit(ep); + return ret; + } + + return 0; +} + +static int stm32_pcie_probe(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie; + struct device *dev =3D &pdev->dev; + int ret; + + stm32_pcie =3D devm_kzalloc(dev, sizeof(*stm32_pcie), GFP_KERNEL); + if (!stm32_pcie) + return -ENOMEM; + + stm32_pcie->pci.dev =3D dev; + stm32_pcie->pci.ops =3D &dw_pcie_ops; + + stm32_pcie->regmap =3D syscon_regmap_lookup_by_compatible("st,stm32mp25-s= yscfg"); + if (IS_ERR(stm32_pcie->regmap)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->regmap), + "No syscfg specified\n"); + + stm32_pcie->phy =3D devm_phy_get(dev, NULL); + if (IS_ERR(stm32_pcie->phy)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->phy), + "failed to get pcie-phy\n"); + + stm32_pcie->clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(stm32_pcie->clk)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->clk), + "Failed to get PCIe clock source\n"); + + stm32_pcie->rst =3D devm_reset_control_get_exclusive(dev, NULL); + if (IS_ERR(stm32_pcie->rst)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->rst), + "Failed to get PCIe reset\n"); + + stm32_pcie->perst_gpio =3D devm_gpiod_get(dev, "reset", GPIOD_IN); + if (IS_ERR(stm32_pcie->perst_gpio)) + return dev_err_probe(dev, PTR_ERR(stm32_pcie->perst_gpio), + "Failed to get reset GPIO\n"); + + ret =3D phy_set_mode(stm32_pcie->phy, PHY_MODE_PCIE); + if (ret) + return ret; + + platform_set_drvdata(pdev, stm32_pcie); + + pm_runtime_get_noresume(dev); + + ret =3D devm_pm_runtime_enable(dev); + if (ret < 0) { + pm_runtime_put_noidle(&pdev->dev); + return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); + } + + stm32_pcie->perst_irq =3D gpiod_to_irq(stm32_pcie->perst_gpio); + + /* Will be enabled in start_link when device is initialized. */ + irq_set_status_flags(stm32_pcie->perst_irq, IRQ_NOAUTOEN); + + ret =3D devm_request_threaded_irq(dev, stm32_pcie->perst_irq, NULL, + stm32_pcie_ep_perst_irq_thread, + IRQF_TRIGGER_HIGH | IRQF_ONESHOT, + "perst_irq", stm32_pcie); + if (ret) { + pm_runtime_put_noidle(&pdev->dev); + return dev_err_probe(dev, ret, "Failed to request PERST IRQ\n"); + } + + ret =3D stm32_add_pcie_ep(stm32_pcie, pdev); + if (ret) + pm_runtime_put_noidle(&pdev->dev); + + return ret; +} + +static void stm32_pcie_remove(struct platform_device *pdev) +{ + struct stm32_pcie *stm32_pcie =3D platform_get_drvdata(pdev); + struct dw_pcie *pci =3D &stm32_pcie->pci; + struct dw_pcie_ep *ep =3D &pci->ep; + + dw_pcie_stop_link(pci); + + pci_epc_deinit_notify(ep->epc); + dw_pcie_ep_deinit(ep); + + stm32_pcie_disable_resources(stm32_pcie); + + pm_runtime_put_sync(&pdev->dev); +} + +static const struct of_device_id stm32_pcie_ep_of_match[] =3D { + { .compatible =3D "st,stm32mp25-pcie-ep" }, + {}, +}; + +static struct platform_driver stm32_pcie_ep_driver =3D { + .probe =3D stm32_pcie_probe, + .remove =3D stm32_pcie_remove, + .driver =3D { + .name =3D "stm32-ep-pcie", + .of_match_table =3D stm32_pcie_ep_of_match, + }, +}; + +module_platform_driver(stm32_pcie_ep_driver); + +MODULE_AUTHOR("Christian Bruel "); +MODULE_DESCRIPTION("STM32MP25 PCIe Endpoint Controller driver"); +MODULE_LICENSE("GPL"); +MODULE_DEVICE_TABLE(of, stm32_pcie_ep_of_match); diff --git a/drivers/pci/controller/dwc/pcie-stm32.h b/drivers/pci/controll= er/dwc/pcie-stm32.h index 387112c4e42c..09d39f04e469 100644 --- a/drivers/pci/controller/dwc/pcie-stm32.h +++ b/drivers/pci/controller/dwc/pcie-stm32.h @@ -9,6 +9,7 @@ #define to_stm32_pcie(x) dev_get_drvdata((x)->dev) =20 #define STM32MP25_PCIECR_TYPE_MASK GENMASK(11, 8) +#define STM32MP25_PCIECR_EP 0 #define STM32MP25_PCIECR_LTSSM_EN BIT(2) #define STM32MP25_PCIECR_RC BIT(10) =20 --=20 2.34.1 From nobody Sat Oct 4 04:59:55 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B2D72C3266; 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charset="utf-8" Add myself as maintainer of STM32MP25 PCIe host and PCIe endpoint drivers Signed-off-by: Christian Bruel --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index fe168477caa4..8318f105e0cd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19377,6 +19377,13 @@ L: linux-samsung-soc@vger.kernel.org S: Maintained F: drivers/pci/controller/dwc/pci-exynos.c =20 +PCI DRIVER FOR STM32MP25 +M: Christian Bruel +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/st,stm32-pcie-*.yaml +F: drivers/pci/controller/dwc/*stm32* + PCI DRIVER FOR SYNOPSYS DESIGNWARE M: Jingoo Han M: Manivannan Sadhasivam --=20 2.34.1 From nobody Sat Oct 4 04:59:55 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 108352D979D; Wed, 20 Aug 2025 07:59:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Add PCIe pinctrl entries in stm32mp25-pinctrl.dtsi init: forces GPIO to low while probing so CLKREQ is low for phy_init default: restore the AFMUX after controller probe Add Analog pins of PCIe to perform power cycle Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boo= t/dts/st/stm32mp25-pinctrl.dtsi index 5ac9e72478dd..04e1606df126 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -133,6 +133,26 @@ pins { }; }; =20 + pcie_pins_a: pcie-0 { + pins { + pinmux =3D ; + bias-disable; + }; + }; + + pcie_init_pins_a: pcie-init-0 { + pins { + pinmux =3D ; + output-low; + }; + }; + + pcie_sleep_pins_a: pcie-sleep-0 { + pins { + pinmux =3D ; + }; + }; + pwm3_pins_a: pwm3-0 { pins { pinmux =3D ; /* TIM3_CH2 */ --=20 2.34.1 From nobody Sat Oct 4 04:59:55 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7ECD2237A4F; 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charset="utf-8" Add pcie_rc node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Root Complex mode Supports Gen1/Gen2, single lane, MSI interrupts using the ARM GICv2m Acked-by: Manivannan Sadhasivam Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 44 ++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 303abf915b8e..a3ed617a43d3 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -122,6 +122,15 @@ intc: interrupt-controller@4ac00000 { <0x0 0x4ac20000 0x0 0x20000>, <0x0 0x4ac40000 0x0 0x20000>, <0x0 0x4ac60000 0x0 0x20000>; + #address-cells =3D <2>; + #size-cells =3D <2>; + ranges; + + v2m0: v2m@48090000 { + compatible =3D "arm,gic-v2m-frame"; + reg =3D <0x0 0x48090000 0x0 0x1000>; + msi-controller; + }; }; =20 psci { @@ -1654,6 +1663,41 @@ stmmac_axi_config_1: stmmac-axi-config { snps,wr_osr_lmt =3D <0x7>; }; }; + + pcie_rc: pcie@48400000 { + compatible =3D "st,stm32mp25-pcie-rc"; + device_type =3D "pci"; + reg =3D <0x48400000 0x400000>, + <0x10000000 0x10000>; + reg-names =3D "dbi", "config"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &intc 0 0 GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; + #address-cells =3D <3>; + #size-cells =3D <2>; + ranges =3D <0x01000000 0x0 0x00000000 0x10010000 0x0 0x10000>, + <0x02000000 0x0 0x10020000 0x10020000 0x0 0x7fe0000>, + <0x42000000 0x0 0x18000000 0x18000000 0x0 0x8000000>; + dma-ranges =3D <0x42000000 0x0 0x80000000 0x80000000 0x0 0x80000000>; + clocks =3D <&rcc CK_BUS_PCIE>; + resets =3D <&rcc PCIE_R>; + msi-parent =3D <&v2m0>; + access-controllers =3D <&rifsc 68>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + + pcie@0,0 { + device_type =3D "pci"; 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charset="utf-8" Add pcie_ep node to support STM32 MP25 PCIe driver based on the DesignWare PCIe core configured as Endpoint mode Acked-by: Manivannan Sadhasivam Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index a3ed617a43d3..764b6a1623db 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1664,6 +1664,21 @@ stmmac_axi_config_1: stmmac-axi-config { }; }; =20 + pcie_ep: pcie-ep@48400000 { + compatible =3D "st,stm32mp25-pcie-ep"; + reg =3D <0x48400000 0x100000>, + <0x48500000 0x100000>, + <0x48700000 0x80000>, + <0x10000000 0x10000000>; + reg-names =3D "dbi", "dbi2", "atu", "addr_space"; + clocks =3D <&rcc CK_BUS_PCIE>; + resets =3D <&rcc PCIE_R>; + phys =3D <&combophy PHY_TYPE_PCIE>; + access-controllers =3D <&rifsc 68>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; 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charset="utf-8" Add PCIe RC and EP support on stm32mp257f-ev1 board. Default to RC mode. Signed-off-by: Christian Bruel --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 836b1958ce65..b20bff82da80 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -265,6 +265,27 @@ scmi_vdd_sdcard: regulator@23 { }; }; =20 +&pcie_ep { + pinctrl-names =3D "default", "init"; + pinctrl-0 =3D <&pcie_pins_a>; + pinctrl-1 =3D <&pcie_init_pins_a>; + reset-gpios =3D <&gpioj 8 GPIO_ACTIVE_LOW>; + status =3D "disabled"; +}; + +&pcie_rc { + pinctrl-names =3D "default", "init", "sleep"; + pinctrl-0 =3D <&pcie_pins_a>; + pinctrl-1 =3D <&pcie_init_pins_a>; + pinctrl-2 =3D <&pcie_sleep_pins_a>; + status =3D "okay"; + + pcie@0,0 { + reset-gpios =3D <&gpioj 8 GPIO_ACTIVE_LOW>; + wake-gpios =3D <&gpioh 5 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + }; +}; + &sdmmc1 { pinctrl-names =3D "default", "opendrain", "sleep"; pinctrl-0 =3D <&sdmmc1_b4_pins_a>; --=20 2.34.1