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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni Subject: [net-next Patch] Octeontx2-af: Broadcast XON on all channels Date: Wed, 20 Aug 2025 12:16:25 +0530 Message-ID: <20250820064625.1464361-1-hkelam@marvell.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: aIF4cOFPENb5x4stqJ4qKuTj_Bu-EPtX X-Proofpoint-GUID: aIF4cOFPENb5x4stqJ4qKuTj_Bu-EPtX X-Authority-Analysis: v=2.4 cv=I9E8hNgg c=1 sm=1 tr=0 ts=68a56f4f cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=2OwXVqhp2XgA:10 a=M5GUcnROAAAA:8 a=Zm5e-TsFn6k_I1Zn3SQA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 a=cPQSjfK2_nFv0Q5t_7PE:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIwMDA1NyBTYWx0ZWRfX5xFSkjaHru68 v9UdCAn5UB2zn66qoUbsImFwYVB2SrsQXPfwWudzQsdznhOL7hFuBBEAikjsYNQRpdOVqRWj+XO 8QZZ9Etffv5+Fax3QCl0eS/0GVCEIcgOuiXn7/VIgEW9hdYeNiHUKv9qifvu/XP5zVp03q0R+AI 8D4Gy4yH73wmBCf7GQL8odJyqwa2K8gqcZoXlibzbpeUqEX6EZCRK3fphvm00yU86QmgTaDQIWI UWE0w1gtXHO6Rguqtc2GA24aifLnCMI9z/FhO5oAs9nj188vEGTC+rquudzjlP98Br7AonSm2Mf C9B2qrUgxQ7fR/9zi885f4uosHHSHPa8r9+4grTtpDU7+ekCFBfRynxoHQ0cwL2v+9XoCvikS4o Um6GLql0EjKGqVGBQe2YNiVqDvZykq34Sn68+TpXpG+3l+46KZiNq2lqtYnootPrmAY84WJR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-20_03,2025-08-14_01,2025-03-28_01 Content-Type: text/plain; charset="utf-8" The NIX block receives traffic from multiple channels, including: MAC block (RPM) Loopback module (LBK) CPT block RPM | ----------------- LBK --| NIX | ----------------- | CPT Due to a hardware errata, CN10k and earlier Octeon silicon series, the hardware may incorrectly assert XOFF on certain channels during reset. As a workaround, a write operation to the NIX_AF_RX_CHANX_CFG register can be performed to broadcast XON signals on the affected channels Signed-off-by: Hariprasad Kelam --- drivers/net/ethernet/marvell/octeontx2/af/rvu.c | 3 +++ drivers/net/ethernet/marvell/octeontx2/af/rvu.h | 1 + .../net/ethernet/marvell/octeontx2/af/rvu_nix.c | 16 ++++++++++++++++ 3 files changed, 20 insertions(+) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.c index c6bb3aaa8e0d..2d78e08f985f 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.c @@ -1164,6 +1164,9 @@ static int rvu_setup_hw_resources(struct rvu *rvu) rvu_program_channels(rvu); cgx_start_linkup(rvu); =20 + rvu_block_bcast_xon(rvu, BLKADDR_NIX0); + rvu_block_bcast_xon(rvu, BLKADDR_NIX1); + err =3D rvu_mcs_init(rvu); if (err) { dev_err(rvu->dev, "%s: Failed to initialize mcs\n", __func__); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h b/drivers/net/= ethernet/marvell/octeontx2/af/rvu.h index 7ee1fdeb5295..1692033b46b0 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu.h @@ -1017,6 +1017,7 @@ int rvu_nix_mcast_update_mcam_entry(struct rvu *rvu, = u16 pcifunc, void rvu_nix_flr_free_bpids(struct rvu *rvu, u16 pcifunc); int rvu_alloc_cint_qint_mem(struct rvu *rvu, struct rvu_pfvf *pfvf, int blkaddr, int nixlf); +void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr); /* NPC APIs */ void rvu_npc_freemem(struct rvu *rvu); int rvu_npc_get_pkind(struct rvu *rvu, u16 pf); diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/= net/ethernet/marvell/octeontx2/af/rvu_nix.c index 60db1f616cc8..828316211b24 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -6616,3 +6616,19 @@ int rvu_mbox_handler_nix_mcast_grp_update(struct rvu= *rvu, =20 return ret; } + +/* On CN10k and older series of silicons, hardware may incorrectly + * assert XOFF on certain channels. Issue a write on NIX_AF_RX_CHANX_CFG + * to broadcacst XON on the same. + */ +void rvu_block_bcast_xon(struct rvu *rvu, int blkaddr) +{ + struct rvu_block *block =3D &rvu->hw->block[blkaddr]; + u64 cfg; + + if (!block->implemented || is_cn20k(rvu->pdev)) + return; + + cfg =3D rvu_read64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(0)); + rvu_write64(rvu, blkaddr, NIX_AF_RX_CHANX_CFG(0), cfg); +} --=20 2.34.1