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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Aug 2025 04:26:07.1341 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 58d2be75-3300-42cf-5808-08dddfa1aecb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B370.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS4PR12MB9817 Content-Type: text/plain; charset="utf-8" AMD IOMMU Extended Feature (EFR) and Extended Feature 2 (EFR2) registers specify features supported by each IOMMU hardware instance. The IOMMU driver checks each feature-specific bits before enabling each feature at run time. For IOMMUFD, the hypervisor determines which IOMMU features to support in the guest, and communicates this information to user-space (e.g. QEMU) via iommufd IOMMU_DEVICE_GET_HW_INFO ioctl. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 3 +++ drivers/iommu/amd/iommu.c | 40 +++++++++++++++++++++++++++++ include/uapi/linux/iommufd.h | 19 ++++++++++++++ 3 files changed, 62 insertions(+) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_io= mmu_types.h index 5219d7ddfdaa..efdd0cbda1df 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -95,9 +95,12 @@ #define FEATURE_HE BIT_ULL(8) #define FEATURE_PC BIT_ULL(9) #define FEATURE_HATS GENMASK_ULL(11, 10) +#define FEATURE_GATS_SHIFT 12 #define FEATURE_GATS GENMASK_ULL(13, 12) +#define FEATURE_GLX_SHIFT 14 #define FEATURE_GLX GENMASK_ULL(15, 14) #define FEATURE_GAM_VAPIC BIT_ULL(21) +#define FEATURE_PASMAX_SHIFT 32 #define FEATURE_PASMAX GENMASK_ULL(36, 32) #define FEATURE_GIOSUP BIT_ULL(48) #define FEATURE_HASUP BIT_ULL(49) diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c index eb348c63a8d0..ebe1cb9b0807 100644 --- a/drivers/iommu/amd/iommu.c +++ b/drivers/iommu/amd/iommu.c @@ -3038,8 +3038,48 @@ static const struct iommu_dirty_ops amd_dirty_ops = =3D { .read_and_clear_dirty =3D amd_iommu_read_and_clear_dirty, }; =20 +#define AMD_VIOMMU_EFR_GUEST_TRANSLATION_FLAGS \ + (FEATURE_GT | FEATURE_GA | FEATURE_GIOSUP | \ + FEATURE_PPR | FEATURE_EPHSUP) + +static void _build_efr_guest_translation(struct amd_iommu *iommu, u64 *efr= , u64 *efr2) +{ + /* + * Build the EFR against the current hardware capabilities + * + * Also, not all IOMMU features are emulated by KVM. + * Therefore, only advertise what KVM can support + * or virtualzied by the hardware. + */ + if (!efr) + return; + + *efr |=3D (amd_iommu_efr & AMD_VIOMMU_EFR_GUEST_TRANSLATION_FLAGS); + *efr |=3D (FIELD_GET(FEATURE_GATS, amd_iommu_efr) << FEATURE_GATS_SHIFT); + *efr |=3D (FIELD_GET(FEATURE_GLX, amd_iommu_efr) << FEATURE_GLX_SHIFT); + *efr |=3D (FIELD_GET(FEATURE_PASMAX, amd_iommu_efr) << FEATURE_PASMAX_SHI= FT); + pr_debug("%s: efr=3D%#llx\n", __func__, *efr); +} + +static void *amd_iommu_hw_info(struct device *dev, u32 *length, u32 *type) +{ + struct iommu_hw_info_amd *hwinfo; + struct amd_iommu *iommu =3D rlookup_amd_iommu(dev); + + hwinfo =3D kzalloc(sizeof(*hwinfo), GFP_KERNEL); + if (!hwinfo) + return ERR_PTR(-ENOMEM); + + *length =3D sizeof(*hwinfo); + *type =3D IOMMU_HW_INFO_TYPE_AMD; + + _build_efr_guest_translation(iommu, &hwinfo->efr, &hwinfo->efr2); + return hwinfo; +} + const struct iommu_ops amd_iommu_ops =3D { .capable =3D amd_iommu_capable, + .hw_info =3D amd_iommu_hw_info, .blocked_domain =3D &blocked_domain, .release_domain =3D &release_domain, .identity_domain =3D &identity_domain.domain, diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index c218c89e0e2e..0f7212f9e0ce 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -613,6 +613,24 @@ struct iommu_hw_info_tegra241_cmdqv { __u8 __reserved; }; =20 +/** + * struct iommu_hw_info_amd - AMD IOMMU device info + * + * @efr : Value of AMD IOMMU Extended Feature Register (EFR) + * @efr2: Value of AMD IOMMU Extended Feature 2 Register (EFR2) + * + * Please See description of these registers in the following sections of + * the AMD I/O Virtualization Technology (IOMMU) Specification. + * (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/s= pecifications/48882_IOMMU.pdf) + * + * - MMIO Offset 0030h IOMMU Extended Feature Register + * - MMIO Offset 01A0h IOMMU Extended Feature 2 Register + */ +struct iommu_hw_info_amd { + __aligned_u64 efr; + __aligned_u64 efr2; +}; + /** * enum iommu_hw_info_type - IOMMU Hardware Info Types * @IOMMU_HW_INFO_TYPE_NONE: Output by the drivers that do not report hard= ware @@ -629,6 +647,7 @@ enum iommu_hw_info_type { IOMMU_HW_INFO_TYPE_INTEL_VTD =3D 1, IOMMU_HW_INFO_TYPE_ARM_SMMUV3 =3D 2, IOMMU_HW_INFO_TYPE_TEGRA241_CMDQV =3D 3, + IOMMU_HW_INFO_TYPE_AMD =3D 4, }; =20 /** --=20 2.34.1