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Wed, 20 Aug 2025 02:49:26 -0700 (PDT) From: Neil Armstrong Date: Wed, 20 Aug 2025 11:49:22 +0200 Subject: [PATCH 1/2] arm64: dts: qcom: sm8550: switch to interrupt-cells 4 to add PPI partitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-1-a8915672e996@linaro.org> References: <20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-0-a8915672e996@linaro.org> In-Reply-To: <20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-0-a8915672e996@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=52745; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=nEvJ4fFaaqSqFMmRjXbKxL85MI6XU0ukTu5GgPzmGE4=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBopZokeMmfn+NE8knc5DgBjuxPWdu0mXZNksx6m0RN qyHyGbSJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCaKWaJAAKCRB33NvayMhJ0Y8kD/ 9QoJFhEXR3YxOnB2TbSbx0qmzLe0hdvZ/RYE1UboVE6R2Qms0wClo5nFyEYo9l60z+SigqsEUSuE1g hsV+jVsSpKLsMB1DcqteGl+lPekr3dSqTZZBLQs6xtjMYgyXCpPEyeC5cEir38dVa1VHQLOjjEif9n afNW7VbVW9Ih82qghDr6PpYruBV984c0ocnSvoenhadeuyyxq4howpvQvL0WaMbQ2NmvXvS58iNfqE 1dQ7XDjHAPfkeaaE0GxBguqdcfWzXXTlBo0CCAKlJTg9jt8yXkolwlp/pw85P+M8eA/YUNnXENp7IV bejbh7WAqlB0BmpT4vbqpyndI2D/aSuYtBHe+SUZV8B1HhtH5h4KpnBI2PGmjtt7PW1gSKqMr2kDZG e2P2gdt4FfE/gbrlrfUlWaZCJgJ1+kuFWw8hWpKW4jaOix/we+AWFwBNmSBNqLJbGrgD7X1ZwO9v3J aqcG5VjZJOrey3vauMfK0Ld27wETTA0zbGSuRuAY1dOwVz9Q3om57OtdG5C48V4rz0LvxmcIes/TF1 P4Anpodl6dY5+ckTtTBkY6kk4s+G5Bn9hzAASEoV2tk2c7REeP0NKhjZFlR1Lqtju5boQNB42P3BM1 dMZxFLDSLYngH1C7mq/lSX78RmlXsNy8939ellbl/gSp0mGh6NG/jnATXg+Q== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch to interrupt-cells =3D <4> in the GIC node to allow adding an interrupt partition map phandle as the 4th cell value for GIC_PPI interrupts. Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 580 +++++++++++++++++--------------= ---- 1 file changed, 290 insertions(+), 290 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 38d139d1dd4a994287c03d064ca01d59a11ac771..2ebe02e2ca8c03ac9b987af720c= 7ebe1cd63afec 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -399,22 +399,22 @@ memory@a0000000 { =20 pmu-a510 { compatible =3D "arm,cortex-a510-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 pmu-a710 { compatible =3D "arm,cortex-a710-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 pmu-a715 { compatible =3D "arm,cortex-a715-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 pmu-x3 { compatible =3D "arm,cortex-x3-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 psci { @@ -842,7 +842,7 @@ gcc: clock-controller@100000 { ipcc: mailbox@408000 { compatible =3D "qcom,sm8550-ipcc", "qcom,ipcc"; reg =3D <0 0x00408000 0 0x1000>; - interrupts =3D ; + interrupts =3D ; interrupt-controller; #interrupt-cells =3D <3>; #mbox-cells =3D <2>; @@ -852,18 +852,18 @@ gpi_dma2: dma-controller@800000 { compatible =3D "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells =3D <3>; reg =3D <0 0x00800000 0 0x60000>; - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - ; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; dma-channels =3D <12>; dma-channel-mask =3D <0x3e>; iommus =3D <&apps_smmu 0x436 0>; @@ -891,7 +891,7 @@ i2c8: i2c@880000 { clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c8_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -914,7 +914,7 @@ spi8: spi@880000 { reg =3D <0 0x00880000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP2_S0_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi8_data_clk>, <&qup_spi8_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -941,7 +941,7 @@ i2c9: i2c@884000 { clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c9_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -964,7 +964,7 @@ spi9: spi@884000 { reg =3D <0 0x00884000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP2_S1_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi9_data_clk>, <&qup_spi9_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -991,7 +991,7 @@ i2c10: i2c@888000 { clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c10_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1014,7 +1014,7 @@ spi10: spi@888000 { reg =3D <0 0x00888000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP2_S2_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi10_data_clk>, <&qup_spi10_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1041,7 +1041,7 @@ i2c11: i2c@88c000 { clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c11_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1064,7 +1064,7 @@ spi11: spi@88c000 { reg =3D <0 0x0088c000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP2_S3_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi11_data_clk>, <&qup_spi11_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1091,7 +1091,7 @@ i2c12: i2c@890000 { clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c12_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1114,7 +1114,7 @@ spi12: spi@890000 { reg =3D <0 0x00890000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP2_S4_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi12_data_clk>, <&qup_spi12_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1141,7 +1141,7 @@ i2c13: i2c@894000 { clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c13_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1164,7 +1164,7 @@ spi13: spi@894000 { reg =3D <0 0x00894000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP2_S5_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi13_data_clk>, <&qup_spi13_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1191,7 +1191,7 @@ uart14: serial@898000 { clocks =3D <&gcc GCC_QUPV3_WRAP2_S6_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_uart14_default>, <&qup_uart14_cts_rts>; - interrupts =3D ; + interrupts =3D ; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1209,7 +1209,7 @@ i2c15: i2c@89c000 { clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c15_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1232,7 +1232,7 @@ spi15: spi@89c000 { reg =3D <0 0x0089c000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP2_S7_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi15_data_clk>, <&qup_spi15_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS @@ -1271,7 +1271,7 @@ i2c_hub_0: i2c@980000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c0_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1292,7 +1292,7 @@ i2c_hub_1: i2c@984000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c1_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1313,7 +1313,7 @@ i2c_hub_2: i2c@988000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c2_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1334,7 +1334,7 @@ i2c_hub_3: i2c@98c000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c3_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1355,7 +1355,7 @@ i2c_hub_4: i2c@990000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c4_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1376,7 +1376,7 @@ i2c_hub_5: i2c@994000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c5_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1397,7 +1397,7 @@ i2c_hub_6: i2c@998000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c6_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1418,7 +1418,7 @@ i2c_hub_7: i2c@99c000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c7_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1439,7 +1439,7 @@ i2c_hub_8: i2c@9a0000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c8_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1460,7 +1460,7 @@ i2c_hub_9: i2c@9a4000 { <&gcc GCC_QUPV3_I2C_CORE_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&hub_i2c9_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS @@ -1478,18 +1478,18 @@ gpi_dma1: dma-controller@a00000 { compatible =3D "qcom,sm8550-gpi-dma", "qcom,sm6350-gpi-dma"; #dma-cells =3D <3>; reg =3D <0 0x00a00000 0 0x60000>; - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - ; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + ; dma-channels =3D <12>; dma-channel-mask =3D <0x1e>; iommus =3D <&apps_smmu 0xb6 0>; @@ -1520,7 +1520,7 @@ i2c0: i2c@a80000 { clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c0_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1543,7 +1543,7 @@ spi0: spi@a80000 { reg =3D <0 0x00a80000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP1_S0_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi0_data_clk>, <&qup_spi0_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1570,7 +1570,7 @@ i2c1: i2c@a84000 { clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c1_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1593,7 +1593,7 @@ spi1: spi@a84000 { reg =3D <0 0x00a84000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP1_S1_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi1_data_clk>, <&qup_spi1_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1620,7 +1620,7 @@ i2c2: i2c@a88000 { clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c2_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1643,7 +1643,7 @@ spi2: spi@a88000 { reg =3D <0 0x00a88000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP1_S2_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi2_data_clk>, <&qup_spi2_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1670,7 +1670,7 @@ i2c3: i2c@a8c000 { clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c3_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1693,7 +1693,7 @@ spi3: spi@a8c000 { reg =3D <0 0x00a8c000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP1_S3_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi3_data_clk>, <&qup_spi3_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1720,7 +1720,7 @@ i2c4: i2c@a90000 { clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c4_data_clk>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <1>; #size-cells =3D <0>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1743,7 +1743,7 @@ spi4: spi@a90000 { reg =3D <0 0x00a90000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP1_S4_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi4_data_clk>, <&qup_spi4_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1770,7 +1770,7 @@ i2c5: i2c@a94000 { clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c5_data_clk>; - interrupts =3D ; + interrupts =3D ; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1793,7 +1793,7 @@ spi5: spi@a94000 { reg =3D <0 0x00a94000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP1_S5_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi5_data_clk>, <&qup_spi5_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1820,7 +1820,7 @@ i2c6: i2c@a98000 { clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_i2c6_data_clk>; - interrupts =3D ; + interrupts =3D ; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY @@ -1843,7 +1843,7 @@ spi6: spi@a98000 { reg =3D <0 0x00a98000 0 0x4000>; clock-names =3D "se"; clocks =3D <&gcc GCC_QUPV3_WRAP1_S6_CLK>; - interrupts =3D ; + interrupts =3D ; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_spi6_data_clk>, <&qup_spi6_cs>; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS @@ -1870,7 +1870,7 @@ uart7: serial@a9c000 { clocks =3D <&gcc GCC_QUPV3_WRAP1_S7_CLK>; pinctrl-names =3D "default"; pinctrl-0 =3D <&qup_uart7_default>; - interrupts =3D ; + interrupts =3D ; interconnect-names =3D "qup-core", "qup-config"; interconnects =3D <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, @@ -1961,15 +1961,15 @@ pcie0: pcie@1c00000 { linux,pci-domain =3D <0>; num-lanes =3D <2>; =20 - interrupts =3D , - , - , - , - , - , - , - , - ; + interrupts =3D , + , + , + , + , + , + , + , + ; interrupt-names =3D "msi0", "msi1", "msi2", @@ -1981,10 +1981,10 @@ pcie0: pcie@1c00000 { "global"; #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 0x7>; - interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int= _a */ - <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map =3D <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH 0>, /* i= nt_a */ + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ =20 clocks =3D <&gcc GCC_PCIE_0_AUX_CLK>, <&gcc GCC_PCIE_0_CFG_AHB_CLK>, @@ -2122,15 +2122,15 @@ pcie1: pcie@1c08000 { linux,pci-domain =3D <1>; num-lanes =3D <2>; =20 - interrupts =3D , - , - , - , - , - , - , - , - ; + interrupts =3D , + , + , + , + , + , + , + , + ; interrupt-names =3D "msi0", "msi1", "msi2", @@ -2142,10 +2142,10 @@ pcie1: pcie@1c08000 { "global"; #interrupt-cells =3D <1>; interrupt-map-mask =3D <0 0 0 0x7>; - interrupt-map =3D <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, /* int= _a */ - <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, /* int_b */ - <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, /* int_c */ - <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; /* int_d */ + interrupt-map =3D <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH 0>, /* i= nt_a */ + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH 0>, /* int_b */ + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH 0>, /* int_c */ + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH 0>; /* int_d */ =20 clocks =3D <&gcc GCC_PCIE_1_AUX_CLK>, <&gcc GCC_PCIE_1_CFG_AHB_CLK>, @@ -2280,7 +2280,7 @@ pcie1_phy: phy@1c0e000 { cryptobam: dma-controller@1dc4000 { compatible =3D "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg =3D <0x0 0x01dc4000 0x0 0x28000>; - interrupts =3D ; + interrupts =3D ; #dma-cells =3D <1>; qcom,ee =3D <0>; qcom,num-ees =3D <4>; @@ -2327,7 +2327,7 @@ ufs_mem_hc: ufshc@1d84000 { compatible =3D "qcom,sm8550-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg =3D <0x0 0x01d84000 0x0 0x3000>; - interrupts =3D ; + interrupts =3D ; phys =3D <&ufs_mem_phy>; phy-names =3D "ufsphy"; lanes-per-direction =3D <2>; @@ -2440,7 +2440,7 @@ gpu: gpu@3d00000 { "cx_mem", "cx_dbgc"; =20 - interrupts =3D ; + interrupts =3D ; =20 iommus =3D <&adreno_smmu 0 0x0>, <&adreno_smmu 1 0x0>; @@ -2521,8 +2521,8 @@ gmu: gmu@3d6a000 { <0x0 0x0b280000 0x0 0x10000>; reg-names =3D "gmu", "rscc", "gmu_pdc"; =20 - interrupts =3D , - ; + interrupts =3D , + ; interrupt-names =3D "hfi", "gmu"; =20 clocks =3D <&gpucc GPU_CC_AHB_CLK>, @@ -2583,32 +2583,32 @@ adreno_smmu: iommu@3da0000 { reg =3D <0x0 0x03da0000 0x0 0x40000>; #iommu-cells =3D <2>; #global-interrupts =3D <1>; - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; clocks =3D <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, @@ -2633,8 +2633,8 @@ ipa: ipa@3f40000 { "ipa-shared", "gsi"; =20 - interrupts-extended =3D <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, - <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended =3D <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING 0>, + <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH 0>, <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; interrupt-names =3D "ipa", @@ -2666,7 +2666,7 @@ remoteproc_mpss: remoteproc@4080000 { compatible =3D "qcom,sm8550-mpss-pas"; reg =3D <0x0 0x04080000 0x0 0x10000>; =20 - interrupts-extended =3D <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + interrupts-extended =3D <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, @@ -2854,7 +2854,7 @@ lpass_wsa2macro: codec@6aa0000 { swr3: soundwire@6ab0000 { compatible =3D "qcom,soundwire-v2.0.0"; reg =3D <0 0x06ab0000 0 0x10000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&lpass_wsa2macro>; clock-names =3D "iface"; label =3D "WSA2"; @@ -2898,7 +2898,7 @@ lpass_rxmacro: codec@6ac0000 { swr1: soundwire@6ad0000 { compatible =3D "qcom,soundwire-v2.0.0"; reg =3D <0 0x06ad0000 0 0x10000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&lpass_rxmacro>; clock-names =3D "iface"; label =3D "RX"; @@ -2956,7 +2956,7 @@ lpass_wsamacro: codec@6b00000 { swr0: soundwire@6b10000 { compatible =3D "qcom,soundwire-v2.0.0"; reg =3D <0 0x06b10000 0 0x10000>; - interrupts =3D ; + interrupts =3D ; clocks =3D <&lpass_wsamacro>; clock-names =3D "iface"; label =3D "WSA"; @@ -2986,8 +2986,8 @@ swr0: soundwire@6b10000 { swr2: soundwire@6d30000 { compatible =3D "qcom,soundwire-v2.0.0"; reg =3D <0 0x06d30000 0 0x10000>; - interrupts =3D , - ; + interrupts =3D , + ; interrupt-names =3D "core", "wakeup"; clocks =3D <&lpass_txmacro>; clock-names =3D "iface"; @@ -3169,8 +3169,8 @@ sdhc_2: mmc@8804000 { compatible =3D "qcom,sm8550-sdhci", "qcom,sdhci-msm-v5"; reg =3D <0 0x08804000 0 0x1000>; =20 - interrupts =3D , - ; + interrupts =3D , + ; interrupt-names =3D "hc_irq", "pwr_irq"; =20 clocks =3D <&gcc GCC_SDCC2_AHB_CLK>, @@ -3225,7 +3225,7 @@ iris: video-codec@aa00000 { compatible =3D "qcom,sm8550-iris"; =20 reg =3D <0 0x0aa00000 0 0xf0000>; - interrupts =3D ; + interrupts =3D ; =20 power-domains =3D <&videocc VIDEO_CC_MVS0C_GDSC>, <&videocc VIDEO_CC_MVS0_GDSC>, @@ -3317,7 +3317,7 @@ videocc: clock-controller@aaf0000 { cci0: cci@ac15000 { compatible =3D "qcom,sm8550-cci", "qcom,msm8996-cci"; reg =3D <0 0x0ac15000 0 0x1000>; - interrupts =3D ; + interrupts =3D ; power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3350,7 +3350,7 @@ cci0_i2c1: i2c-bus@1 { cci1: cci@ac16000 { compatible =3D "qcom,sm8550-cci", "qcom,msm8996-cci"; reg =3D <0 0x0ac16000 0 0x1000>; - interrupts =3D ; + interrupts =3D ; power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3376,7 +3376,7 @@ cci1_i2c0: i2c-bus@0 { cci2: cci@ac17000 { compatible =3D "qcom,sm8550-cci", "qcom,msm8996-cci"; reg =3D <0 0x0ac17000 0 0x1000>; - interrupts =3D ; + interrupts =3D ; power-domains =3D <&camcc CAM_CC_TITAN_TOP_GDSC>; clocks =3D <&camcc CAM_CC_CAMNOC_AXI_CLK>, <&camcc CAM_CC_CPAS_AHB_CLK>, @@ -3521,24 +3521,24 @@ camss: isp@acb7000 { "vfe_lite_cphy_rx", "vfe_lite_csid"; =20 - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; interrupt-names =3D "csid0", "csid1", "csid2", @@ -3635,7 +3635,7 @@ mdss: display-subsystem@ae00000 { reg =3D <0 0x0ae00000 0 0x1000>; reg-names =3D "mdss"; =20 - interrupts =3D ; + interrupts =3D ; interrupt-controller; #interrupt-cells =3D <1>; =20 @@ -4107,9 +4107,9 @@ usb_1: usb@a600000 { <&gcc GCC_USB30_PRIM_MASTER_CLK>; assigned-clock-rates =3D <19200000>, <200000000>; =20 - interrupts-extended =3D <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + interrupts-extended =3D <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH 0>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; @@ -4192,8 +4192,8 @@ tsens0: thermal-sensor@c271000 { reg =3D <0 0x0c271000 0 0x1000>, /* TM */ <0 0x0c222000 0 0x1000>; /* SROT */ #qcom,sensors =3D <16>; - interrupts =3D , - ; + interrupts =3D , + ; interrupt-names =3D "uplow", "critical"; #thermal-sensor-cells =3D <1>; }; @@ -4203,8 +4203,8 @@ tsens1: thermal-sensor@c272000 { reg =3D <0 0x0c272000 0 0x1000>, /* TM */ <0 0x0c223000 0 0x1000>; /* SROT */ #qcom,sensors =3D <16>; - interrupts =3D , - ; + interrupts =3D , + ; interrupt-names =3D "uplow", "critical"; #thermal-sensor-cells =3D <1>; }; @@ -4214,8 +4214,8 @@ tsens2: thermal-sensor@c273000 { reg =3D <0 0x0c273000 0 0x1000>, /* TM */ <0 0x0c224000 0 0x1000>; /* SROT */ #qcom,sensors =3D <16>; - interrupts =3D , - ; + interrupts =3D , + ; interrupt-names =3D "uplow", "critical"; #thermal-sensor-cells =3D <1>; }; @@ -4259,7 +4259,7 @@ spmi_bus: spmi@c400000 { tlmm: pinctrl@f100000 { compatible =3D "qcom,sm8550-tlmm"; reg =3D <0 0x0f100000 0 0x300000>; - interrupts =3D ; + interrupts =3D ; gpio-controller; #gpio-cells =3D <2>; interrupt-controller; @@ -4953,103 +4953,103 @@ apps_smmu: iommu@15000000 { reg =3D <0 0x15000000 0 0x100000>; #iommu-cells =3D <2>; #global-interrupts =3D <1>; - interrupts =3D , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; dma-coherent; }; =20 @@ -5058,11 +5058,11 @@ intc: interrupt-controller@17100000 { reg =3D <0 0x17100000 0 0x10000>, /* GICD */ <0 0x17180000 0 0x200000>; /* GICR * 8 */ ranges; - #interrupt-cells =3D <3>; + #interrupt-cells =3D <4>; interrupt-controller; #redistributor-regions =3D <1>; redistributor-stride =3D <0 0x40000>; - interrupts =3D ; + interrupts =3D ; #address-cells =3D <2>; #size-cells =3D <2>; =20 @@ -5085,49 +5085,49 @@ frame@17421000 { reg =3D <0x17421000 0x1000>, <0x17422000 0x1000>; frame-number =3D <0>; - interrupts =3D , - ; + interrupts =3D , + ; }; =20 frame@17423000 { reg =3D <0x17423000 0x1000>; frame-number =3D <1>; - interrupts =3D ; + interrupts =3D ; status =3D "disabled"; }; =20 frame@17425000 { reg =3D <0x17425000 0x1000>; frame-number =3D <2>; - interrupts =3D ; + interrupts =3D ; status =3D "disabled"; }; =20 frame@17427000 { reg =3D <0x17427000 0x1000>; frame-number =3D <3>; - interrupts =3D ; + interrupts =3D ; status =3D "disabled"; }; =20 frame@17429000 { reg =3D <0x17429000 0x1000>; frame-number =3D <4>; - interrupts =3D ; + interrupts =3D ; status =3D "disabled"; }; =20 frame@1742b000 { reg =3D <0x1742b000 0x1000>; frame-number =3D <5>; - interrupts =3D ; + interrupts =3D ; status =3D "disabled"; }; =20 frame@1742d000 { reg =3D <0x1742d000 0x1000>; frame-number =3D <6>; - interrupts =3D ; + interrupts =3D ; status =3D "disabled"; }; }; @@ -5140,9 +5140,9 @@ apps_rsc: rsc@17a00000 { <0 0x17a20000 0 0x10000>, <0 0x17a30000 0 0x10000>; reg-names =3D "drv-0", "drv-1", "drv-2", "drv-3"; - interrupts =3D , - , - ; + interrupts =3D , + , + ; qcom,tcs-offset =3D <0xd00>; qcom,drv-id =3D <2>; qcom,tcs-config =3D , , @@ -5239,9 +5239,9 @@ cpufreq_hw: cpufreq@17d91000 { reg-names =3D "freq-domain0", "freq-domain1", "freq-domain2"; clocks =3D <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; clock-names =3D "xo", "alternate"; - interrupts =3D , - , - ; + interrupts =3D , + , + ; interrupt-names =3D "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells =3D <1>; #clock-cells =3D <1>; @@ -5250,7 +5250,7 @@ cpufreq_hw: cpufreq@17d91000 { pmu@24091000 { compatible =3D "qcom,sm8550-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; reg =3D <0 0x24091000 0 0x1000>; - interrupts =3D ; + interrupts =3D ; interconnects =3D <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; =20 @@ -5300,7 +5300,7 @@ opp-8 { pmu@240b6400 { compatible =3D "qcom,sm8550-cpu-bwmon", "qcom,sdm845-bwmon"; reg =3D <0 0x240b6400 0 0x600>; - interrupts =3D ; + interrupts =3D ; interconnects =3D <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; =20 @@ -5356,7 +5356,7 @@ system-cache-controller@25000000 { "llcc3_base", "llcc_broadcast_base", "llcc_broadcast_and_base"; - interrupts =3D ; + interrupts =3D ; }; =20 nsp_noc: interconnect@320c0000 { @@ -5370,7 +5370,7 @@ remoteproc_cdsp: remoteproc@32300000 { compatible =3D "qcom,sm8550-cdsp-pas"; reg =3D <0x0 0x32300000 0x0 0x10000>; =20 - interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + interrupts-extended =3D <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING 0>, <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, @@ -6552,9 +6552,9 @@ trip-point2 { =20 timer { compatible =3D "arm,armv8-timer"; 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Wed, 20 Aug 2025 02:49:26 -0700 (PDT) From: Neil Armstrong Date: Wed, 20 Aug 2025 11:49:23 +0200 Subject: [PATCH 2/2] arm64: dts: qcom: sm8550: add PPI interrupt partitions for the ARM PMUs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-2-a8915672e996@linaro.org> References: <20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-0-a8915672e996@linaro.org> In-Reply-To: <20250820-topic-sm8550-upstream-pmu-ppi-4-cells-v1-0-a8915672e996@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2039; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=L1WblGj94ZaDL048pCEw1KwCIcqYN2hMDRmKDSs9uaA=; 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Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qco= m/sm8550.dtsi index 2ebe02e2ca8c03ac9b987af720c7ebe1cd63afec..1b7fbbdba2df986e1efca5dbfa3= 6c01eb1be0836 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -399,22 +399,22 @@ memory@a0000000 { =20 pmu-a510 { compatible =3D "arm,cortex-a510-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 pmu-a710 { compatible =3D "arm,cortex-a710-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 pmu-a715 { compatible =3D "arm,cortex-a715-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 pmu-x3 { compatible =3D "arm,cortex-x3-pmu"; - interrupts =3D ; + interrupts =3D ; }; =20 psci { @@ -5066,6 +5066,24 @@ intc: interrupt-controller@17100000 { #address-cells =3D <2>; #size-cells =3D <2>; =20 + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity =3D <&cpu0 &cpu1 &cpu2>; + }; + + ppi_cluster1: interrupt-partition-1 { + affinity =3D <&cpu3 &cpu4>; + }; + + ppi_cluster2: interrupt-partition-2 { + affinity =3D <&cpu5 &cpu6>; + }; + + ppi_cluster3: interrupt-partition-3 { + affinity =3D <&cpu7>; + }; + }; + gic_its: msi-controller@17140000 { compatible =3D "arm,gic-v3-its"; reg =3D <0 0x17140000 0 0x20000>; --=20 2.34.1