From nobody Sat Oct 4 03:17:49 2025 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9DA7525B31D; Wed, 20 Aug 2025 17:41:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755711666; cv=none; b=hwrmJuGV4Y0xqPoVqhxvVT/W1nYMYF/c1F2+sfu2QNqfxyzkV1BL7WaDKOe1HYYVHBp/d3ubBVkt2UFjdaNp6KuL4mwdvg8V4eo8c9DjRGcFC/DMnyj+htljlii9ROURukxb3dd7qMlWGN9NzZ2sESjRY2WmYAXCTSBOt1s+msU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755711666; c=relaxed/simple; bh=CXhcwvZlSopAbL/fzdt9Z5pqnhV9bGyubMCozha3/tk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OQX1JvFR/v5m+2hvXDS8OEfW9YnBfJjZPoqeYXYzt04FlMlWOGCWUxR1QMMnaQkIoaxnmNPgXW1Jl00sDL/Dwvuiwzcl5trQSfBwSt0KSLeHrvyYrj3/yBhMMaZsGjUpUFAmcbiH1/fbEXRWAPFGNvy/a7+5rfUeHdwmrLnFQ8Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QLp6YNsV; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QLp6YNsV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1755711657; bh=CXhcwvZlSopAbL/fzdt9Z5pqnhV9bGyubMCozha3/tk=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QLp6YNsVbhv+tfZ/N25WieK+Bp9PyQTTAE80dGT39VbbOAyU8qiiedyx5a4xfuRzY cZpTHY3Zr+FvbCaDnCzrnYKajqesngTurxw/Nf5Ff3stYlTxzKmoRlPyLv1r5bbgjs 6tf+lkbxZsU73m893B5KZNFVnawWxuDGtb2VAb0CQYyoc8kfqK74J1FdWqkyJ/ouxG ZQM1bGSqxj7MOD5dToSWxxnKQiEcUeplF5jbCCKzGuEev4HaEQlKz4SJl3qKNu0+ZM E8d7Mz8rMLkbi4NBZi4r4zKtu0HnfmIs4cyB928umXiwB6/8ZlS7iMVH7gEUPVto6m HJOk6eKUjWN/Q== Received: from jupiter.universe (dyndsl-091-248-213-114.ewe-ip-backbone.de [91.248.213.114]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) (Authenticated sender: sre) by bali.collaboradmins.com (Postfix) with ESMTPSA id 016B017E12FF; Wed, 20 Aug 2025 19:40:57 +0200 (CEST) Received: by jupiter.universe (Postfix, from userid 1000) id A4BD8480041; Wed, 20 Aug 2025 19:40:56 +0200 (CEST) From: Sebastian Reichel Date: Wed, 20 Aug 2025 19:40:47 +0200 Subject: [PATCH v2 1/3] thermal: rockchip: unify struct rockchip_tsadc_chip format Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-thermal-rockchip-grf-warning-v2-1-c7e2d35017b8@kernel.org> References: <20250820-thermal-rockchip-grf-warning-v2-0-c7e2d35017b8@kernel.org> In-Reply-To: <20250820-thermal-rockchip-grf-warning-v2-0-c7e2d35017b8@kernel.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Robin Murphy , Diederik de Haas , linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7215; i=sre@kernel.org; h=from:subject:message-id; bh=CXhcwvZlSopAbL/fzdt9Z5pqnhV9bGyubMCozha3/tk=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGimCKgHMa7MUGksYzbMAXCgjqNcDH/x+phfq flZ+YuS9XSWQ4kCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJopgioAAoJENju1/PI O/qaTe4QAJyLFIErw0hULWNuAzcMfVyHGfNvHkyPeZLYmoNOKRKJiTFMIF2U4FRsxbK2av08daT A0OtTykG9BYRAZMAoSFO1DNY7MdeGQ68D1l/ILiWFRXHG9qOjudrZCDWyt+8HzFukj30Z5CDxwl ZfpY5+EH9yXVIhhDMutG1RyRZnwjjgd95Y1LsKbVvpDvn86dM6wrwBP+DrE24qgtEL3XQkrrQBO SLfmSzTKnXKOwjPBetV3t6gN+MXcIFO74yJ8/iHYwpUwTf59ljczcy1mTT4kiAlLI3dZgmQ6Vvm ajcAd7bAYMiNkr72GnYD8PLrz9snpNvxCJLb7HS7UA/+8ONxcZtge0+E0QsuHz176xgmzdkoE7d 362labJ3YeSJdL9uhZUo9l2zA6fZU7QvDKzrxTIFvFyp/+vlAgbXRoFmVSfa3mg63HBEp7sq7Vf +jDe3XvlCQlOPrD0t/mv4DlnWAwLSr+pa26sYzLhPrsoAGMO3LBn3AzQXSf8m9QGVZS4CBQtK6N spEBWvLQUfgkR8cqat1fon/3ET/Q+K5DHJshvShJxFNWRfVi3zQoemwc4QFrMt2EHShV8HHZ5AO GMHX1nWXjvtpWm2qCnabosr0BtV0BDPxvL6DymkxrHGbszVHbNoXPK2ELaK/oPtJRdFPYV/G7cA ajXSK7xc2tdbiCqng3nw1Og== X-Developer-Key: i=sre@kernel.org; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Unify all chip descriptions to the version without any empty lines. Suggested-by: Heiko Stuebner Signed-off-by: Sebastian Reichel Reviewed-by: Dragan Simic --- drivers/thermal/rockchip_thermal.c | 27 --------------------------- 1 file changed, 27 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 3beff9b6fac3abe8948b56132b618ff1bed57217..7b18a705dfade6fa7318b28c2b5= 7544a4446c1cc 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -1098,10 +1098,8 @@ static const struct rockchip_tsadc_chip px30_tsadc_d= ata =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* 2 channels for tsadc */ - .tshut_mode =3D TSHUT_MODE_CRU, /* default TSHUT via CRU */ .tshut_temp =3D 95000, - .initialize =3D rk_tsadcv4_initialize, .irq_ack =3D rk_tsadcv3_irq_ack, .control =3D rk_tsadcv3_control, @@ -1109,7 +1107,6 @@ static const struct rockchip_tsadc_chip px30_tsadc_da= ta =3D { .set_alarm_temp =3D rk_tsadcv2_alarm_temp, .set_tshut_temp =3D rk_tsadcv2_tshut_temp, .set_tshut_mode =3D rk_tsadcv2_tshut_mode, - .table =3D { .id =3D rk3328_code_table, .length =3D ARRAY_SIZE(rk3328_code_table), @@ -1122,11 +1119,9 @@ static const struct rockchip_tsadc_chip rv1108_tsadc= _data =3D { /* cpu */ .chn_offset =3D 0, .chn_num =3D 1, /* one channel for tsadc */ - .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, - .initialize =3D rk_tsadcv2_initialize, .irq_ack =3D rk_tsadcv3_irq_ack, .control =3D rk_tsadcv3_control, @@ -1134,7 +1129,6 @@ static const struct rockchip_tsadc_chip rv1108_tsadc_= data =3D { .set_alarm_temp =3D rk_tsadcv2_alarm_temp, .set_tshut_temp =3D rk_tsadcv2_tshut_temp, .set_tshut_mode =3D rk_tsadcv2_tshut_mode, - .table =3D { .id =3D rv1108_table, .length =3D ARRAY_SIZE(rv1108_table), @@ -1147,11 +1141,9 @@ static const struct rockchip_tsadc_chip rk3228_tsadc= _data =3D { /* cpu */ .chn_offset =3D 0, .chn_num =3D 1, /* one channel for tsadc */ - .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, - .initialize =3D rk_tsadcv2_initialize, .irq_ack =3D rk_tsadcv3_irq_ack, .control =3D rk_tsadcv3_control, @@ -1159,7 +1151,6 @@ static const struct rockchip_tsadc_chip rk3228_tsadc_= data =3D { .set_alarm_temp =3D rk_tsadcv2_alarm_temp, .set_tshut_temp =3D rk_tsadcv2_tshut_temp, .set_tshut_mode =3D rk_tsadcv2_tshut_mode, - .table =3D { .id =3D rk3228_code_table, .length =3D ARRAY_SIZE(rk3228_code_table), @@ -1172,11 +1163,9 @@ static const struct rockchip_tsadc_chip rk3288_tsadc= _data =3D { /* cpu, gpu */ .chn_offset =3D 1, .chn_num =3D 2, /* two channels for tsadc */ - .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, - .initialize =3D rk_tsadcv2_initialize, .irq_ack =3D rk_tsadcv2_irq_ack, .control =3D rk_tsadcv2_control, @@ -1184,7 +1173,6 @@ static const struct rockchip_tsadc_chip rk3288_tsadc_= data =3D { .set_alarm_temp =3D rk_tsadcv2_alarm_temp, .set_tshut_temp =3D rk_tsadcv2_tshut_temp, .set_tshut_mode =3D rk_tsadcv2_tshut_mode, - .table =3D { .id =3D rk3288_code_table, .length =3D ARRAY_SIZE(rk3288_code_table), @@ -1197,10 +1185,8 @@ static const struct rockchip_tsadc_chip rk3328_tsadc= _data =3D { /* cpu */ .chn_offset =3D 0, .chn_num =3D 1, /* one channels for tsadc */ - .tshut_mode =3D TSHUT_MODE_CRU, /* default TSHUT via CRU */ .tshut_temp =3D 95000, - .initialize =3D rk_tsadcv2_initialize, .irq_ack =3D rk_tsadcv3_irq_ack, .control =3D rk_tsadcv3_control, @@ -1208,7 +1194,6 @@ static const struct rockchip_tsadc_chip rk3328_tsadc_= data =3D { .set_alarm_temp =3D rk_tsadcv2_alarm_temp, .set_tshut_temp =3D rk_tsadcv2_tshut_temp, .set_tshut_mode =3D rk_tsadcv2_tshut_mode, - .table =3D { .id =3D rk3328_code_table, .length =3D ARRAY_SIZE(rk3328_code_table), @@ -1221,11 +1206,9 @@ static const struct rockchip_tsadc_chip rk3366_tsadc= _data =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ - .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, - .initialize =3D rk_tsadcv3_initialize, .irq_ack =3D rk_tsadcv3_irq_ack, .control =3D rk_tsadcv3_control, @@ -1233,7 +1216,6 @@ static const struct rockchip_tsadc_chip rk3366_tsadc_= data =3D { .set_alarm_temp =3D rk_tsadcv2_alarm_temp, .set_tshut_temp =3D rk_tsadcv2_tshut_temp, .set_tshut_mode =3D rk_tsadcv2_tshut_mode, - .table =3D { .id =3D rk3228_code_table, .length =3D ARRAY_SIZE(rk3228_code_table), @@ -1246,11 +1228,9 @@ static const struct rockchip_tsadc_chip rk3368_tsadc= _data =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ - .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, - .initialize =3D rk_tsadcv2_initialize, .irq_ack =3D rk_tsadcv2_irq_ack, .control =3D rk_tsadcv2_control, @@ -1258,7 +1238,6 @@ static const struct rockchip_tsadc_chip rk3368_tsadc_= data =3D { .set_alarm_temp =3D rk_tsadcv2_alarm_temp, .set_tshut_temp =3D rk_tsadcv2_tshut_temp, .set_tshut_mode =3D rk_tsadcv2_tshut_mode, - .table =3D { .id =3D rk3368_code_table, .length =3D ARRAY_SIZE(rk3368_code_table), @@ -1271,11 +1250,9 @@ static const struct rockchip_tsadc_chip rk3399_tsadc= _data =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ - .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, - .initialize =3D rk_tsadcv3_initialize, .irq_ack =3D rk_tsadcv3_irq_ack, .control =3D rk_tsadcv3_control, @@ -1283,7 +1260,6 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_= data =3D { .set_alarm_temp =3D rk_tsadcv2_alarm_temp, .set_tshut_temp =3D rk_tsadcv2_tshut_temp, .set_tshut_mode =3D rk_tsadcv2_tshut_mode, - .table =3D { .id =3D rk3399_code_table, .length =3D ARRAY_SIZE(rk3399_code_table), @@ -1296,11 +1272,9 @@ static const struct rockchip_tsadc_chip rk3568_tsadc= _data =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ - .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, - 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Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Robin Murphy , Diederik de Haas , linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5959; i=sre@kernel.org; h=from:subject:message-id; bh=cv/HvJA3SdPGsRxB/T+jdV8EVtU5USfUusiJ3NtOEdA=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGimCKhZB2Qy/66UnTyJwTNkprOFtM351AXBX MeqRJwywrIjnokCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJopgioAAoJENju1/PI O/qapPMQAJ4AIB5czKPJT5zpXcir8OrTbNePX5Pa6EvaYMwXm1kTybwSx0Rsq/TpIqj7Sq8UV0Y ycI8O4/2RMNoyIlL0qsQBq+MXhKW8lVrtnIhO2JIPBGc+HlO7zDym7YgatR8lQWvn9ScFfqr/zc PROvFlNKInk7oeK8tfJdhTkJoNTxI7Uo3RLGct8VKwjvRxa+z0Cj7cpYMj8haB5Af6cVsIidq8T JxYS+RSJorssph5nphREzyz3IxKhC44lLV2WeZ7qWzr8w2WLS2y0aEnF/xrN+RKeJ+aLvO2i7fb 3+DRyoayJEzM7AlUpsWnFw4Njk81AOLHXz1erb0AMA57h8qRftRN5pmnRwI8ed7kOZ5nkB5Wm0n qMz13GLorkTSKIA+0KfGTfvo8E9t9Rtd3PpZ3V7WaJucKOcq5BaRdnWiIBcHSkaU2I7LtFm6a7T EQDMRHWcOeLC8tMMZPxJDoel2LD8Z41S7BrgwO078mi95pDGAKg4xNvbMlKFzxgSEkY22gJqDX3 I6Y0Mds5ZaFxzylFWohNWC2RRMrxHNXlCBQpueP1No2RpyG62y3J1G3+PgN7D9MbpRTDXx5lyPM ztVQOp2+QLlNCwDtncwEXuAP3g5OYqj1QTreyV+TkDBAp9/Nfyvn2Zt0hnX+sBSYHM982/YSFXq WSO4F0EOqBEIRDr3gp7Msaw== X-Developer-Key: i=sre@kernel.org; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Most of the recent Rockchip devices do not have a GRF associated with the tsadc IP. Let's avoid printing a warning on those devices. Signed-off-by: Sebastian Reichel Reviewed-by: Dragan Simic Tested-by: Diederik de Haas --- drivers/thermal/rockchip_thermal.c | 23 ++++++++++++++++++----- 1 file changed, 18 insertions(+), 5 deletions(-) diff --git a/drivers/thermal/rockchip_thermal.c b/drivers/thermal/rockchip_= thermal.c index 7b18a705dfade6fa7318b28c2b57544a4446c1cc..c49ddf70f86e7beaf0190b1b3e9= 3f5e6b2f72b2c 100644 --- a/drivers/thermal/rockchip_thermal.c +++ b/drivers/thermal/rockchip_thermal.c @@ -74,6 +74,7 @@ struct chip_tsadc_table { * @tshut_temp: the hardware-controlled shutdown temperature value, with n= o trim * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO) * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH) + * @grf_required: true, if a GRF is required for proper functionality * @initialize: SoC special initialize tsadc controller method * @irq_ack: clear the interrupt * @control: enable/disable method for the tsadc controller @@ -97,6 +98,9 @@ struct rockchip_tsadc_chip { enum tshut_mode tshut_mode; enum tshut_polarity tshut_polarity; =20 + /* GRF availability */ + bool grf_required; + /* Chip-wide methods */ void (*initialize)(struct regmap *grf, void __iomem *reg, enum tshut_polarity p); @@ -1098,6 +1102,7 @@ static const struct rockchip_tsadc_chip px30_tsadc_da= ta =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* 2 channels for tsadc */ + .grf_required =3D true, .tshut_mode =3D TSHUT_MODE_CRU, /* default TSHUT via CRU */ .tshut_temp =3D 95000, .initialize =3D rk_tsadcv4_initialize, @@ -1119,6 +1124,7 @@ static const struct rockchip_tsadc_chip rv1108_tsadc_= data =3D { /* cpu */ .chn_offset =3D 0, .chn_num =3D 1, /* one channel for tsadc */ + .grf_required =3D false, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1141,6 +1147,7 @@ static const struct rockchip_tsadc_chip rk3228_tsadc_= data =3D { /* cpu */ .chn_offset =3D 0, .chn_num =3D 1, /* one channel for tsadc */ + .grf_required =3D false, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1163,6 +1170,7 @@ static const struct rockchip_tsadc_chip rk3288_tsadc_= data =3D { /* cpu, gpu */ .chn_offset =3D 1, .chn_num =3D 2, /* two channels for tsadc */ + .grf_required =3D false, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1185,6 +1193,7 @@ static const struct rockchip_tsadc_chip rk3328_tsadc_= data =3D { /* cpu */ .chn_offset =3D 0, .chn_num =3D 1, /* one channels for tsadc */ + .grf_required =3D false, .tshut_mode =3D TSHUT_MODE_CRU, /* default TSHUT via CRU */ .tshut_temp =3D 95000, .initialize =3D rk_tsadcv2_initialize, @@ -1206,6 +1215,7 @@ static const struct rockchip_tsadc_chip rk3366_tsadc_= data =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ + .grf_required =3D true, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1228,6 +1238,7 @@ static const struct rockchip_tsadc_chip rk3368_tsadc_= data =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ + .grf_required =3D false, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1250,6 +1261,7 @@ static const struct rockchip_tsadc_chip rk3399_tsadc_= data =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ + .grf_required =3D true, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1272,6 +1284,7 @@ static const struct rockchip_tsadc_chip rk3568_tsadc_= data =3D { /* cpu, gpu */ .chn_offset =3D 0, .chn_num =3D 2, /* two channels for tsadc */ + .grf_required =3D true, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1294,6 +1307,7 @@ static const struct rockchip_tsadc_chip rk3576_tsadc_= data =3D { /* top, big_core, little_core, ddr, npu, gpu */ .chn_offset =3D 0, .chn_num =3D 6, /* six channels for tsadc */ + .grf_required =3D false, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1318,6 +1332,7 @@ static const struct rockchip_tsadc_chip rk3588_tsadc_= data =3D { /* top, big_core0, big_core1, little_core, center, gpu, npu */ .chn_offset =3D 0, .chn_num =3D 7, /* seven channels for tsadc */ + .grf_required =3D false, .tshut_mode =3D TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */ .tshut_polarity =3D TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */ .tshut_temp =3D 95000, @@ -1594,12 +1609,10 @@ static int rockchip_configure_from_dt(struct device= *dev, return -EINVAL; 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Wed, 20 Aug 2025 19:40:56 +0200 (CEST) From: Sebastian Reichel Date: Wed, 20 Aug 2025 19:40:49 +0200 Subject: [PATCH v2 3/3] dt-bindings: thermal: rockchip: tighten grf requirements Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-thermal-rockchip-grf-warning-v2-3-c7e2d35017b8@kernel.org> References: <20250820-thermal-rockchip-grf-warning-v2-0-c7e2d35017b8@kernel.org> In-Reply-To: <20250820-thermal-rockchip-grf-warning-v2-0-c7e2d35017b8@kernel.org> To: "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Robin Murphy , Diederik de Haas , linux-pm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, kernel@collabora.com, Sebastian Reichel X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1270; i=sre@kernel.org; h=from:subject:message-id; bh=Au5yTrQB84jFwkCOgmGw2+Tw7pL8gxb6s+o7q0BYyIc=; b=owJ4nAFtApL9kA0DAAoB2O7X88g7+poByyZiAGimCKhlGYYCe/U2tChbQRkiLHhxGSQ6BpBxa WOuv5ACEVPMEokCMwQAAQoAHRYhBO9mDQdGP4tyanlUE9ju1/PIO/qaBQJopgioAAoJENju1/PI O/qaM+sP/2Nn0diaMf83Q0cmf1E57OtX4JtDr8KsLopYMbzIygSUE/y+C2k2HaGN/oHpW8+feyD lUZoaaLnjUrf00HmIWJZwgvWRzwuOjkm0M+e+N0MWJfZVjDoYQ1ROkqQ76yKOGk8XyNxO/THwze T3xoZZHZrmeTzdopWbt5UGoqoy0tyD5S96w3R0eSIGEaXrAxPoTMH+9Q7wx60YNrVHQbsHO3S26 UMDo1NUOqpFNBeX6SARmZey2cak/yWjt0jNER6eCXZJJPmocwXhpBSO2JX+9ouGmIt9N/qEQSh0 l7f44DzCaRNOjYsfJx2E4e7EkQ35VQY9jdvybQ7Yu9dc8SFiNDJyT4YZ3zQbeXcENVpgxj8LdlN vKgfAnvWNjzFEnbf+MiFOOJH1C6oO2VlxRWVtoiIf+qOfA1exal5+ImohIBEtK+WHlDyE2wg8Kz HycDZwMDTm6GPMI65Cgcvn/JgBVPDQWVOX9B0eDErChUxwI6Ls4bDJeyv/YrnWKZqNmz4iroEtD qI5Ghzp44gJdFi4W+x3Z6mlDq0vprB06MDgRMEa58+L1eIbq+LTcOLkI3s+JdqPQd+NZ1iHSWrR +c0vP416yo52o09HMPJD6AAXeZhpzIl5WFP5E9zKNGwqvVfqfTjQ88Dt/+P1L4+gJOHEpb3R8E9 D/tf6TQDQez0tL2uz1t4qkg== X-Developer-Key: i=sre@kernel.org; a=openpgp; fpr=EF660D07463F8B726A795413D8EED7F3C83BFA9A Instead of having an optional rockchip,grf property, forbid using it on platforms without registers in a GRF being needed for thermal monitoring and make it mandatory on the platforms actually needing it. Signed-off-by: Sebastian Reichel Acked-by: Conor Dooley Reviewed-by: Dragan Simic --- .../devicetree/bindings/thermal/rockchip-thermal.yaml | 15 +++++++++++= ++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yam= l b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index 573f447cc26ed7100638277598b0e745d436fd01..9fa5c4c49d76e3a689f31797875= 124e7fb30d3df 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -119,6 +119,21 @@ required: - resets =20 allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-tsadc + - rockchip,rk3366-tsadc + - rockchip,rk3399-tsadc + - rockchip,rk3568-tsadc + then: + required: + - rockchip,grf + else: + properties: + rockchip,grf: false - if: not: properties: --=20 2.50.1