From nobody Sat Oct 4 03:17:09 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 026C0321F58 for ; Wed, 20 Aug 2025 13:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; cv=none; b=nmWjNiNB+DeYRjG5DIskKQ/F3qmhjLDDUOLKePAG2eZSpLSLqgBQ8G/rs7nvCfbPu2M6IYeC6o2Uylp4E8Ibj5uD4LnZU+fFBY8YqxAEgK2A4q8SUGm/3opdcCw4DM61wnJNBXjmnkOUryXoOvNjo1BGNS8fqmrO/qhNh2EK9OM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; c=relaxed/simple; bh=BEifChlpfU0M076HlGeRnhxqkcPP9GmalCnVSG1+o9w=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=gMzpmt20YErW0tk0ykS5EG6Vdp7gJXtHz6wM2oY/RX9+aWzsjuu+U0FWxd02FC9pvQB3B/b4b5NGa5u8t1Q4jSlmDdp0T+xibZEtRpvNzHx5sk3X82m6eLxE+QIYfv7umCeuGPdZJAHc71Cw0kLJU7b0PeulKZXToQy6N3iszu8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.87.235]) by APP-01 (Coremail) with SMTP id qwCowABHN6tT0aVogOTBDQ--.24665S3; Wed, 20 Aug 2025 21:44:52 +0800 (CST) From: Vivian Wang Date: Wed, 20 Aug 2025 21:44:45 +0800 Subject: [PATCH 1/6] riscv: Introduce use_alternative_{likely,unlikely} Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-riscv-altn-helper-wip-v1-1-c3c626c1f7e6@iscas.ac.cn> References: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> In-Reply-To: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes Cc: Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Ayd=C4=B1n_Mercan?= X-Mailer: b4 0.14.2 X-CM-TRANSID: qwCowABHN6tT0aVogOTBDQ--.24665S3 X-Coremail-Antispam: 1UD129KBjvJXoWxAr4fWF4rXw45Ar43JF1UKFg_yoW5Ww4UpF s3Ga45AFZ5G3WIyF9xZw1qqr4Yk3yfK3sxXasxKF1jka1jy3yrtr18Jr4Yvr9rA3sxWry7 JFn7t3W8C3WjkFJanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmj14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1le2I2 62IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcV AFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG 0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI 1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_ Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17 CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0 I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I 8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsGvfC2Kfnx nUUI43ZEXa7VUjnXo7UUUUU== X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Introduce convenience helpers use_alternative_likely() and use_alternative_unlikely() to implement the pattern of using asm goto to check if an alternative is selected. Existing code will be converted in subsequent patches. Similar to arm64 alternative_has_cap_{likely,unlikely}, but for riscv, alternatives are not all CPU capabilities. Suggested-by: Ayd=C4=B1n Mercan Signed-off-by: Vivian Wang --- arch/riscv/include/asm/alternative-macros.h | 73 +++++++++++++++++++++++++= ++++ 1 file changed, 73 insertions(+) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/inclu= de/asm/alternative-macros.h index 231d777d936c2d29c858decaa9a3fa5f172efbb8..be9835b5e4eba03d76db3a73da1= 9ac9e2981c4db 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -158,4 +158,77 @@ _ALTERNATIVE_CFG_2(old_content, new_content_1, vendor_id_1, patch_id_1, C= ONFIG_k_1, \ new_content_2, vendor_id_2, patch_id_2, CONFIG_k_2) =20 +/* + * use_alternative_{likely,unlikely}() returns true if the alternative is + * applied and false otherwise, but in a way where the compiler can optimi= ze + * this check down to a nop instruction that's patched into a jump, or vice + * versa. + * + * Always returns false if the alternatives mechanism is not available. + * + * Usage example: + * if (use_alternative_likely(0, RISCV_ISA_ZBB)) + * + * Similar to static keys, "likely" means use a nop if the alternative is + * selected, and jump if unselected; "unlikely" is the other way around. + */ + +#ifndef __ASSEMBLER__ + +#include + +#ifdef CONFIG_RISCV_ALTERNATIVE + +static __always_inline bool use_alternative_likely(u16 vendor_id, u32 patc= h_id) +{ + BUILD_BUG_ON(!__builtin_constant_p(vendor_id)); + BUILD_BUG_ON(!__builtin_constant_p(patch_id)); + + asm goto(ALTERNATIVE("j %l[no_alt]", "nop", %[vendor_id], %[patch_id], 1) + : + : [vendor_id] "i"(vendor_id), + [patch_id] "i"(patch_id) + : + : no_alt); + + return true; + +no_alt: + return false; +} + +static __always_inline bool use_alternative_unlikely(u16 vendor_id, u32 pa= tch_id) +{ + BUILD_BUG_ON(!__builtin_constant_p(vendor_id)); + BUILD_BUG_ON(!__builtin_constant_p(patch_id)); + + asm goto(ALTERNATIVE("nop", "j %l[alt]", %[vendor_id], %[patch_id], 1) + : + : [vendor_id] "i"(vendor_id), + [patch_id] "i"(patch_id) + : + : alt); + + return false; + +alt: + return true; +} + +#else + +static inline bool use_alternative_likely(u16 vendor_id, u32 patch_id) +{ + return false; +} + +static inline bool use_alternative_unlikely(u16 vendor_id, u32 patch_id) +{ + return false; +} + +#endif /* CONFIG_RISCV_ALTERNATIVE */ + +#endif /* __ASSEMBLER__ */ + #endif --=20 2.50.1 From nobody Sat Oct 4 03:17:09 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02750321F59 for ; Wed, 20 Aug 2025 13:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; cv=none; b=ow2dI345D61gcsB6OKm8jhi9craVMZcnXjoKp3yDD4sX4CSFmgWamxeBI6tg/dWP3x8I3sFNBLYOfo4ujI2cxR5dH944PouYXmA1ZaRmKZD3Etc2uKrLHbC91Ug8i4ntg+127UMlMXUGxgDkDa5JWtSil9RvtFLZ8L9bfCZ7VYs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; c=relaxed/simple; bh=UaCKawQeo4rcaFjHfUPRvD0w2sJMwd20/syfhFSKKaA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=TvE0ixoq1q+5xmNDGHRItusThIy88JrTBs+RMhCEKQFbxpsdi8C9bfxLm3l77ZitQPcjOzeYza3tKOhvZ2eBTQ7CVeKE+k0Ai3f94ar84KHaFFb8RK1yv8P9VTs6LB4Vvdlhc+Wc7SRKYzhgFOCqe7YRFmMcxLFwRbh5HSbgcUs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.87.235]) by APP-01 (Coremail) with SMTP id qwCowABHN6tT0aVogOTBDQ--.24665S4; Wed, 20 Aug 2025 21:44:52 +0800 (CST) From: Vivian Wang Date: Wed, 20 Aug 2025 21:44:46 +0800 Subject: [PATCH 2/6] riscv: pgtable: Convert to use_alternative_unlikely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-riscv-altn-helper-wip-v1-2-c3c626c1f7e6@iscas.ac.cn> References: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> In-Reply-To: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes Cc: Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: qwCowABHN6tT0aVogOTBDQ--.24665S4 X-Coremail-Antispam: 1UD129KBjvJXoWxJFWUKFWUWrWxtFyftF1xGrg_yoW5CFy5pr Z3CasxXFWrGw1I9rZayr4Uur45Z39ag3Z8tr1S93ZYyr4akrWavFnxJ3WSvry8Ja97X34x KF4Ykr45Gw1ayr7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmj14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jryl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1le2I2 62IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI8IcV AFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwACjcxG 0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0xkIwI 1lc7CjxVAaw2AFwI0_Jw0_GFyl42xK82IYc2Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_ Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17 CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0 I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I 8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWxJrUvcSsGvfC2Kfnx nUUI43ZEXa7VUbH5lUUUUUU== X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use use_alternative_unlikely() to check for RISCV_ISA_EXT_SVVPTC, replacing the use of asm goto with ALTERNATIVE. The "unlikely" variant is used to match the behavior of the original implementation using ALTERNATIVE("nop", "j %l[svvptc]", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/pgtable.h | 15 +++++++-------- arch/riscv/mm/pgtable.c | 22 ++++++++++------------ 2 files changed, 17 insertions(+), 20 deletions(-) diff --git a/arch/riscv/include/asm/pgtable.h b/arch/riscv/include/asm/pgta= ble.h index 91697fbf1f9013005800f713797e4b6b1fc8d312..81eb386da837f064c7372530e2f= 2227575a703d3 100644 --- a/arch/riscv/include/asm/pgtable.h +++ b/arch/riscv/include/asm/pgtable.h @@ -495,8 +495,13 @@ static inline void update_mmu_cache_range(struct vm_fa= ult *vmf, struct vm_area_struct *vma, unsigned long address, pte_t *ptep, unsigned int nr) { - asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) - : : : : svvptc); + /* + * Svvptc guarantees that the new valid pte will be visible within + * a bounded timeframe, so when the uarch does not cache invalid + * entries, we don't have to do anything. + */ + if (use_alternative_unlikely(0, RISCV_ISA_EXT_SVVPTC)) + return; =20 /* * The kernel assumes that TLBs don't cache invalid entries, but @@ -508,12 +513,6 @@ static inline void update_mmu_cache_range(struct vm_fa= ult *vmf, while (nr--) local_flush_tlb_page(address + nr * PAGE_SIZE); =20 -svvptc:; - /* - * Svvptc guarantees that the new valid pte will be visible within - * a bounded timeframe, so when the uarch does not cache invalid - * entries, we don't have to do anything. - */ } #define update_mmu_cache(vma, addr, ptep) \ update_mmu_cache_range(NULL, vma, addr, ptep, 1) diff --git a/arch/riscv/mm/pgtable.c b/arch/riscv/mm/pgtable.c index 8b6c0a112a8db4e91de54c3bd3bd527a605a6197..e0c414fa0d433fdc39c80ec390c= 467ca59a9a334 100644 --- a/arch/riscv/mm/pgtable.c +++ b/arch/riscv/mm/pgtable.c @@ -9,8 +9,16 @@ int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address, pte_t *ptep, pte_t entry, int dirty) { - asm goto(ALTERNATIVE("nop", "j %l[svvptc]", 0, RISCV_ISA_EXT_SVVPTC, 1) - : : : : svvptc); + if (use_alternative_unlikely(0, RISCV_ISA_EXT_SVVPTC)) { + if (!pte_same(ptep_get(ptep), entry)) { + __set_pte_at(vma->vm_mm, ptep, entry); + /* Here only not svadu is impacted */ + flush_tlb_page(vma, address); + return true; + } + + return false; + } =20 if (!pte_same(ptep_get(ptep), entry)) __set_pte_at(vma->vm_mm, ptep, entry); @@ -19,16 +27,6 @@ int ptep_set_access_flags(struct vm_area_struct *vma, * the case that the PTE changed and the spurious fault case. */ return true; - -svvptc: - if (!pte_same(ptep_get(ptep), entry)) { - __set_pte_at(vma->vm_mm, ptep, entry); - /* Here only not svadu is impacted */ - flush_tlb_page(vma, address); - return true; - } - - return false; } =20 int ptep_test_and_clear_young(struct vm_area_struct *vma, --=20 2.50.1 From nobody Sat Oct 4 03:17:09 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0289B321F5C for ; Wed, 20 Aug 2025 13:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; cv=none; b=RW0GYDcTx8yD7+47y4PpKaXZSGntqZL5VIuLnGTjHPGLst1ziicO3fL8DwH1eUc3gzT+VQ7IBRGp/Wf836R0bEeeYQb8IO7KNBNqjq4dzod+gArqZSa0IduNlXUNI3WFahd+gXE6+Jsc+t6pgVpupEfCwMwstpUyisaIiydtc7Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; c=relaxed/simple; bh=le57gNwHYQnmJmjrHAge3cBUX2EEkP4b/lkxD1Aej6A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Bhq/CKMKdhqdUfYJXdhCG4eZu+K2ZyteiqO6bAQXM6qptQypRkpMCXXvsEb+cb54MuhuLOlHlrRpJHBLnANKVUmtJpt7ICVeWEfboVUQ5/weW5PGc9qLVgmubTWfXTct0AwDHcz2iXOGu8DPEaLHGNEbswUFduZDqEdjEgcO31M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.87.235]) by APP-01 (Coremail) with SMTP id qwCowABHN6tT0aVogOTBDQ--.24665S5; Wed, 20 Aug 2025 21:44:52 +0800 (CST) From: Vivian Wang Date: Wed, 20 Aug 2025 21:44:47 +0800 Subject: [PATCH 3/6] riscv: checksum: Convert to use_alternative_likely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-riscv-altn-helper-wip-v1-3-c3c626c1f7e6@iscas.ac.cn> References: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> In-Reply-To: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes Cc: Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: qwCowABHN6tT0aVogOTBDQ--.24665S5 X-Coremail-Antispam: 1UD129KBjvJXoW3ArWrAF43ur1fWFyDWr17ZFb_yoW7XrWrpF s3trWrKFykCa4Sk34qyrZ8Wrn8Xw4kGwn8KrsxGry8AF90y3sxKr1DtF13Ary5XFyIqa4S yayfuw1a93W5AaUanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUm014x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j 6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7 AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE 2Ix0cI8IcVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcV C2z280aVAFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8Jr0_Cr1UYxBIdaVFxhVj vjDU0xZFpf9x0JUHWlkUUUUU= X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use use_alternative_likely() to check for RISCV_ISA_EXT_ZBB, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[no_zbb]", "nop", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/checksum.h | 13 +++----- arch/riscv/lib/csum.c | 65 +++++++++++++++--------------------= ---- 2 files changed, 28 insertions(+), 50 deletions(-) diff --git a/arch/riscv/include/asm/checksum.h b/arch/riscv/include/asm/che= cksum.h index da378856f1d590e22271b90e803c7e55e8dd22e3..14f3942007b55646a0feb82bf73= 351323350347e 100644 --- a/arch/riscv/include/asm/checksum.h +++ b/arch/riscv/include/asm/checksum.h @@ -49,16 +49,11 @@ static inline __sum16 ip_fast_csum(const void *iph, uns= igned int ihl) * ZBB only saves three instructions on 32-bit and five on 64-bit so not * worth checking if supported without Alternatives. */ - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { unsigned long fold_temp; =20 - asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : - : - : - : no_zbb); - if (IS_ENABLED(CONFIG_32BIT)) { asm(".option push \n\ .option arch,+zbb \n\ @@ -81,7 +76,7 @@ static inline __sum16 ip_fast_csum(const void *iph, unsig= ned int ihl) } return (__force __sum16)(csum >> 16); } -no_zbb: + #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); csum >>=3D 32; diff --git a/arch/riscv/lib/csum.c b/arch/riscv/lib/csum.c index 9408f50ca59a8901f7cfbcf3297d1492172c6ea2..659d3b51d0db1010deda042134b= def1f79cf8b42 100644 --- a/arch/riscv/lib/csum.c +++ b/arch/riscv/lib/csum.c @@ -40,20 +40,15 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, uproto =3D (__force unsigned int)htonl(proto); sum +=3D uproto; =20 - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) { + /* + * Zbb is likely available when the kernel is compiled with Zbb + * support. + */ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { unsigned long fold_temp; =20 - /* - * Zbb is likely available when the kernel is compiled with Zbb - * support, so nop when Zbb is available and jump when Zbb is - * not available. - */ - asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : - : - : - : no_zbb); asm(".option push \n\ .option arch,+zbb \n\ rori %[fold_temp], %[sum], 32 \n\ @@ -66,7 +61,7 @@ __sum16 csum_ipv6_magic(const struct in6_addr *saddr, : [sum] "+r" (sum), [fold_temp] "=3D&r" (fold_temp)); return (__force __sum16)(sum >> 16); } -no_zbb: + sum +=3D ror64(sum, 32); sum >>=3D 32; return csum_fold((__force __wsum)sum); @@ -151,22 +146,16 @@ do_csum_with_alignment(const unsigned char *buff, int= len) end =3D (const unsigned long *)(buff + len); csum =3D do_csum_common(ptr, end, data); =20 + /* + * Zbb is likely available when the kernel is compiled with Zbb + * support. + */ #ifdef CC_HAS_ASM_GOTO_TIED_OUTPUT - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) { + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { unsigned long fold_temp; =20 - /* - * Zbb is likely available when the kernel is compiled with Zbb - * support, so nop when Zbb is available and jump when Zbb is - * not available. - */ - asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : - : - : - : no_zbb); - #ifdef CONFIG_32BIT asm_goto_output(".option push \n\ .option arch,+zbb \n\ @@ -204,7 +193,7 @@ do_csum_with_alignment(const unsigned char *buff, int l= en) end: return csum >> 16; } -no_zbb: + #endif /* CC_HAS_ASM_GOTO_TIED_OUTPUT */ #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); @@ -234,21 +223,15 @@ do_csum_no_alignment(const unsigned char *buff, int l= en) end =3D (const unsigned long *)(buff + len); csum =3D do_csum_common(ptr, end, data); =20 - if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && IS_ENABLED(CONFIG_TOOLCHAIN_HAS_Z= BB)) { + /* + * Zbb is likely available when the kernel is compiled with Zbb + * support. + */ + if (IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && + IS_ENABLED(CONFIG_TOOLCHAIN_HAS_ZBB) && + use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { unsigned long fold_temp; =20 - /* - * Zbb is likely available when the kernel is compiled with Zbb - * support, so nop when Zbb is available and jump when Zbb is - * not available. - */ - asm goto(ALTERNATIVE("j %l[no_zbb]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : - : - : - : no_zbb); - #ifdef CONFIG_32BIT asm (".option push \n\ .option arch,+zbb \n\ @@ -274,7 +257,7 @@ do_csum_no_alignment(const unsigned char *buff, int len) #endif /* !CONFIG_32BIT */ return csum >> 16; } -no_zbb: + #ifndef CONFIG_32BIT csum +=3D ror64(csum, 32); csum >>=3D 32; --=20 2.50.1 From nobody Sat Oct 4 03:17:09 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F6DC321F55 for ; Wed, 20 Aug 2025 13:45:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; cv=none; b=WwVkKG5DEfBfaftA/lFjvPm4qEEDrNCXRsJm2hfIIeENeXhxk03YvnqE1HAqDh8uizVLbjAC8DYhuHiF586CdUwzZ8dVeksX9UCf0raY5dK3RPtYTpNX2QEIH1T6hqzNTLO2JEuMblaIp7M0Wq6uwxQv2z3a20w0xPPqboil/1E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; c=relaxed/simple; bh=NpzORn97GESos8tdB/QDdUeNSnxDvCcvqgwce60Fzho=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=HphR4yew2EYCcc7wsQggcVbPQ912izhJuBe9Hzb8YANj6KZMPW2iWn5VEvVy/5FIiapVlsmyssHPePxxqOCjfimzqXbFbZsfGy27ibWNN1ZULTa2m9CQdyYO6FWUJhAhwWaermhbSbqJJwFJljlyiwMnZa1NTbEUaYHji4WyuzA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.87.235]) by APP-01 (Coremail) with SMTP id qwCowABHN6tT0aVogOTBDQ--.24665S6; Wed, 20 Aug 2025 21:44:52 +0800 (CST) From: Vivian Wang Date: Wed, 20 Aug 2025 21:44:48 +0800 Subject: [PATCH 4/6] riscv: hweight: Convert to use_alternative_likely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-riscv-altn-helper-wip-v1-4-c3c626c1f7e6@iscas.ac.cn> References: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> In-Reply-To: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes Cc: Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: qwCowABHN6tT0aVogOTBDQ--.24665S6 X-Coremail-Antispam: 1UD129KBjvJXoW7tr4rXF13uFW3Jry3uryDKFg_yoW8uF1fpr 4Ik397Ca48Ka1xuF9Iyrn5Xa1rW395G343GrW3urW8XFyYkw4Yyr18K3Z5Gr95tFyvq3Wx XrW7Aa43u3WjyF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmI14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnI WIevJa73UjIFyTuYvjfUOyIUUUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use use_alternative_likely() to check for RISCV_ISA_EXT_ZBB, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[legacy]", "nop", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/arch_hweight.h | 42 +++++++++++++++----------------= ---- 1 file changed, 18 insertions(+), 24 deletions(-) diff --git a/arch/riscv/include/asm/arch_hweight.h b/arch/riscv/include/asm= /arch_hweight.h index 0e7cdbbec8efd3c293da2fa96a8c6d0a93faf56f..58ed7a3b2d7882f6a7913c4bfdb= 9bce4a4394956 100644 --- a/arch/riscv/include/asm/arch_hweight.h +++ b/arch/riscv/include/asm/arch_hweight.h @@ -20,20 +20,17 @@ static __always_inline unsigned int __arch_hweight32(unsigned int w) { #if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { + asm (".option push\n" + ".option arch,+zbb\n" + CPOPW "%0, %1\n" + ".option pop\n" + : "=3Dr" (w) : "r" (w) :); =20 - asm (".option push\n" - ".option arch,+zbb\n" - CPOPW "%0, %1\n" - ".option pop\n" - : "=3Dr" (w) : "r" (w) :); - - return w; - -legacy: + return w; + } #endif + return __sw_hweight32(w); } =20 @@ -51,20 +48,17 @@ static inline unsigned int __arch_hweight8(unsigned int= w) static __always_inline unsigned long __arch_hweight64(__u64 w) { #if defined(CONFIG_RISCV_ISA_ZBB) && defined(CONFIG_TOOLCHAIN_HAS_ZBB) - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); + if (use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { + asm (".option push\n" + ".option arch,+zbb\n" + "cpop %0, %1\n" + ".option pop\n" + : "=3Dr" (w) : "r" (w) :); =20 - asm (".option push\n" - ".option arch,+zbb\n" - "cpop %0, %1\n" - ".option pop\n" - : "=3Dr" (w) : "r" (w) :); - - return w; - -legacy: + return w; + } #endif + return __sw_hweight64(w); } #else /* BITS_PER_LONG =3D=3D 64 */ --=20 2.50.1 From nobody Sat Oct 4 03:17:09 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02800321F5B for ; Wed, 20 Aug 2025 13:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697512; cv=none; b=YvWcRfqa+xxdlzLqyoYd2HqK48XJazSKzvw0fGLmuy4YSJWPGp+yo4ZslE3a5vKZJBwJsIZUQGrlLIAKClfMlQZ9PKio3UfQh5PhkHKmYR8qrhpE7ysF/w53UoGAs7w1k9MmTt2ThSB4HZkjt+G27BvRSQC4sr3/Z+mp3wML1hU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697512; c=relaxed/simple; bh=9Bb/39yuIfYm4QnC8/6dotXjRhj+voskjZfoJY7Zs4Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=VScNkHhl2qdYx9earBPLw91LrOVGNC8PKm5Lr0SFtWxVm2th7tpR87AzC9GOJ28hXugp/LpMat8YrwGeCTxWi9BHVhbx5w0qHE/jghPWRSGGGGrtNBGiPh58pO5/Uy8UMMriTvX+O/nZia/bRc+xSTsB08fWSjbQdNTHiFXBd/Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.87.235]) by APP-01 (Coremail) with SMTP id qwCowABHN6tT0aVogOTBDQ--.24665S7; Wed, 20 Aug 2025 21:44:52 +0800 (CST) From: Vivian Wang Date: Wed, 20 Aug 2025 21:44:49 +0800 Subject: [PATCH 5/6] riscv: bitops: Convert to use_alternative_likely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-riscv-altn-helper-wip-v1-5-c3c626c1f7e6@iscas.ac.cn> References: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> In-Reply-To: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes Cc: Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: qwCowABHN6tT0aVogOTBDQ--.24665S7 X-Coremail-Antispam: 1UD129KBjvJXoWxZF4UZry5Aw47ur1UtryrJFb_yoW5tFWxpr 1kKws7CayDKa4ruFn2yr1fW3WrWrW7J39rGr93GF1kJa4DC39Ykr1Fk3WfKr95AFWvq347 ZrWUAF95C3WUZ3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmI14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnI WIevJa73UjIFyTuYvjfUOyIUUUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use use_alternative_likely() to check for RISCV_ISA_EXT_ZBB, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[legacy]", "nop", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/bitops.h | 112 ++++++++++++++++++------------------= ---- 1 file changed, 50 insertions(+), 62 deletions(-) diff --git a/arch/riscv/include/asm/bitops.h b/arch/riscv/include/asm/bitop= s.h index d59310f74c2ba70caeb7b9b0e9221882117583f5..0257d547a96293909d90b017c8a= 48b508d0fd642 100644 --- a/arch/riscv/include/asm/bitops.h +++ b/arch/riscv/include/asm/bitops.h @@ -47,20 +47,17 @@ =20 static __always_inline unsigned long variable__ffs(unsigned long word) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); - - asm volatile (".option push\n" - ".option arch,+zbb\n" - "ctz %0, %1\n" - ".option pop\n" - : "=3Dr" (word) : "r" (word) :); - - return word; - -legacy: - return generic___ffs(word); + if (use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { + asm volatile (".option push\n" + ".option arch,+zbb\n" + "ctz %0, %1\n" + ".option pop\n" + : "=3Dr" (word) : "r" (word) :); + + return word; + } else { + return generic___ffs(word); + } } =20 /** @@ -76,20 +73,17 @@ static __always_inline unsigned long variable__ffs(unsi= gned long word) =20 static __always_inline unsigned long variable__fls(unsigned long word) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); - - asm volatile (".option push\n" - ".option arch,+zbb\n" - "clz %0, %1\n" - ".option pop\n" - : "=3Dr" (word) : "r" (word) :); - - return BITS_PER_LONG - 1 - word; - -legacy: - return generic___fls(word); + if (use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { + asm volatile (".option push\n" + ".option arch,+zbb\n" + "clz %0, %1\n" + ".option pop\n" + : "=3Dr" (word) : "r" (word) :); + + return BITS_PER_LONG - 1 - word; + } else { + return generic___fls(word); + } } =20 /** @@ -105,23 +99,20 @@ static __always_inline unsigned long variable__fls(uns= igned long word) =20 static __always_inline int variable_ffs(int x) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); - - if (!x) - return 0; - - asm volatile (".option push\n" - ".option arch,+zbb\n" - CTZW "%0, %1\n" - ".option pop\n" - : "=3Dr" (x) : "r" (x) :); - - return x + 1; - -legacy: - return generic_ffs(x); + if (use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { + if (!x) + return 0; + + asm volatile (".option push\n" + ".option arch,+zbb\n" + CTZW "%0, %1\n" + ".option pop\n" + : "=3Dr" (x) : "r" (x) :); + + return x + 1; + } else { + return generic_ffs(x); + } } =20 /** @@ -137,23 +128,20 @@ static __always_inline int variable_ffs(int x) =20 static __always_inline int variable_fls(unsigned int x) { - asm goto(ALTERNATIVE("j %l[legacy]", "nop", 0, - RISCV_ISA_EXT_ZBB, 1) - : : : : legacy); - - if (!x) - return 0; - - asm volatile (".option push\n" - ".option arch,+zbb\n" - CLZW "%0, %1\n" - ".option pop\n" - : "=3Dr" (x) : "r" (x) :); - - return 32 - x; - -legacy: - return generic_fls(x); + if (use_alternative_likely(0, RISCV_ISA_EXT_ZBB)) { + if (!x) + return 0; + + asm volatile (".option push\n" + ".option arch,+zbb\n" + CLZW "%0, %1\n" + ".option pop\n" + : "=3Dr" (x) : "r" (x) :); + + return 32 - x; + } else { + return generic_fls(x); + } } =20 /** --=20 2.50.1 From nobody Sat Oct 4 03:17:09 2025 Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) (using TLSv1.2 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02944321F5D for ; Wed, 20 Aug 2025 13:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=159.226.251.21 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; cv=none; b=Tm7p22MhzfZNierRXdskLiYiZ7RAq1KWHdwU9d86LHfQv/lWN6Or/5dHyQdjYFfuW6B1N1qsXKkJ2Nt6qC2kVBMpkTwiC8nyE1sXxM4DRnEgiKxcjwJoSo1PIP1xY+kGUMf/LW6GV2ItAPSOPzcWKAZzk0HyyL+kS3Tnyzh+RDo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755697513; c=relaxed/simple; bh=URO3yM+bou/dZBHqBIIdbeS/iZ0OKFhoqXQrWWr8jy8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mJ3E4394MIYfiZNxeAqt4CE3oT2CaNTHPwlYjwRGgXyeihASugYCR6Crv56ZJ0dE1LdYD2nWIdzsIZYhH0E0vXKMOdmDsTCHsKP8nT/vn1CbqpMWRL6suUpDZB9L55zNJ8O9s2BRrQKZYyOJeDrKKj3Wc/O24tb1pQ0g3n0AIbU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn; spf=pass smtp.mailfrom=iscas.ac.cn; arc=none smtp.client-ip=159.226.251.21 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from [127.0.0.2] (unknown [114.241.87.235]) by APP-01 (Coremail) with SMTP id qwCowABHN6tT0aVogOTBDQ--.24665S8; Wed, 20 Aug 2025 21:44:52 +0800 (CST) From: Vivian Wang Date: Wed, 20 Aug 2025 21:44:50 +0800 Subject: [PATCH 6/6] riscv: cmpxchg: Convert to use_alternative_likely Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-riscv-altn-helper-wip-v1-6-c3c626c1f7e6@iscas.ac.cn> References: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> In-Reply-To: <20250820-riscv-altn-helper-wip-v1-0-c3c626c1f7e6@iscas.ac.cn> To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Yury Norov , Rasmus Villemoes Cc: Vivian Wang , Vivian Wang , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-CM-TRANSID: qwCowABHN6tT0aVogOTBDQ--.24665S8 X-Coremail-Antispam: 1UD129KBjvJXoWxZF4UZry8tryfXFWfuFW5trb_yoW5ury5pF n3CwsrKFWvg343uF9Iy392g3W5t397Kr4qyr9IkF95XF13Krs5ZF1Yk3sa9ry8JFWxJwn8 tFyYkr95WF1jqrDanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmI14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr 1UM28EF7xvwVC2z280aVAFwI0_GcCE3s1l84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7MxkF7I0En4kS14v26r1q6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY 6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17 CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF 0xvE2Ix0cI8IcVCY1x0267AKxVWxJVW8Jr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMI IF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr1j6F4UJbIYCTnI WIevJa73UjIFyTuYvjfUOyIUUUUUU X-CM-SenderInfo: pzdqw2pxlnt03j6l2u1dvotugofq/ Use use_alternative_likely() to check for RISCV_ISA_EXT_ZAWRS, replacing the use of asm goto with ALTERNATIVE. The "likely" variant is used to match the behavior of the original implementation using ALTERNATIVE("j %l[no_zawrs]", "nop", ...). Signed-off-by: Vivian Wang --- arch/riscv/include/asm/cmpxchg.h | 125 +++++++++++++++++++----------------= ---- 1 file changed, 61 insertions(+), 64 deletions(-) diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpx= chg.h index 0b749e7102162477432f7cf9a34768fbdf2e8cc7..1ef6e9de5f6d2721d325fa07f2e= 636ebc951dc7e 100644 --- a/arch/riscv/include/asm/cmpxchg.h +++ b/arch/riscv/include/asm/cmpxchg.h @@ -370,74 +370,71 @@ static __always_inline void __cmpwait(volatile void *= ptr, u32 *__ptr32b; ulong __s, __val, __mask; =20 - asm goto(ALTERNATIVE("j %l[no_zawrs]", "nop", - 0, RISCV_ISA_EXT_ZAWRS, 1) - : : : : no_zawrs); - - switch (size) { - case 1: - __ptr32b =3D (u32 *)((ulong)(ptr) & ~0x3); - __s =3D ((ulong)(ptr) & 0x3) * BITS_PER_BYTE; - __val =3D val << __s; - __mask =3D 0xff << __s; - - asm volatile( - " lr.w %0, %1\n" - " and %0, %0, %3\n" - " xor %0, %0, %2\n" - " bnez %0, 1f\n" - ZAWRS_WRS_NTO "\n" - "1:" - : "=3D&r" (tmp), "+A" (*(__ptr32b)) - : "r" (__val), "r" (__mask) - : "memory"); - break; - case 2: - __ptr32b =3D (u32 *)((ulong)(ptr) & ~0x3); - __s =3D ((ulong)(ptr) & 0x2) * BITS_PER_BYTE; - __val =3D val << __s; - __mask =3D 0xffff << __s; - - asm volatile( - " lr.w %0, %1\n" - " and %0, %0, %3\n" - " xor %0, %0, %2\n" - " bnez %0, 1f\n" - ZAWRS_WRS_NTO "\n" - "1:" - : "=3D&r" (tmp), "+A" (*(__ptr32b)) - : "r" (__val), "r" (__mask) - : "memory"); - break; - case 4: - asm volatile( - " lr.w %0, %1\n" - " xor %0, %0, %2\n" - " bnez %0, 1f\n" - ZAWRS_WRS_NTO "\n" - "1:" - : "=3D&r" (tmp), "+A" (*(u32 *)ptr) - : "r" (val)); - break; + if (use_alternative_likely(0, RISCV_ISA_EXT_ZAWRS)) { + switch (size) { + case 1: + __ptr32b =3D (u32 *)((ulong)(ptr) & ~0x3); + __s =3D ((ulong)(ptr) & 0x3) * BITS_PER_BYTE; + __val =3D val << __s; + __mask =3D 0xff << __s; + + asm volatile( + " lr.w %0, %1\n" + " and %0, %0, %3\n" + " xor %0, %0, %2\n" + " bnez %0, 1f\n" + ZAWRS_WRS_NTO "\n" + "1:" + : "=3D&r" (tmp), "+A" (*(__ptr32b)) + : "r" (__val), "r" (__mask) + : "memory"); + break; + case 2: + __ptr32b =3D (u32 *)((ulong)(ptr) & ~0x3); + __s =3D ((ulong)(ptr) & 0x2) * BITS_PER_BYTE; + __val =3D val << __s; + __mask =3D 0xffff << __s; + + asm volatile( + " lr.w %0, %1\n" + " and %0, %0, %3\n" + " xor %0, %0, %2\n" + " bnez %0, 1f\n" + ZAWRS_WRS_NTO "\n" + "1:" + : "=3D&r" (tmp), "+A" (*(__ptr32b)) + : "r" (__val), "r" (__mask) + : "memory"); + break; + case 4: + asm volatile( + " lr.w %0, %1\n" + " xor %0, %0, %2\n" + " bnez %0, 1f\n" + ZAWRS_WRS_NTO "\n" + "1:" + : "=3D&r" (tmp), "+A" (*(u32 *)ptr) + : "r" (val)); + break; #if __riscv_xlen =3D=3D 64 - case 8: - asm volatile( - " lr.d %0, %1\n" - " xor %0, %0, %2\n" - " bnez %0, 1f\n" - ZAWRS_WRS_NTO "\n" - "1:" - : "=3D&r" (tmp), "+A" (*(u64 *)ptr) - : "r" (val)); - break; + case 8: + asm volatile( + " lr.d %0, %1\n" + " xor %0, %0, %2\n" + " bnez %0, 1f\n" + ZAWRS_WRS_NTO "\n" + "1:" + : "=3D&r" (tmp), "+A" (*(u64 *)ptr) + : "r" (val)); + break; #endif - default: - BUILD_BUG(); - } + default: + BUILD_BUG(); + } =20 - return; + return; + } =20 -no_zawrs: asm volatile(RISCV_PAUSE : : : "memory"); } =20 --=20 2.50.1