From nobody Sat Oct 4 04:56:46 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AA0326F45A for ; Wed, 20 Aug 2025 14:02:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698533; cv=none; b=E1WbUJrR6cBX/KAZd/tg0p7jEuFu6XV5J0hmItQaMGfYI6FHRgJYCPL/UG4BzOuG9nEtfHVQqFvsPjzGumYYgG6JVUbNXmo42itVVIUvmtlby5AaqgLOuMqlrFlcOCUs183MTwVcPp8fOpntBdKmZ/RFjZlx1SmAZ37P4EkwYmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698533; c=relaxed/simple; bh=3tToQxPuD+Y+SqYGY3q3oiIhiOifongn+nBP/XX4RXc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ovFU5kg8h/jXzHj6THZyWnsLxaX7OON6OuIuE14b8Btpq+F9LbSpkRE8liF/UDJyUe/QzIblxGFHCqbLqo5MZuZe5GOYLngv95Lv0UTXvSaUuN/VOTURh/v8CZwL0RHRJ0p7OzOdtxSkJbBu4+IN+KGc3roH78lKf2KPwVwHy44= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g1DX8RTu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g1DX8RTu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31C2AC116B1; Wed, 20 Aug 2025 14:02:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698532; bh=3tToQxPuD+Y+SqYGY3q3oiIhiOifongn+nBP/XX4RXc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=g1DX8RTu8fwBrDLssJQyt5TEyZD9fZ36GSf2wIzgYcdZL3mtWmusx3jLlgP3S/YdR bFNAsbB34ZrW11HLTMYhSHpkZTuVekNPGkWbK99LBvbnWYpQHJiLdpGKfhutgc5cY9 aDm4O2RE/N9xJERc3Hwuh9CCkCUGWw84j0BfW7wsnOi0SeCEB1K8xQ9/+0e4T0tLKD ibtpRfBPLCgnshZymACHg+8bok7uvhLThst0WkAv5NtAi41nHOtoBfJqRaECPrQVFt wUiF05X7LCNvrlB62IWxBmEdga8XHPveoxxMyiBKDO+tcJ+hd/eJpXlsfWM9v4LWPQ 3YDSzXmYoDrvA== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:44 +0200 Subject: [PATCH v2 04/14] drm/tidss: dispc: Get rid of FLD_VAL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-4-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7248; i=mripard@kernel.org; h=from:subject:message-id; bh=3tToQxPuD+Y+SqYGY3q3oiIhiOifongn+nBP/XX4RXc=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwa0dG4LEWf6sVR/xopDIY6bdvzSvfVf/n+n9P7ZO U1c1rYxHVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAi57wY60M8tr7YvJkv75ay nb64tfrqzJrM/DvaOusU3JuXnYn/uyV5xVGBXZVb+9hKb9tOePksn7FOv8XnePDGuYueqn9fv3S /cNMRdaeJlmrLYs6H3juYE/fusscVq0v9x6JvvM17I+Yd9tIOAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_VAL function is an equivalent to what FIELD_PREP + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 58 +++++++++++++++++----------------= ---- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 929c9e3ac1174df68937afd86f13bda4e3a66394..f0568ae3e7bebf481bb5f6d0603= dae4b6e6a0729 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,17 +607,10 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_VAL(val, start, end) \ - ({ \ - int _end_inner =3D (end); \ - u32 _new_val =3D ((val) << _end_inner) & GENMASK((start), _end_inner); \ - _new_val; \ - }) - #define FLD_GET(val, start, end) \ ({ \ int _end =3D (end); \ u32 _ret_val =3D ((val) & GENMASK((start), _end)) >> _end; \ _ret_val; \ @@ -625,11 +618,11 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) =20 #define FLD_MOD(orig, val, start, end) \ ({ \ int _start =3D (start), _end =3D (end); \ u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ - u32 _new_val =3D _masked_val | FLD_VAL((val), _start, _end); \ + u32 _new_val =3D _masked_val | FIELD_PREP(GENMASK(_start, _end), (val));= \ _new_val; \ }) =20 #define REG_GET(dispc, idx, start, end) \ ((u32)FLD_GET(dispc_read((dispc), (idx)), (start), (end))) @@ -1233,18 +1226,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, vfp =3D mode->vsync_start - mode->vdisplay; vsw =3D mode->vsync_end - mode->vsync_start; vbp =3D mode->vtotal - mode->vsync_end; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, - FLD_VAL(hsw - 1, 7, 0) | - FLD_VAL(hfp - 1, 19, 8) | - FLD_VAL(hbp - 1, 31, 20)); + FIELD_PREP(GENMASK(7, 0), hsw - 1) | + FIELD_PREP(GENMASK(19, 8), hfp - 1) | + FIELD_PREP(GENMASK(31, 20), hbp - 1)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, - FLD_VAL(vsw - 1, 7, 0) | - FLD_VAL(vfp, 19, 8) | - FLD_VAL(vbp, 31, 20)); + FIELD_PREP(GENMASK(7, 0), vsw - 1) | + FIELD_PREP(GENMASK(19, 8), vfp) | + FIELD_PREP(GENMASK(31, 20), vbp)); =20 ivs =3D !!(mode->flags & DRM_MODE_FLAG_NVSYNC); =20 ihs =3D !!(mode->flags & DRM_MODE_FLAG_NHSYNC); =20 @@ -1263,21 +1256,21 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, /* always use DE_HIGH for OLDI */ if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) ieo =3D false; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, - FLD_VAL(align, 18, 18) | - FLD_VAL(onoff, 17, 17) | - FLD_VAL(rf, 16, 16) | - FLD_VAL(ieo, 15, 15) | - FLD_VAL(ipc, 14, 14) | - FLD_VAL(ihs, 13, 13) | - FLD_VAL(ivs, 12, 12)); + FIELD_PREP(GENMASK(18, 18), align) | + FIELD_PREP(GENMASK(17, 17), onoff) | + FIELD_PREP(GENMASK(16, 16), rf) | + FIELD_PREP(GENMASK(15, 15), ieo) | + FIELD_PREP(GENMASK(14, 14), ipc) | + FIELD_PREP(GENMASK(13, 13), ihs) | + FIELD_PREP(GENMASK(12, 12), ivs)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, - FLD_VAL(mode->hdisplay - 1, 11, 0) | - FLD_VAL(mode->vdisplay - 1, 27, 16)); + FIELD_PREP(GENMASK(11, 0), mode->hdisplay - 1) | + FIELD_PREP(GENMASK(27, 16), mode->vdisplay - 1)); =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) @@ -1589,18 +1582,18 @@ struct dispc_csc_coef { #define DISPC_CSC_REGVAL_LEN 8 =20 static void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) { -#define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19)) +#define OVAL(x, y) (FIELD_PREP(GENMASK(15, 3), x) | FIELD_PREP(GENMASK(31,= 19), y)) regval[5] =3D OVAL(csc->preoffset[0], csc->preoffset[1]); regval[6] =3D OVAL(csc->preoffset[2], csc->postoffset[0]); regval[7] =3D OVAL(csc->postoffset[1], csc->postoffset[2]); #undef OVAL } =20 -#define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16)) +#define CVAL(x, y) (FIELD_PREP(GENMASK(10, 0), x) | FIELD_PREP(GENMASK(26,= 16), y)) static void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regva= l) { regval[0] =3D CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); regval[1] =3D CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); @@ -1835,11 +1828,12 @@ static void dispc_vid_write_fir_coefs(struct dispc_= device *dispc, s16 c1, c2; u32 c12; =20 c1 =3D coefs->c1[phase]; c2 =3D coefs->c2[phase]; - c12 =3D FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20); + c12 =3D FIELD_PREP(GENMASK(19, 10), c1) | FIELD_PREP(GENMASK(29, 20), + c2); =20 dispc_vid_write(dispc, hw_plane, reg, c12); } } =20 @@ -2333,18 +2327,18 @@ static u32 dispc_vid_get_fifo_size(struct dispc_dev= ice *dispc, u32 hw_plane) =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, - FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); + FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); } =20 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, - FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); + FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); } =20 static void dispc_k2g_plane_init(struct dispc_device *dispc) { unsigned int hw_plane; @@ -2481,12 +2475,12 @@ static void dispc_initial_config(struct dispc_devic= e *dispc) dispc_vp_init(dispc); =20 /* Note: Hardcoded DPI routing on J721E for now */ if (dispc->feat->subrev =3D=3D DISPC_J721E) { dispc_write(dispc, DISPC_CONNECTIONS, - FLD_VAL(2, 3, 0) | /* VP1 to DPI0 */ - FLD_VAL(8, 7, 4) /* VP3 to DPI1 */ + FIELD_PREP(GENMASK(3, 0), 2) | /* VP1 to DPI0 */ + FIELD_PREP(GENMASK(7, 4), 8) /* VP3 to DPI1 */ ); } } =20 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, @@ -2660,12 +2654,12 @@ static void dispc_k2g_cpr_from_ctm(const struct drm= _color_ctm *ctm, cpr->m[CSC_BR] =3D dispc_S31_32_to_s2_8(ctm->matrix[6]); cpr->m[CSC_BG] =3D dispc_S31_32_to_s2_8(ctm->matrix[7]); cpr->m[CSC_BB] =3D dispc_S31_32_to_s2_8(ctm->matrix[8]); } =20 -#define CVAL(xR, xG, xB) (FLD_VAL(xR, 9, 0) | FLD_VAL(xG, 20, 11) | \ - FLD_VAL(xB, 31, 22)) +#define CVAL(xR, xG, xB) (FIELD_PREP(GENMASK(9, 0), xR) | FIELD_PREP(GENMA= SK(20, 11), xG) | \ + FIELD_PREP(GENMASK(31, 22), xB)) =20 static void dispc_k2g_vp_csc_cpr_regval(const struct dispc_csc_coef *csc, u32 *regval) { regval[0] =3D CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); --=20 2.50.1