From nobody Sat Oct 4 04:56:44 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B9982E5B2F for ; Wed, 20 Aug 2025 14:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698549; cv=none; b=ajQPhRuT7GfvVRY9p87/GdjdofjBw42Olih41a54zBobDaWXOmm00vLNkh/jC2AlCEOXZNoNnMROZFaMnK9vWXmFoB6K+9O5OJ4Vwp15+uaS9Fe+GIsWWdtzVvvgJlwv9+nETjFqtLgvcBfWEVpfvSpI6PsT0D8NxI4+FPXotCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698549; c=relaxed/simple; bh=fDlH7Dl44z2D5Cx4UK14nab6ys1a6BsEEAuxo4ovtjo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oJlWqV6ycaqqKui8C+uPArWocJqztGjQ1RmBMSnNPVWAH6ys+KhEglIn6Esfhh1aUJ2Ko0F6uN/aDBK2b5JO6xT/i4LIaS3V1bVQ0by0zmob8maOemMEAxZYJqAwQkQm48i2upxgR5y1cjdwBJVJ/07SFBr9UswCwZIm3bOSGWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vq2C+kqc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vq2C+kqc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70DD2C116B1; Wed, 20 Aug 2025 14:02:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698548; bh=fDlH7Dl44z2D5Cx4UK14nab6ys1a6BsEEAuxo4ovtjo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Vq2C+kqc7lmG84N+RXhvDjohnx58pl6gc5A8npjjEk6sLc1z4C8TWpcuYvJVAcym/ +cJs/EnWmZ9xPAAFhLD+VD5V+I2iSEYsjIGtc9vKEXGW/WooWlUQ8mwAKgZmZk7E4B /vQSc8wdYfGQvRhyuxlviqzZ4iwGs16O6GYW48QD/gISpIrSeqsY21RFJsIBSynfzU aGjT/l2UPt7vjdB6P2+J5BwvmuB87Ccby1bDf5da58PvuYIINN/E1EnEdvyNPLE2zl gdcESqIA94Lucrux7LXA3HFYVJmCo36zowWRWLjkLBrAT4GLFUtBdCQ09wPZLAnyeC nKTcoZcPA+BeQ== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:50 +0200 Subject: [PATCH v2 10/14] drm/tidss: dispc: Switch VID_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-10-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5234; i=mripard@kernel.org; h=from:subject:message-id; bh=fDlH7Dl44z2D5Cx4UK14nab6ys1a6BsEEAuxo4ovtjo=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwbfsjnd/iBsIsf3p9fmXUkMi558/crGGR5ri29y7 CtwYpOV7pjKwiDMySArpsjyRCbs9PL2xVUO9it/wMxhZQIZwsDFKQATyZ7AWKeVYSl8Om2dJF/P r/32fq6n/K9k3il8s6+uZHHCj+yS0rn/9mx5drU/bZ5+8Cqemu9T5jPWafRIa2w45a2Y7xsYqsL L8sR8pbDqff1Ns1oeHV2Rt+Ygk0PzA9lTuq0qlVrbX1hLyMgDAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VID_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VID_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index b4928cfbb6f7ca9a03371c5e599e2029baae333f..8c0949203ace147e403ea43ab46= 8c3a56d170156 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -622,17 +622,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) }) =20 #define VID_REG_GET(dispc, hw_plane, idx, mask) \ ((u32)FIELD_GET((mask), dispc_vid_read((dispc), (hw_plane), (idx)))) =20 -#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ +#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \ }) =20 #define VP_REG_GET(dispc, vp, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ @@ -1755,11 +1755,12 @@ static void dispc_vid_csc_setup(struct dispc_device= *dispc, u32 hw_plane, } =20 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(9, 9)); } =20 /* SCALER */ =20 static u32 dispc_calc_fir_inc(u32 in, u32 out) @@ -2012,24 +2013,24 @@ static void dispc_vid_set_scaling(struct dispc_devi= ce *dispc, u32 hw_plane, struct dispc_scaling_params *sp, u32 fourcc) { /* HORIZONTAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_x, 7, 7); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x, + GENMASK(7, 7)); =20 /* VERTICAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_y, 8, 8); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y, + GENMASK(8, 8)); =20 /* Skip the rest if no scaling is used */ if (!sp->scale_x && !sp->scale_y) return; =20 /* VERTICAL 5-TAPS */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->five_taps, 21, 21); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps, + GENMASK(21, 21)); =20 if (dispc_fourcc_is_yuv(fourcc)) { if (sp->scale_x) { dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, sp->fir_xinc_uv); @@ -2115,11 +2116,11 @@ static void dispc_plane_set_pixel_format(struct dis= pc_device *dispc, =20 for (i =3D 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { if (dispc_color_formats[i].fourcc =3D=3D fourcc) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, dispc_color_formats[i].dss_code, - 6, 1); + GENMASK(6, 1)); return; } } =20 WARN_ON(1); @@ -2293,19 +2294,20 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, 0xFF & (state->alpha >> 8)); =20 if (state->pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 28, 28); + GENMASK(28, 28)); else VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 28, 28); + GENMASK(28, 28)); } =20 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool ena= ble) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(0, 0)); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, @@ -2370,11 +2372,11 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) * Prefetch up to fifo high-threshold value to minimize the * possibility of underflows. Note that this means the PRELOAD * register is ignored. */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 19, 19); + GENMASK(19, 19)); } } =20 static void dispc_k3_plane_init(struct dispc_device *dispc) { @@ -2421,11 +2423,11 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); =20 /* Prefech up to PRELOAD value */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 19, 19); + GENMASK(19, 19)); } } =20 static void dispc_plane_init(struct dispc_device *dispc) { --=20 2.50.1