From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 39F292690D1 for ; Wed, 20 Aug 2025 14:02:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698524; cv=none; b=MKBLHsFEQJWtE4Xauxdnv90sGi9HI1QtAD+rgYstqmSXj9O1Cw9tpxfwGg43Wv0VR2pCTXjUqYsc1hc72u9fyeOAcj9xoT4G9DEVGTZ6CBxbWXn1UKoYxGEind/uTxWGyJ6GcPae4Kjq+AIh3uUYSe4O/ANH9MLv8iOMcybtRHk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698524; c=relaxed/simple; bh=7M8WQ93AaEVDFJvrP9tpFEBFhyFY0X5kFY5fADadnZw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Cv4qV0fh2yhTbP86z7lJ+IbkXuVVJCfGQGggqBG2L2hbVPJ7ZR+6Q81VnzprNO+lF4o5fD+0jIWQvOB2ROk1I2MGuwjE7BEPWVBySHvr4TWXDWUlt3D91OfWvNnoJUNisEhkI3Gao7wlEgfIHCukAsikmHTY/e2pLTCUC2z/zII= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bBYYpC0F; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bBYYpC0F" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 75FA5C4CEE7; Wed, 20 Aug 2025 14:02:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698523; bh=7M8WQ93AaEVDFJvrP9tpFEBFhyFY0X5kFY5fADadnZw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=bBYYpC0FkTO01ZF0XW2EroYm0Mp+L8HTFnWs0O/Gtl+5EybiJq0oCCqVf7EoLxfl3 G+P4KPSucuU0/HxyigbeHZS8oBS5WCh9kyU7IREFbHKX2gr0nZLpCwyDYdH6UrJa0n CTEj0QFokXchz2zC8qaElhkmqGYv0ykzezT/q9keH7KnPsOmdV2ZTIffCslowM8FLz c7cYlKwx8Pi2hXlBWh1qH0dPJPp4j5t4WdpNdt4L1jOCsUCXrdcHsXzx5Ydq7Q+xtx yYFVSmKm8KIc05Joecw91dyaZgutWheFaxB74qFPEaC3O6lrs4CVSBVpE9V6OiIA8L 6n+4REYkfc3qg== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:41 +0200 Subject: [PATCH v2 01/14] drm/tidss: dispc: Remove unused OVR_REG_GET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-1-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1128; i=mripard@kernel.org; h=from:subject:message-id; bh=7M8WQ93AaEVDFJvrP9tpFEBFhyFY0X5kFY5fADadnZw=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLr/r/bH52w+CrpJBp7naZmG97k+MXr/Xc9qr/gPQ0R 6MVt4rEO6ayMAhzMsiKKbI8kQk7vbx9cZWD/cofMHNYmUCGMHBxCsBEuPgY65QuS20zyz529NNa PZuf39Tz19o0tQfIs+xa4+3++/rH9U2Z/PFVSyTPVfy+rz1rxswSBcaGRpHWn26c1q98zdLO/hG TqO96ph6d6/TTae8Ex/j3peJOs1bvSLk7ydH5S/jmLVI3Y0oB X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The OVR_REG_GET function in the dispc driver is not used anywhere. Let's drop it. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 975d94547c3f9d5e9ad61aefd4eeb8ada8874cb0..8ec06412cffa71512cead9725bb= 43440258eb1ec 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -666,17 +666,10 @@ static void VP_REG_FLD_MOD(struct dispc_device *dispc= , u32 vp, u32 idx, u32 val, { dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), val, start, end)); } =20 -__maybe_unused -static u32 OVR_REG_GET(struct dispc_device *dispc, u32 ovr, u32 idx, - u32 start, u32 end) -{ - return FLD_GET(dispc_ovr_read(dispc, ovr, idx), start, end); -} - static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, u32 val, u32 start, u32 end) { dispc_ovr_write(dispc, ovr, idx, FLD_MOD(dispc_ovr_read(dispc, ovr, idx), --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2271426B771 for ; Wed, 20 Aug 2025 14:02:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698527; cv=none; b=giFiGrDnH72o3CXGphalcHnS5zv8NIgkEKbEdZPsJG+Pl/PKA4DvTfb6R+4A+gsgpomBHqxRsmFo8h/hLCJslI7R1p1cHDJ4j6ps4BmDwuZ9zqaZkvZ5UV7rEoIwpwgLEJLYijZIIRMd5PgPza48ipJ1TXoNbCKXA6USSNiULGA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698527; c=relaxed/simple; bh=3aNJgeDFD4sfqRbU+o4cUxCdoyeNnLVOpGO7B7cBEt0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ntm6puhjZ3nUzVhBd3pXq8vs9CQO/tNWShdVrjt7F3aOnBxEWPsuDwE+bmKuftgWId5zAWfMz6ep09+bdX4T9CezFavWKwb4hBpjFiB4611f+237A9dRBpDDyRvQNsMtmLIEo5wM5Wd4DxHgGSQv1sgrWQ8coeBXWCS08Fed3HU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DoZGx48O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DoZGx48O" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6925EC4CEEB; Wed, 20 Aug 2025 14:02:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698526; bh=3aNJgeDFD4sfqRbU+o4cUxCdoyeNnLVOpGO7B7cBEt0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=DoZGx48Oky4VkB8bQ8tlNarnaLpz5RJqKIGMxMd59F5qtb+Ci2CCDzNb3ZsItmu6c OSxqawWzYbY1wS4oP1PdA4yb7TknxPx1X4tjcSSseq+CNvb/sQiiFn5pOieDI7lgn0 GWUArAQHF7VvdSeKlS6YvWLpoKjY+V73I9c1jHgZL4L0sLpF89KdAHwQAm59w+eb2q BuuXiQE/vTRE+Feskut/jnp8o8YTLfFm318wycd9cGnfohnDMF8HINTuphGvEyIHtd 9FFdlOEZ3/oOB9NEauODF4nv06VbWyHLfkG2+/qIOsq8EF4Z+orswVTjUtYdY7yQ3U X1QIfggeI3veA== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:42 +0200 Subject: [PATCH v2 02/14] drm/tidss: dispc: Convert accessors to macros Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-2-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5528; i=mripard@kernel.org; h=from:subject:message-id; bh=3aNJgeDFD4sfqRbU+o4cUxCdoyeNnLVOpGO7B7cBEt0=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLr/r7JrH953L2rXlbdGT5e2sBHZX8GRlP1C2T2WdPr dHZbWPUMZWFQZiTQVZMkeWJTNjp5e2LqxzsV/6AmcPKBDKEgYtTACayJoqx4UjRh/U9mz1fuX7Y K/1PNZmB8Z6/+ld/9WTxs9kv61rqdluUzj/ifNzM3oDfz2Z+5t1QxlpJhZsHLj/7/FWPc9n3iFu T0tec7b5w4sV8vdqlssdCn1zesOnJ54nX09z/hk3zbbV+cqsJAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The dispc driver uses upper-cased, inlined, functions to provide macro-like accessors to the dispc registers. This is confusing, since upper-case is usually used by macros, and that pattern will create gcc errors later on in this series. Let's switch to macros to make it more consistent, and prevent those errors down the line. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 122 +++++++++++++++++++-------------= ---- 1 file changed, 66 insertions(+), 56 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 8ec06412cffa71512cead9725bb43440258eb1ec..10fbc99621c149f4e119ef4a458= 67c369ca5df0b 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,76 +607,86 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -static u32 FLD_MASK(u32 start, u32 end) -{ - return ((1 << (start - end + 1)) - 1) << end; -} +#define FLD_MASK(start, end) \ + ({ \ + int _end_inner =3D (end); \ + u32 _mask =3D ((1 << ((start) - _end_inner + 1)) - 1) << _end_inner; \ + _mask; \ + }) =20 -static u32 FLD_VAL(u32 val, u32 start, u32 end) -{ - return (val << end) & FLD_MASK(start, end); -} +#define FLD_VAL(val, start, end) \ + ({ \ + int _end_inner =3D (end); \ + u32 _new_val =3D ((val) << _end_inner) & FLD_MASK((start), _end_inner); \ + _new_val; \ + }) =20 -static u32 FLD_GET(u32 val, u32 start, u32 end) -{ - return (val & FLD_MASK(start, end)) >> end; -} +#define FLD_GET(val, start, end) \ + ({ \ + int _end =3D (end); \ + u32 _ret_val =3D ((val) & FLD_MASK((start), _end)) >> _end; \ + _ret_val; \ + }) =20 -static u32 FLD_MOD(u32 orig, u32 val, u32 start, u32 end) -{ - return (orig & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end); -} +#define FLD_MOD(orig, val, start, end) \ + ({ \ + int _start =3D (start), _end =3D (end); \ + u32 _masked_val =3D (orig) & ~FLD_MASK(_start, _end); \ + u32 _new_val =3D _masked_val | FLD_VAL((val), _start, _end); \ + _new_val; \ + }) =20 -static u32 REG_GET(struct dispc_device *dispc, u32 idx, u32 start, u32 end) -{ - return FLD_GET(dispc_read(dispc, idx), start, end); -} +#define REG_GET(dispc, idx, start, end) \ + ((u32)FLD_GET(dispc_read((dispc), (idx)), (start), (end))) =20 -static void REG_FLD_MOD(struct dispc_device *dispc, u32 idx, u32 val, - u32 start, u32 end) -{ - dispc_write(dispc, idx, FLD_MOD(dispc_read(dispc, idx), val, - start, end)); -} +#define REG_FLD_MOD(dispc, idx, val, start, end) \ + ({ \ + struct dispc_device *_dispc =3D (dispc); \ + u32 _idx =3D (idx); \ + u32 _curr =3D dispc_read(_dispc, _idx); \ + u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ + dispc_write(_dispc, _idx, _new); \ + }) =20 -static u32 VID_REG_GET(struct dispc_device *dispc, u32 hw_plane, u32 idx, - u32 start, u32 end) -{ - return FLD_GET(dispc_vid_read(dispc, hw_plane, idx), start, end); -} +#define VID_REG_GET(dispc, hw_plane, idx, start, end) \ + ((u32)FLD_GET(dispc_vid_read((dispc), (hw_plane), (idx)), (start), (end))) =20 -static void VID_REG_FLD_MOD(struct dispc_device *dispc, u32 hw_plane, u32 = idx, - u32 val, u32 start, u32 end) -{ - dispc_vid_write(dispc, hw_plane, idx, - FLD_MOD(dispc_vid_read(dispc, hw_plane, idx), - val, start, end)); -} +#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ + ({ \ + struct dispc_device *_dispc =3D (dispc); \ + u32 _hw_plane =3D (hw_plane); \ + u32 _idx =3D (idx); \ + u32 _curr =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ + u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ + dispc_vid_write(_dispc, _hw_plane, _idx, _new); \ + }) =20 -static u32 VP_REG_GET(struct dispc_device *dispc, u32 vp, u32 idx, - u32 start, u32 end) -{ - return FLD_GET(dispc_vp_read(dispc, vp, idx), start, end); -} +#define VP_REG_GET(dispc, vp, idx, start, end) \ + ((u32)FLD_GET(dispc_vp_read((dispc), (vp), (idx)), (start), (end))) =20 -static void VP_REG_FLD_MOD(struct dispc_device *dispc, u32 vp, u32 idx, u3= 2 val, - u32 start, u32 end) -{ - dispc_vp_write(dispc, vp, idx, FLD_MOD(dispc_vp_read(dispc, vp, idx), - val, start, end)); -} +#define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ + ({ \ + struct dispc_device *_dispc =3D (dispc); \ + u32 _vp =3D (vp); \ + u32 _idx =3D (idx); \ + u32 _curr =3D dispc_vp_read(_dispc, _vp, _idx); \ + u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ + dispc_vp_write(_dispc, _vp, _idx, _new); \ + }) =20 -static void OVR_REG_FLD_MOD(struct dispc_device *dispc, u32 ovr, u32 idx, - u32 val, u32 start, u32 end) -{ - dispc_ovr_write(dispc, ovr, idx, - FLD_MOD(dispc_ovr_read(dispc, ovr, idx), - val, start, end)); -} +#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ + ({ \ + struct dispc_device *_dispc =3D (dispc); \ + u32 _ovr =3D (ovr); \ + u32 _idx =3D (idx); \ + u32 _curr =3D dispc_ovr_read(_dispc, _ovr, _idx); \ + u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ + dispc_ovr_write(_dispc, _ovr, _idx, _new); \ + }) =20 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { dispc_irq_t vp_stat =3D 0; =20 --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23B98261593 for ; Wed, 20 Aug 2025 14:02:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698530; cv=none; b=IeDWaSNCJy0xhUN9QSEty90xetIROkwmHWg2Ctdy+n6UWSL5R+p39nUrlnaJsM3LYp+lfcjPbLmaSwvM8GcAWyYMl2sXKsswz0/fwtLVcNnJ7+/g3njpenE7fIxLpsEg6m8sI+gp+aguFxfQyqgDeN5vgWE/XwZgEFCq27NcYko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698530; c=relaxed/simple; bh=IIsNedq+iyblpRYlMXmp6+zZ9khsNh/7IwMpr1pIVrc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dpVVlaVC/4nG/HYDaNv+dOU/LQq7JMM7JIXjMulbuhvMKwMzobZtQpu8hocmrHht/Egt76ayk26cAnfHitVcEdrosI4TxJmesan1FiPnfBuVjrgrv6FnnqZmTLeWcvpFIE/zG1Qpnd+LK1HIlxR2PAv7NV03bDseXnS0DJszZ4A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=oxd2C/zb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="oxd2C/zb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5AE46C4CEE7; Wed, 20 Aug 2025 14:02:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698529; bh=IIsNedq+iyblpRYlMXmp6+zZ9khsNh/7IwMpr1pIVrc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=oxd2C/zbpQbbcuqDiyV0Owp8XvGtgKTQJr+SZu6qgOV2YH3sQi2uAx/y/LR+YTDPS tJ9bff8uMeTfdVXzeQYGwOEs8ptbI0ADL2lX6sbpVRT4l2RI2CX6QzI5tOA45pqB6E doBWzjrG4uvhGs0sYnDHWFMwjI5AYR6+2SCvTAfnTGYIZwibtWlXZAYPz0ogZaMJVZ Cya2A6XMCkkdvIZKJor4OoqwmhYTrecRw185ZgL/N9h1teEbFJtzSIM8pHIldpwrXy OSH/PfYRUtaO8tqh8siJyr/K4CluEIfwdUK0sUFybLe9i+ORpSe2s7yIKHgL+NGuO4 At9vHJwHw9zLw== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:43 +0200 Subject: [PATCH v2 03/14] drm/tidss: dispc: Switch to GENMASK instead of FLD_MASK Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-3-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1844; i=mripard@kernel.org; h=from:subject:message-id; bh=IIsNedq+iyblpRYlMXmp6+zZ9khsNh/7IwMpr1pIVrc=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwY83fSQv9ujNnwWy7OqrjkLq405mw1ZdywqShG/f t5lYnRjx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZjI1TmMteL88+ZWrbkb+fxt 6DU7JpUNScpBXazBqamxNkuv2fEtk95jGbGPfd4jhspcvu6TQu9fMlazS5vceGxtOU200s59ucn hsl+vQor0jqetW6pcusjUv3Spr/XdnK3qadKZ+4Wz2J88XgsA X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The dispc FLD_MASK function is an exact equivalent of the GENMASK macro. Let's convert the dispc driver to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 10fbc99621c149f4e119ef4a45867c369ca5df0b..929c9e3ac1174df68937afd86f1= 3bda4e3a66394 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,35 +607,28 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_MASK(start, end) \ - ({ \ - int _end_inner =3D (end); \ - u32 _mask =3D ((1 << ((start) - _end_inner + 1)) - 1) << _end_inner; \ - _mask; \ - }) - #define FLD_VAL(val, start, end) \ ({ \ int _end_inner =3D (end); \ - u32 _new_val =3D ((val) << _end_inner) & FLD_MASK((start), _end_inner); \ + u32 _new_val =3D ((val) << _end_inner) & GENMASK((start), _end_inner); \ _new_val; \ }) =20 #define FLD_GET(val, start, end) \ ({ \ int _end =3D (end); \ - u32 _ret_val =3D ((val) & FLD_MASK((start), _end)) >> _end; \ + u32 _ret_val =3D ((val) & GENMASK((start), _end)) >> _end; \ _ret_val; \ }) =20 #define FLD_MOD(orig, val, start, end) \ ({ \ int _start =3D (start), _end =3D (end); \ - u32 _masked_val =3D (orig) & ~FLD_MASK(_start, _end); \ + u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ u32 _new_val =3D _masked_val | FLD_VAL((val), _start, _end); \ _new_val; \ }) =20 #define REG_GET(dispc, idx, start, end) \ --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0AA0326F45A for ; Wed, 20 Aug 2025 14:02:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698533; cv=none; b=E1WbUJrR6cBX/KAZd/tg0p7jEuFu6XV5J0hmItQaMGfYI6FHRgJYCPL/UG4BzOuG9nEtfHVQqFvsPjzGumYYgG6JVUbNXmo42itVVIUvmtlby5AaqgLOuMqlrFlcOCUs183MTwVcPp8fOpntBdKmZ/RFjZlx1SmAZ37P4EkwYmA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698533; c=relaxed/simple; bh=3tToQxPuD+Y+SqYGY3q3oiIhiOifongn+nBP/XX4RXc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ovFU5kg8h/jXzHj6THZyWnsLxaX7OON6OuIuE14b8Btpq+F9LbSpkRE8liF/UDJyUe/QzIblxGFHCqbLqo5MZuZe5GOYLngv95Lv0UTXvSaUuN/VOTURh/v8CZwL0RHRJ0p7OzOdtxSkJbBu4+IN+KGc3roH78lKf2KPwVwHy44= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=g1DX8RTu; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="g1DX8RTu" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 31C2AC116B1; Wed, 20 Aug 2025 14:02:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698532; bh=3tToQxPuD+Y+SqYGY3q3oiIhiOifongn+nBP/XX4RXc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=g1DX8RTu8fwBrDLssJQyt5TEyZD9fZ36GSf2wIzgYcdZL3mtWmusx3jLlgP3S/YdR bFNAsbB34ZrW11HLTMYhSHpkZTuVekNPGkWbK99LBvbnWYpQHJiLdpGKfhutgc5cY9 aDm4O2RE/N9xJERc3Hwuh9CCkCUGWw84j0BfW7wsnOi0SeCEB1K8xQ9/+0e4T0tLKD ibtpRfBPLCgnshZymACHg+8bok7uvhLThst0WkAv5NtAi41nHOtoBfJqRaECPrQVFt wUiF05X7LCNvrlB62IWxBmEdga8XHPveoxxMyiBKDO+tcJ+hd/eJpXlsfWM9v4LWPQ 3YDSzXmYoDrvA== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:44 +0200 Subject: [PATCH v2 04/14] drm/tidss: dispc: Get rid of FLD_VAL Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-4-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=7248; i=mripard@kernel.org; h=from:subject:message-id; bh=3tToQxPuD+Y+SqYGY3q3oiIhiOifongn+nBP/XX4RXc=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwa0dG4LEWf6sVR/xopDIY6bdvzSvfVf/n+n9P7ZO U1c1rYxHVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAi57wY60M8tr7YvJkv75ay nb64tfrqzJrM/DvaOusU3JuXnYn/uyV5xVGBXZVb+9hKb9tOePksn7FOv8XnePDGuYueqn9fv3S /cNMRdaeJlmrLYs6H3juYE/fusscVq0v9x6JvvM17I+Yd9tIOAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_VAL function is an equivalent to what FIELD_PREP + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 58 +++++++++++++++++----------------= ---- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 929c9e3ac1174df68937afd86f13bda4e3a66394..f0568ae3e7bebf481bb5f6d0603= dae4b6e6a0729 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,17 +607,10 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_VAL(val, start, end) \ - ({ \ - int _end_inner =3D (end); \ - u32 _new_val =3D ((val) << _end_inner) & GENMASK((start), _end_inner); \ - _new_val; \ - }) - #define FLD_GET(val, start, end) \ ({ \ int _end =3D (end); \ u32 _ret_val =3D ((val) & GENMASK((start), _end)) >> _end; \ _ret_val; \ @@ -625,11 +618,11 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) =20 #define FLD_MOD(orig, val, start, end) \ ({ \ int _start =3D (start), _end =3D (end); \ u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ - u32 _new_val =3D _masked_val | FLD_VAL((val), _start, _end); \ + u32 _new_val =3D _masked_val | FIELD_PREP(GENMASK(_start, _end), (val));= \ _new_val; \ }) =20 #define REG_GET(dispc, idx, start, end) \ ((u32)FLD_GET(dispc_read((dispc), (idx)), (start), (end))) @@ -1233,18 +1226,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, vfp =3D mode->vsync_start - mode->vdisplay; vsw =3D mode->vsync_end - mode->vsync_start; vbp =3D mode->vtotal - mode->vsync_end; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, - FLD_VAL(hsw - 1, 7, 0) | - FLD_VAL(hfp - 1, 19, 8) | - FLD_VAL(hbp - 1, 31, 20)); + FIELD_PREP(GENMASK(7, 0), hsw - 1) | + FIELD_PREP(GENMASK(19, 8), hfp - 1) | + FIELD_PREP(GENMASK(31, 20), hbp - 1)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, - FLD_VAL(vsw - 1, 7, 0) | - FLD_VAL(vfp, 19, 8) | - FLD_VAL(vbp, 31, 20)); + FIELD_PREP(GENMASK(7, 0), vsw - 1) | + FIELD_PREP(GENMASK(19, 8), vfp) | + FIELD_PREP(GENMASK(31, 20), vbp)); =20 ivs =3D !!(mode->flags & DRM_MODE_FLAG_NVSYNC); =20 ihs =3D !!(mode->flags & DRM_MODE_FLAG_NHSYNC); =20 @@ -1263,21 +1256,21 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, /* always use DE_HIGH for OLDI */ if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) ieo =3D false; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, - FLD_VAL(align, 18, 18) | - FLD_VAL(onoff, 17, 17) | - FLD_VAL(rf, 16, 16) | - FLD_VAL(ieo, 15, 15) | - FLD_VAL(ipc, 14, 14) | - FLD_VAL(ihs, 13, 13) | - FLD_VAL(ivs, 12, 12)); + FIELD_PREP(GENMASK(18, 18), align) | + FIELD_PREP(GENMASK(17, 17), onoff) | + FIELD_PREP(GENMASK(16, 16), rf) | + FIELD_PREP(GENMASK(15, 15), ieo) | + FIELD_PREP(GENMASK(14, 14), ipc) | + FIELD_PREP(GENMASK(13, 13), ihs) | + FIELD_PREP(GENMASK(12, 12), ivs)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, - FLD_VAL(mode->hdisplay - 1, 11, 0) | - FLD_VAL(mode->vdisplay - 1, 27, 16)); + FIELD_PREP(GENMASK(11, 0), mode->hdisplay - 1) | + FIELD_PREP(GENMASK(27, 16), mode->vdisplay - 1)); =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) @@ -1589,18 +1582,18 @@ struct dispc_csc_coef { #define DISPC_CSC_REGVAL_LEN 8 =20 static void dispc_csc_offset_regval(const struct dispc_csc_coef *csc, u32 *regval) { -#define OVAL(x, y) (FLD_VAL(x, 15, 3) | FLD_VAL(y, 31, 19)) +#define OVAL(x, y) (FIELD_PREP(GENMASK(15, 3), x) | FIELD_PREP(GENMASK(31,= 19), y)) regval[5] =3D OVAL(csc->preoffset[0], csc->preoffset[1]); regval[6] =3D OVAL(csc->preoffset[2], csc->postoffset[0]); regval[7] =3D OVAL(csc->postoffset[1], csc->postoffset[2]); #undef OVAL } =20 -#define CVAL(x, y) (FLD_VAL(x, 10, 0) | FLD_VAL(y, 26, 16)) +#define CVAL(x, y) (FIELD_PREP(GENMASK(10, 0), x) | FIELD_PREP(GENMASK(26,= 16), y)) static void dispc_csc_yuv2rgb_regval(const struct dispc_csc_coef *csc, u32 *regva= l) { regval[0] =3D CVAL(csc->m[CSC_RY], csc->m[CSC_RCR]); regval[1] =3D CVAL(csc->m[CSC_RCB], csc->m[CSC_GY]); @@ -1835,11 +1828,12 @@ static void dispc_vid_write_fir_coefs(struct dispc_= device *dispc, s16 c1, c2; u32 c12; =20 c1 =3D coefs->c1[phase]; c2 =3D coefs->c2[phase]; - c12 =3D FLD_VAL(c1, 19, 10) | FLD_VAL(c2, 29, 20); + c12 =3D FIELD_PREP(GENMASK(19, 10), c1) | FIELD_PREP(GENMASK(29, 20), + c2); =20 dispc_vid_write(dispc, hw_plane, reg, c12); } } =20 @@ -2333,18 +2327,18 @@ static u32 dispc_vid_get_fifo_size(struct dispc_dev= ice *dispc, u32 hw_plane) =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, - FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); + FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); } =20 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, - FLD_VAL(high, 31, 16) | FLD_VAL(low, 15, 0)); + FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); } =20 static void dispc_k2g_plane_init(struct dispc_device *dispc) { unsigned int hw_plane; @@ -2481,12 +2475,12 @@ static void dispc_initial_config(struct dispc_devic= e *dispc) dispc_vp_init(dispc); =20 /* Note: Hardcoded DPI routing on J721E for now */ if (dispc->feat->subrev =3D=3D DISPC_J721E) { dispc_write(dispc, DISPC_CONNECTIONS, - FLD_VAL(2, 3, 0) | /* VP1 to DPI0 */ - FLD_VAL(8, 7, 4) /* VP3 to DPI1 */ + FIELD_PREP(GENMASK(3, 0), 2) | /* VP1 to DPI0 */ + FIELD_PREP(GENMASK(7, 4), 8) /* VP3 to DPI1 */ ); } } =20 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, @@ -2660,12 +2654,12 @@ static void dispc_k2g_cpr_from_ctm(const struct drm= _color_ctm *ctm, cpr->m[CSC_BR] =3D dispc_S31_32_to_s2_8(ctm->matrix[6]); cpr->m[CSC_BG] =3D dispc_S31_32_to_s2_8(ctm->matrix[7]); cpr->m[CSC_BB] =3D dispc_S31_32_to_s2_8(ctm->matrix[8]); } =20 -#define CVAL(xR, xG, xB) (FLD_VAL(xR, 9, 0) | FLD_VAL(xG, 20, 11) | \ - FLD_VAL(xB, 31, 22)) +#define CVAL(xR, xG, xB) (FIELD_PREP(GENMASK(9, 0), xR) | FIELD_PREP(GENMA= SK(20, 11), xG) | \ + FIELD_PREP(GENMASK(31, 22), xB)) =20 static void dispc_k2g_vp_csc_cpr_regval(const struct dispc_csc_coef *csc, u32 *regval) { regval[0] =3D CVAL(csc->m[CSC_BB], csc->m[CSC_BG], csc->m[CSC_BR]); --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFEFE2701BD for ; Wed, 20 Aug 2025 14:02:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698535; cv=none; b=EVayUJtmhD37h1FzpJVk4Ih5VwVMIaOEuhNnLY/yosst8P9DDfJJ3mV3QnDPIifaBHGZVhA7HY+V/KFJvCqja53Rng1ST0Ann4naPs2mGXiIR+kvrEjQ9qXHrEzsWOeUSEuyzNNk9G7eAcTD0I27mIKYRBYM5onFdze9Qew8daA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698535; c=relaxed/simple; bh=xyR3hzCpzN87ckPVufv/z6ICYQymJ/j3pasff2hbc8k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=dRq6rCTRONISONeE554B/weIaepCqmzMYbd1lZGXmUm2LRxjolhJZZJteNDvNPLuiPD+NnFybOyKqw66QSjbtAKgAxPTRPuvbTJNlQexiMc+zzzhlNHJtz6iuGQRk45ToCtcQliFRVWUkaNcbPKWG6Nj3DkzoqiT6b42DZ+zMTY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TYtB5ErV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TYtB5ErV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 33792C116B1; Wed, 20 Aug 2025 14:02:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698535; bh=xyR3hzCpzN87ckPVufv/z6ICYQymJ/j3pasff2hbc8k=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TYtB5ErV4fvxUwUxFJdJId2zr4XBuc+JrtK7H0dcbG87jLZxnFqhn08D2PbKm5hgx poglS74XNq2VihtZYxWkjH6S+BG8wcOLhnIOWIninDGSDjJwMuwHDNhcK0LwcV/5JG hTFRir9avfl5Dl4FykZkCHiKPnvbw4u0MBLW+EAjhOtAbhE3P8gCKBi4HZ6N4ISdaH b4efDa0Zev8Ve7okv9Mpr9t1ZyMbmy8DTGPTOJHDn4vfF9+TskvHezE/YUb91oqfex poais4zzx/orSdloDy1f+C/uSPTE0Im3m49T48t4yK5My4ocoL7uw8mvM3cpihre3F q2EaLGxnStl4w== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:45 +0200 Subject: [PATCH v2 05/14] drm/tidss: dispc: Get rid of FLD_GET Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-5-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2757; i=mripard@kernel.org; h=from:subject:message-id; bh=xyR3hzCpzN87ckPVufv/z6ICYQymJ/j3pasff2hbc8k=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwZO3H+oSXbpEQGj9O627Ck3Vs7TSvW5zeYyUe7JH W9Gps98HVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAi97gZ612lrjjfNqp/cH67 y+opQnvFXvcoPZ6z9lxA3ceTDycz8voYstlNj4/oT/jxe2H9TFnhNYwN1222Bb3fqLXYdKK5T5i LeUnGbEWZH0/LYpJfC2nPaWDZHuqz/DGrkdtfoQ2XzldJvy8GAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_GET function is an equivalent to what FIELD_GET + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index f0568ae3e7bebf481bb5f6d0603dae4b6e6a0729..50d5eda0670e6e090d05af6a2c0= 5e5b88f28c322 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,27 +607,21 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_GET(val, start, end) \ - ({ \ - int _end =3D (end); \ - u32 _ret_val =3D ((val) & GENMASK((start), _end)) >> _end; \ - _ret_val; \ - }) - #define FLD_MOD(orig, val, start, end) \ ({ \ int _start =3D (start), _end =3D (end); \ u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ u32 _new_val =3D _masked_val | FIELD_PREP(GENMASK(_start, _end), (val));= \ _new_val; \ }) =20 #define REG_GET(dispc, idx, start, end) \ - ((u32)FLD_GET(dispc_read((dispc), (idx)), (start), (end))) + ((u32)FIELD_GET(GENMASK((start), (end)), \ + dispc_read((dispc), (idx)))) =20 #define REG_FLD_MOD(dispc, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _idx =3D (idx); \ @@ -635,11 +629,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ dispc_write(_dispc, _idx, _new); \ }) =20 #define VID_REG_GET(dispc, hw_plane, idx, start, end) \ - ((u32)FLD_GET(dispc_vid_read((dispc), (hw_plane), (idx)), (start), (end))) + ((u32)FIELD_GET(GENMASK((start), (end)), \ + dispc_vid_read((dispc), (hw_plane), (idx)))) =20 #define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ @@ -648,11 +643,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ dispc_vid_write(_dispc, _hw_plane, _idx, _new); \ }) =20 #define VP_REG_GET(dispc, vp, idx, start, end) \ - ((u32)FLD_GET(dispc_vp_read((dispc), (vp), (idx)), (start), (end))) + ((u32)FIELD_GET(GENMASK((start), (end)), \ + dispc_vp_read((dispc), (vp), (idx)))) =20 #define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _vp =3D (vp); \ --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56BE32749D6 for ; Wed, 20 Aug 2025 14:02:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698538; cv=none; b=giRhDHCfjk01tZG8fa7/wmvyRYM+mAtpT5Puj5BdHri24biyxVcUnfbRcxblYQd9v9HdLdVU/HpHderFswWp4zEg73uJN8ZP9CLV1BXp4LP9RZeCFFcQ3005kyY5SY/nLsaHSfUc8S0qttqNJMd3tvDGiyj5GsrFJjWHckNCaP8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698538; c=relaxed/simple; bh=EYMqfrY9ZLQjH+7eX0m9uico3jmwKgGSQ3eRF+qyzw0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ZWHUYofa5w2lJKcjae5RUoyifO8ucyobx5z8Z/JFKuwVfwfOCe4knbmv2n9oObGl8W3jB8YQrNa/SeuKOflvCXncOwz497A0RYw11gT5cXvP38Oc+02dXgOa0fPmJEdvs1EqM8v8/lfgphz7pqpdKvU4mmOGhDUdwjQn6k4Yh3c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=WK895sny; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="WK895sny" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D50ADC4CEE7; Wed, 20 Aug 2025 14:02:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698538; bh=EYMqfrY9ZLQjH+7eX0m9uico3jmwKgGSQ3eRF+qyzw0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=WK895snyqq/N5zCQh83kCj09qAAG14QGtfQhyP/IgxwhqoEbZskKEKGlBS1A4Yk8I GP5NQYxs63cfjlIf8qLVs7VpC6cj7pPEV3wM0oyIfjAR3wIeXhugNdTRo71SLDGQ9N /ZwOdQBWt90qGXm8P3RkhKueU+IpJZyIxHCdfqKULsgWZCJ2mP8sahQNysl/WHuc5z CFzI1U39Pu7aROdECmJ2es8RrSsYwnaiavPFMz7t3lzAjcFkvC5pUlRafuX85chZ2S vjFrJGHmoSO9RoLgdgd4xwPloVXYj2ZJs5JMQ4+vM3jTG6+epxjOkeVRGulGq6440n dGydj8SiEY9GA== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:46 +0200 Subject: [PATCH v2 06/14] drm/tidss: dispc: Get rid of FLD_MOD Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-6-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4304; i=mripard@kernel.org; h=from:subject:message-id; bh=EYMqfrY9ZLQjH+7eX0m9uico3jmwKgGSQ3eRF+qyzw0=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwaWBYb3rdowN/3+lIPTU3RXc7H9/eYZUvSC+Y3r7 F5BfYYrHVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAiwtyM9TlfzTc2Tej3Sdm/ 2+HAguTzfu+clG5VPf4X27LVZkNSjvwz7gvhSge7WB5YMm98XbZqI2PDsvvHlxRt5X53dlqC0cW 1FmuY+U13apc6T3qRWP4gsLnLfpPcSb4/qSausjeOm65sYtsIAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The FLD_MOD function is an equivalent to what FIELD_MODIFY + GENMASK provide, so let's drop it and switch to the latter. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 36 ++++++++++++++-------------------= --- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 50d5eda0670e6e090d05af6a2c05e5b88f28c322..fef56aed3f6edb6630d079f3548= 21ada5fad327d 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,29 +607,21 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define FLD_MOD(orig, val, start, end) \ - ({ \ - int _start =3D (start), _end =3D (end); \ - u32 _masked_val =3D (orig) & ~GENMASK(_start, _end); \ - u32 _new_val =3D _masked_val | FIELD_PREP(GENMASK(_start, _end), (val));= \ - _new_val; \ - }) - #define REG_GET(dispc, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ dispc_read((dispc), (idx)))) =20 #define REG_FLD_MOD(dispc, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _idx =3D (idx); \ - u32 _curr =3D dispc_read(_dispc, _idx); \ - u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ - dispc_write(_dispc, _idx, _new); \ + u32 _reg =3D dispc_read(_dispc, _idx); \ + FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + dispc_write(_dispc, _idx, _reg); \ }) =20 #define VID_REG_GET(dispc, hw_plane, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ dispc_vid_read((dispc), (hw_plane), (idx)))) @@ -637,13 +629,13 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) #define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ u32 _idx =3D (idx); \ - u32 _curr =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ - u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ - dispc_vid_write(_dispc, _hw_plane, _idx, _new); \ + u32 _reg =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ + FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \ }) =20 #define VP_REG_GET(dispc, vp, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ dispc_vp_read((dispc), (vp), (idx)))) @@ -651,23 +643,23 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) #define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _vp =3D (vp); \ u32 _idx =3D (idx); \ - u32 _curr =3D dispc_vp_read(_dispc, _vp, _idx); \ - u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ - dispc_vp_write(_dispc, _vp, _idx, _new); \ + u32 _reg =3D dispc_vp_read(_dispc, _vp, _idx); \ + FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + dispc_vp_write(_dispc, _vp, _idx, _reg); \ }) =20 #define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ - u32 _ovr =3D (ovr); \ + u32 _ovr =3D (ovr); \ u32 _idx =3D (idx); \ - u32 _curr =3D dispc_ovr_read(_dispc, _ovr, _idx); \ - u32 _new =3D FLD_MOD(_curr, (val), (start), (end)); \ - dispc_ovr_write(_dispc, _ovr, _idx, _new); \ + u32 _reg =3D dispc_ovr_read(_dispc, _ovr, _idx); \ + FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + dispc_ovr_write(_dispc, _ovr, _idx, _reg); \ }) =20 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { dispc_irq_t vp_stat =3D 0; @@ -1160,11 +1152,11 @@ static void dispc_enable_am65x_oldi(struct dispc_de= vice *dispc, u32 hw_videoport dev_warn(dispc->dev, "%s: %d port width not supported\n", __func__, fmt->data_width); =20 oldi_cfg |=3D BIT(7); /* DEPOL */ =20 - oldi_cfg =3D FLD_MOD(oldi_cfg, fmt->am65x_oldi_mode_reg_val, 3, 1); + FIELD_MODIFY(GENMASK(3, 1), &oldi_cfg, fmt->am65x_oldi_mode_reg_val); =20 oldi_cfg |=3D BIT(12); /* SOFTRST */ =20 oldi_cfg |=3D BIT(0); /* ENABLE */ =20 --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F38E0275AE6 for ; Wed, 20 Aug 2025 14:02:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698541; cv=none; b=MmUoUIvTOt9BqfPsfGWEDGLLpp2G8p3AuXXRaSnQM3L3PPwqsIYaLzrmN/jw5B+yNH6FuEuOQOoMAvILXy1F1pYaHmLxFkcMckcsMCvxgCOcpQvOKqeWTaJl+M4yyENxvlomtVX5IfCXqIT9QjU3dwB7U3PLoUJwbIoXHrZ8U4Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698541; c=relaxed/simple; bh=NPKE0HzA70wlsc3DhdEGt6RObPp32ugchgS24Nhjfqc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jNGCJh4/cWKw3ftkiGhVOZ5AoUg51WJmF49Eb+evOuTtBOw7Vpu3RuJ7cAwGCCWzWYwAd/gBSAF3A2spnpd6JnJA6imhafS1IYRM9U6YOE2Pvdg1jg55CNzDHpmDE/hHfqUNt6tQb1qitnxV1ejBeK42NAEh7YBJJBhOzIAvAXI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eyDTCNW1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eyDTCNW1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7B6F7C4CEE7; Wed, 20 Aug 2025 14:02:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698540; bh=NPKE0HzA70wlsc3DhdEGt6RObPp32ugchgS24Nhjfqc=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=eyDTCNW1qws1n3jaCS7qXvN4ke3vb7HK6sJyxhs7xW2YIDg4upsMipqf4chm0zGC8 fjy59+HFTOhk9mfbrdLqDa6NMOsIspgScpx+oDlxvpP8AT1nSkuUuSUyj7ZGKDAxHQ LFCcGyyDQkGJR2pV1pSTxG37TTxj0nw4Vtyl5wZfL667ol1iyaZ20Ahg3SIQHabEdo JGdH6MtpTmEHxIhGnSM7Hehvq2qHWD97X7WG7LlLBactyQtXMqPXBGrBc9fufzVSzV i84x/KhrtxHq6qrEGy97W2Caikh8sYmobzFyeMAd+eC+JfNvY5ESiOEyjW07QT60na Zf2Q09vCb86yQ== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:47 +0200 Subject: [PATCH v2 07/14] drm/tidss: dispc: Switch REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-7-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2796; i=mripard@kernel.org; h=from:subject:message-id; bh=NPKE0HzA70wlsc3DhdEGt6RObPp32ugchgS24Nhjfqc=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwZ9C2JYHPY2SiZeuyJx3fGWg8H1ui8zHY5ceX9NR mVRfK9vx1QWBmFOBlkxRZYnMmGnl7cvrnKwX/kDZg4rE8gQBi5OAZjIbC/Geu8PJ7331OYxNyq8 eZnO+W6qy67Ln0ssyhh09S+civGcW6O/KthwQtqzw1ZMewQDi2UfMDYc3HX07xUBgfWuXW+6pmn cckpnMGz9fGb9t+2zp8U/3qtfta9gcenu3m670kpJR+WCBVcB X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index fef56aed3f6edb6630d079f354821ada5fad327d..807ab0e0afc7f95efe55764dcb0= 8da695fb85963 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -607,13 +607,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) /* * TRM gives bitfields as start:end, where start is the higher bit * number. For example 7:0 */ =20 -#define REG_GET(dispc, idx, start, end) \ - ((u32)FIELD_GET(GENMASK((start), (end)), \ - dispc_read((dispc), (idx)))) +#define REG_GET(dispc, idx, mask) \ + ((u32)FIELD_GET((mask), dispc_read((dispc), (idx)))) =20 #define REG_FLD_MOD(dispc, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _idx =3D (idx); \ @@ -2807,30 +2806,30 @@ int dispc_runtime_resume(struct dispc_device *dispc) { dev_dbg(dispc->dev, "resume\n"); =20 clk_prepare_enable(dispc->fclk); =20 - if (REG_GET(dispc, DSS_SYSSTATUS, 0, 0) =3D=3D 0) + if (REG_GET(dispc, DSS_SYSSTATUS, GENMASK(0, 0)) =3D=3D 0) dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); =20 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", dispc_read(dispc, DSS_REVISION)); =20 dev_dbg(dispc->dev, "VP RESETDONE %d,%d,%d\n", - REG_GET(dispc, DSS_SYSSTATUS, 1, 1), - REG_GET(dispc, DSS_SYSSTATUS, 2, 2), - REG_GET(dispc, DSS_SYSSTATUS, 3, 3)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(1, 1)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(2, 2)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(3, 3))); =20 if (dispc->feat->subrev =3D=3D DISPC_AM625 || dispc->feat->subrev =3D=3D DISPC_AM65X) dev_dbg(dispc->dev, "OLDI RESETDONE %d,%d,%d\n", - REG_GET(dispc, DSS_SYSSTATUS, 5, 5), - REG_GET(dispc, DSS_SYSSTATUS, 6, 6), - REG_GET(dispc, DSS_SYSSTATUS, 7, 7)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(5, 5)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(6, 6)), + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(7, 7))); =20 dev_dbg(dispc->dev, "DISPC IDLE %d\n", - REG_GET(dispc, DSS_SYSSTATUS, 9, 9)); + REG_GET(dispc, DSS_SYSSTATUS, GENMASK(9, 9))); =20 dispc_initial_config(dispc); =20 dispc->is_enabled =3D true; =20 --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B11972D94AF for ; Wed, 20 Aug 2025 14:02:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698543; cv=none; b=qrqXHrH/2B/xfe3P22HJzOSwOQdxlHQZbliDojJ3swzPlO7ZdGDReQJQZwBNy4I6aTBA4ZsLPG4V1v9E5THOddaotH0qJuRxLs9RYI3emZODSYALlXSHJ6DybdHxpIUuPIfkVUF2bvp0HSIr/VvmZifE0qJKMAv0Qxv7EV39/7E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698543; c=relaxed/simple; bh=tyf4QDY+Y4oRSzMu6QcNi4jQbxuRHQzh39N7pPTYBIs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BeeZo5r2r19S4GPGrE7nb35mz5Df/Dgdv4I34TphCUWuGXcN5+Tq4BBdWWj1I/3AZ8dC6Ocy/mIAszucXSFuyq55tF9r+10k/hMraVXPwrgYhdVpN2oLvVehLwO1C2jO86VidPZkjXUJyfsH1LH554+f1dW4dDSOKVwoQerFzp0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=s6V6YnOd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="s6V6YnOd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 42638C4CEEB; Wed, 20 Aug 2025 14:02:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698543; bh=tyf4QDY+Y4oRSzMu6QcNi4jQbxuRHQzh39N7pPTYBIs=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=s6V6YnOdlR5+JjRMoQ1GMMzPzsrMgp3wILKvNTK9eE18JA6G7mrm0/EkPdV638M9r usqzjuaI/wX/HAI1Djrxrrta6awmnOWEjUenoou5tZ+CTFUkSKC4G/9rjxa5I0F3ni HNmSCoFcdMYcsUvECR8G5ETa57jbV3N1fVS+SgNdKcINEkasjwgY4N7/Wu+ewDSz7c /sO6q8S5CWj6D11CvXlSwybJpiswcQV5kK5kijw0vuLx5faewcR4LyO06Qy23tEcO0 +XQ0/OQjGIZPeJfsccWIk+nXDh/w7ougsYkrU1LYI1rJERDxnu3SndGw0qy8bEFgj9 gW0z6hXg+P+Gg== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:48 +0200 Subject: [PATCH v2 08/14] drm/tidss: dispc: Switch REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-8-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3642; i=mripard@kernel.org; h=from:subject:message-id; bh=tyf4QDY+Y4oRSzMu6QcNi4jQbxuRHQzh39N7pPTYBIs=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwatcfYK4IyYWbxZV+etq3W23tbP0x/dun/rbCiLz XbuY+Z5HVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAir94xNtyurVg6mbMjsFvu 0IkPe/WK/Tv+61tmNkXWnfz4ZOumi1paXM08J7xXWL8rLw6YL/eNhbFO74PiI5c75wJzpA5kCUq s42fe+lH2+ewgmzd6M94aSEk8tJE8y7m/wYRxDufebC6rHYoA X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 807ab0e0afc7f95efe55764dcb08da695fb85963..1b2791e8c04c463552ad370f48d= ce8eae5b94702 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -610,16 +610,16 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) */ =20 #define REG_GET(dispc, idx, mask) \ ((u32)FIELD_GET((mask), dispc_read((dispc), (idx)))) =20 -#define REG_FLD_MOD(dispc, idx, val, start, end) \ +#define REG_FLD_MOD(dispc, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_read(_dispc, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_write(_dispc, _idx, _reg); \ }) =20 #define VID_REG_GET(dispc, hw_plane, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ @@ -2331,13 +2331,13 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) unsigned int hw_plane; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2382,17 +2382,17 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) u32 cba_lo_pri =3D 1; u32 cba_hi_pri =3D 0; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, 2, 0); - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, 5, 3); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, GENMASK(2, 0)); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, GENMASK(5, 3)); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, 1, 0); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, 6, 6); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2916,11 +2916,11 @@ static int dispc_softreset(struct dispc_device *dis= pc) dispc_softreset_k2g(dispc); return 0; } =20 /* Soft reset */ - REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, 1, 1); + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, GENMASK(1, 1)); /* Wait for reset to complete */ ret =3D readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, val, val & 1, 100, 5000); if (ret) { dev_err(dispc->dev, "failed to reset dispc\n"); --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8F73A2E11B0 for ; Wed, 20 Aug 2025 14:02:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698546; cv=none; b=SVVfnkNqhbPusuUcFQWnIGOI/80mOIHVMEOvcASl6psaIfHMH6JRodwRxv/hWI66cQUSU1AgisDN8gonES3L8TeQDrJ9PnigaxXFQtGTiZJEd8eRDmRx+gTz10U1CiahIhHQK2rgkUsdtquOuabyDBKCKVPrQ3tiuKwOO5cUyUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698546; c=relaxed/simple; bh=K3NEYHCQpJ1kDmGIWdG9eDLnXkdpgxdjpAhoq0rNdq4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Kq2mYC58CCbwuw11dqG7cUPPLgX7obcz7rwv3YvQwZizDsA0OcIufkkDKEdbWt/7QQQ+nE21jLBk3yh5n3Yp3q7JoPJYliYjrB/XaMNTxohY9KXwsw2cVdU/8c+ngJ+Cx9bpBXuUYms7yZvH7vkWm5KkjLGlbUPqMgWDssVjdHQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=l2XvW7LP; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="l2XvW7LP" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D82ADC4CEE7; Wed, 20 Aug 2025 14:02:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698546; bh=K3NEYHCQpJ1kDmGIWdG9eDLnXkdpgxdjpAhoq0rNdq4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=l2XvW7LP3E46eF/beH/ZdNih0mOHhbb7/pwUHrv5sN4bb3NaLFefCNQTDnRyr7/ah Mpjr0BCUxkvfCZ1ZQv41BJJ/IqGTQqnv4ZvQyiMA92s6UwwYghQvUpRF6QlU67yZY7 5VLY1f9dF5vL5aFdAaJea/7WYr6sVU0xqQ7M9WlZIMxauVRWZkg1CNv5afg/pidRqI K4/41SzVuvxUqSy3x9ZUXQEyf2n9omgvXao5sE3BaF1KffSTZG/GHN3xqQtcSr7T9G WY5ZErRBt1Z5WjUC7oEnFFVO71Hc8OZMXcXyCh5bc/IUFjyPOrrnGwCWojcLbrkDSE gSjLN1N/y2cwg== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:49 +0200 Subject: [PATCH v2 09/14] drm/tidss: dispc: Switch VID_REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-9-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2081; i=mripard@kernel.org; h=from:subject:message-id; bh=K3NEYHCQpJ1kDmGIWdG9eDLnXkdpgxdjpAhoq0rNdq4=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwZp8FjueuJ54uPav+u7Vi73DpD9ESZmXcoUw/7SI Ghhwce1HVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAiNkKMDTtydMUPx//LdrE1 0vqpmfukOG5dr5LNpfJNu52fu1z9v9fta2Pfro4Vph0Rkos2VXT/Y2y49OnU74+pL8tKNyi4230 UkvAyWsbYzRgzrznvqYuRpMcUZseys+7x/Q9z4qbKvlRmfQ4A X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VID_REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VID_REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 1b2791e8c04c463552ad370f48dce8eae5b94702..b4928cfbb6f7ca9a03371c5e599= e2029baae333f 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -619,13 +619,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _reg =3D dispc_read(_dispc, _idx); \ FIELD_MODIFY((mask), &_reg, (val)); \ dispc_write(_dispc, _idx, _reg); \ }) =20 -#define VID_REG_GET(dispc, hw_plane, idx, start, end) \ - ((u32)FIELD_GET(GENMASK((start), (end)), \ - dispc_vid_read((dispc), (hw_plane), (idx)))) +#define VID_REG_GET(dispc, hw_plane, idx, mask) \ + ((u32)FIELD_GET((mask), dispc_vid_read((dispc), (hw_plane), (idx)))) =20 #define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ @@ -2307,11 +2306,12 @@ void dispc_plane_enable(struct dispc_device *dispc,= u32 hw_plane, bool enable) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { - return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, 15, 0); + return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, + GENMASK(15, 0)); } =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3B9982E5B2F for ; Wed, 20 Aug 2025 14:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698549; cv=none; b=ajQPhRuT7GfvVRY9p87/GdjdofjBw42Olih41a54zBobDaWXOmm00vLNkh/jC2AlCEOXZNoNnMROZFaMnK9vWXmFoB6K+9O5OJ4Vwp15+uaS9Fe+GIsWWdtzVvvgJlwv9+nETjFqtLgvcBfWEVpfvSpI6PsT0D8NxI4+FPXotCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698549; c=relaxed/simple; bh=fDlH7Dl44z2D5Cx4UK14nab6ys1a6BsEEAuxo4ovtjo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oJlWqV6ycaqqKui8C+uPArWocJqztGjQ1RmBMSnNPVWAH6ys+KhEglIn6Esfhh1aUJ2Ko0F6uN/aDBK2b5JO6xT/i4LIaS3V1bVQ0by0zmob8maOemMEAxZYJqAwQkQm48i2upxgR5y1cjdwBJVJ/07SFBr9UswCwZIm3bOSGWk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Vq2C+kqc; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Vq2C+kqc" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70DD2C116B1; Wed, 20 Aug 2025 14:02:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698548; bh=fDlH7Dl44z2D5Cx4UK14nab6ys1a6BsEEAuxo4ovtjo=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Vq2C+kqc7lmG84N+RXhvDjohnx58pl6gc5A8npjjEk6sLc1z4C8TWpcuYvJVAcym/ +cJs/EnWmZ9xPAAFhLD+VD5V+I2iSEYsjIGtc9vKEXGW/WooWlUQ8mwAKgZmZk7E4B /vQSc8wdYfGQvRhyuxlviqzZ4iwGs16O6GYW48QD/gISpIrSeqsY21RFJsIBSynfzU aGjT/l2UPt7vjdB6P2+J5BwvmuB87Ccby1bDf5da58PvuYIINN/E1EnEdvyNPLE2zl gdcESqIA94Lucrux7LXA3HFYVJmCo36zowWRWLjkLBrAT4GLFUtBdCQ09wPZLAnyeC nKTcoZcPA+BeQ== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:50 +0200 Subject: [PATCH v2 10/14] drm/tidss: dispc: Switch VID_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-10-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5234; i=mripard@kernel.org; h=from:subject:message-id; bh=fDlH7Dl44z2D5Cx4UK14nab6ys1a6BsEEAuxo4ovtjo=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwbfsjnd/iBsIsf3p9fmXUkMi558/crGGR5ri29y7 CtwYpOV7pjKwiDMySArpsjyRCbs9PL2xVUO9it/wMxhZQIZwsDFKQATyZ7AWKeVYSl8Om2dJF/P r/32fq6n/K9k3il8s6+uZHHCj+yS0rn/9mx5drU/bZ5+8Cqemu9T5jPWafRIa2w45a2Y7xsYqsL L8sR8pbDqff1Ns1oeHV2Rt+Ygk0PzA9lTuq0qlVrbX1hLyMgDAA== X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VID_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VID_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 32 +++++++++++++++++--------------- 1 file changed, 17 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index b4928cfbb6f7ca9a03371c5e599e2029baae333f..8c0949203ace147e403ea43ab46= 8c3a56d170156 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -622,17 +622,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) }) =20 #define VID_REG_GET(dispc, hw_plane, idx, mask) \ ((u32)FIELD_GET((mask), dispc_vid_read((dispc), (hw_plane), (idx)))) =20 -#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, start, end) \ +#define VID_REG_FLD_MOD(dispc, hw_plane, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _hw_plane =3D (hw_plane); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \ }) =20 #define VP_REG_GET(dispc, vp, idx, start, end) \ ((u32)FIELD_GET(GENMASK((start), (end)), \ @@ -1755,11 +1755,12 @@ static void dispc_vid_csc_setup(struct dispc_device= *dispc, u32 hw_plane, } =20 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 9, 9); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(9, 9)); } =20 /* SCALER */ =20 static u32 dispc_calc_fir_inc(u32 in, u32 out) @@ -2012,24 +2013,24 @@ static void dispc_vid_set_scaling(struct dispc_devi= ce *dispc, u32 hw_plane, struct dispc_scaling_params *sp, u32 fourcc) { /* HORIZONTAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_x, 7, 7); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x, + GENMASK(7, 7)); =20 /* VERTICAL RESIZE ENABLE */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->scale_y, 8, 8); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y, + GENMASK(8, 8)); =20 /* Skip the rest if no scaling is used */ if (!sp->scale_x && !sp->scale_y) return; =20 /* VERTICAL 5-TAPS */ - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, - sp->five_taps, 21, 21); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps, + GENMASK(21, 21)); =20 if (dispc_fourcc_is_yuv(fourcc)) { if (sp->scale_x) { dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, sp->fir_xinc_uv); @@ -2115,11 +2116,11 @@ static void dispc_plane_set_pixel_format(struct dis= pc_device *dispc, =20 for (i =3D 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { if (dispc_color_formats[i].fourcc =3D=3D fourcc) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, dispc_color_formats[i].dss_code, - 6, 1); + GENMASK(6, 1)); return; } } =20 WARN_ON(1); @@ -2293,19 +2294,20 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, 0xFF & (state->alpha >> 8)); =20 if (state->pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 28, 28); + GENMASK(28, 28)); else VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 28, 28); + GENMASK(28, 28)); } =20 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool ena= ble) { - VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, 0, 0); + VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, + GENMASK(0, 0)); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, @@ -2370,11 +2372,11 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) * Prefetch up to fifo high-threshold value to minimize the * possibility of underflows. Note that this means the PRELOAD * register is ignored. */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - 19, 19); + GENMASK(19, 19)); } } =20 static void dispc_k3_plane_init(struct dispc_device *dispc) { @@ -2421,11 +2423,11 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); =20 /* Prefech up to PRELOAD value */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - 19, 19); + GENMASK(19, 19)); } } =20 static void dispc_plane_init(struct dispc_device *dispc) { --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78EB7305056 for ; Wed, 20 Aug 2025 14:02:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698551; cv=none; b=jHJV878uxayCzMJwpVITV67j40EZtmzR7UbYpmcVvgpxQz+uq6eeGdVcLKbPjDOLRCgm+Zefyo9ExZ5q2QBAAalypQWO45xa3GzCk+0tJqXUmpDc0BJbLyzkwc4gYRCo+2yWjUWwnVTJoFawcKFk6/ClsnaKzAxDuv49FMFAzrM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698551; c=relaxed/simple; bh=NV11js6s9srfec80XO+Hoq/5LAEC7NyYVUkzDZjiUhM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=AddlNf4r685k+n4PpeVTiJ/V9rclrgAroNc6Y2xTocqHgtHkj8Ws2E5hAqAhYUN6kRqdUWCmFadTKSg8URT0C+pe9L3hGARoJv6e8E1cPZXqpWpXcgsBS/ZTpLIsHPPKW2ZuuUpb2VfzyAnwM6qJ4gevZBCjaBtLaVdcJct93Yw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TlqKMyud; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TlqKMyud" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0B068C4CEEB; Wed, 20 Aug 2025 14:02:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698551; bh=NV11js6s9srfec80XO+Hoq/5LAEC7NyYVUkzDZjiUhM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=TlqKMyudO837wMokfWbMnB2MQD6MHiLbu7e1S6l2duTSlFQ0tdNROEYwBDFK2lnKH MbVtALB3k0OBm6fBBNV7Qgxf2XtvNq4QytUaMD9Xyg+FHSIbLWo9zsW0o3XaJ6z0Uk 1am30rIfK/AcQnDWODi05LDhJfU+QpwL1LYAyiIIE50etDrgAQypNARnkl4dIqcKGi rqseBkHF/CD9EWkhb2ur78oTo2O3Yk+U8VMXm9RT6e+NVsH0mLMXeKpGlIkCkiZF3X XQ/NFV/B1Fv3qFcO+pga9yhpK7QyKOCLjORmLE4ScBGD2Jz9pAaNUlbPCQsKNFP5lL vrywwxFuzlN3Q== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:51 +0200 Subject: [PATCH v2 11/14] drm/tidss: dispc: Switch VP_REG_GET to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-11-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2215; i=mripard@kernel.org; h=from:subject:message-id; bh=NV11js6s9srfec80XO+Hoq/5LAEC7NyYVUkzDZjiUhM=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLrwbvNbWQlagPSvmeddCVNcvy2+kEp+WVDVYF2f93v UxTSrnSMZWFQZiTQVZMkeWJTNjp5e2LqxzsV/6AmcPKBDKEgYtTACZy5QRjw5ulf1wzst/2L16a UWq/XIBx31kpqSiBhFCffUbzci8m3ZD/XaD6/ZX1VMXGE5c2C1xYzFin2dsxUyhUYDVLgZVuhFn kvC5m1ijn3emhR1tFCtt3RL9rivEuMZJMfWyazGV7JSwnDQA= X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VP_REG_GET function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VP_REG_GET to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 8c0949203ace147e403ea43ab468c3a56d170156..45422fb6038a255b8ba1246762f= 39a4284e5b1d5 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -632,13 +632,12 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _reg =3D dispc_vid_read(_dispc, _hw_plane, _idx); \ FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vid_write(_dispc, _hw_plane, _idx, _reg); \ }) =20 -#define VP_REG_GET(dispc, vp, idx, start, end) \ - ((u32)FIELD_GET(GENMASK((start), (end)), \ - dispc_vp_read((dispc), (vp), (idx)))) +#define VP_REG_GET(dispc, vp, idx, mask) \ + ((u32)FIELD_GET((mask), dispc_vp_read((dispc), (vp), (idx)))) =20 #define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _vp =3D (vp); \ @@ -1273,16 +1272,17 @@ void dispc_vp_unprepare(struct dispc_device *dispc,= u32 hw_videoport) } } =20 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) { - return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5); + return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, + GENMASK(5, 5)); } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { - WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, 5, 5)); + WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5A1ED31CA5C for ; Wed, 20 Aug 2025 14:02:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698554; cv=none; b=hdlIGumuoHgbjRaZmA3T7GNqhsz9kqOSshws5ak+hY/YbpZ2F2xaEqmF6xVHAh+cE2oSCjYZZpdphcVEfGE1iDcsLESFOSdr0rTOHFDFXQ3hPeqRhu7jucgT37Dq4vxcgCfvChXeJZPBUsSAyuiJe3pCeFQF7D5IWwrOWrEeFlc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698554; c=relaxed/simple; bh=b6xJyo18UYS8O7YOE9dEVSSRl/sjpwJiLbl0KFBA/JY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GoVRnR9FX1LM40Xn3n/wPtFz5rAH4gMcBiI20ZNYawRcBzsIBj0lO4MZWy6N9gO+RXib9tgMP5XbcmlXd6bIKmnfNOt+H7pHIJ+1l35rDJRt6ZB07Wru4SWqTENuBt1ZH2tbgIzc9VuACi7rJTkeo9VPT3Rszkz/C99YMPX7UrQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=mDAxE6Eo; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="mDAxE6Eo" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A5A9FC4CEE7; Wed, 20 Aug 2025 14:02:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698554; bh=b6xJyo18UYS8O7YOE9dEVSSRl/sjpwJiLbl0KFBA/JY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mDAxE6EoHibiW3nR5lH0tZnw6styea3YObdfyJfqpLFkcvk3eroH3HhuJ1LcxtL+V w5qRzia5VHNDcKIhh/cRyP5vUqireQxr2FxSqCqbl6M9tmNN8g9RNcFS2VHiYhodOa sPZFUv4Pqr3urRaLrZzsrWb8KD9vYM1jCeJDYOxPJ2S5+/TvChx4b2NW7fDeVylkte ny6h0ImybyJTCgGxyO7DCwFU2lxln8I4VbbkzSKuL78AFnjnaYmh3gD5xdd+G99u5S k4esPOFc3TVrbX7aQzvHXnHpkBdFqfUSmQOtHzRDYArbnwfjDB8Ts0JkP/EqKbO0A8 P+yQBzQJP5llg== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:52 +0200 Subject: [PATCH v2 12/14] drm/tidss: dispc: Switch VP_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-12-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5443; i=mripard@kernel.org; h=from:subject:message-id; bh=b6xJyo18UYS8O7YOE9dEVSSRl/sjpwJiLbl0KFBA/JY=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLr4ZwxRbVPC6p5fihk53SP31H2XuJ0sXL8nJ+T4h54 bXkmfH2jqksDMKcDLJiiixPZMJOL29fXOVgv/IHzBxWJpAhDFycAjCR9zGMDfveck78fmoJ6+tD vpe4Zy5b9HpDR4RX+vSp5fbr7hgvjdud9yuc5emB/SKP/s26fs0oYwpjw/bOgk3T/vb8Wyh2ZPE PuYJ/K4TMUp0NFhv79WhGhNXUNgv+2f4jZ1+iftHsG1px558XAQA= X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The VP_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change VP_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 45422fb6038a255b8ba1246762f39a4284e5b1d5..c5cad1ddcccfbf1d0b6fb53773b= b3aff428ef493 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -635,17 +635,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) }) =20 #define VP_REG_GET(dispc, vp, idx, mask) \ ((u32)FIELD_GET((mask), dispc_vp_read((dispc), (vp), (idx)))) =20 -#define VP_REG_FLD_MOD(dispc, vp, idx, val, start, end) \ +#define VP_REG_FLD_MOD(dispc, vp, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _vp =3D (vp); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_vp_read(_dispc, _vp, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vp_write(_dispc, _vp, _idx, _reg); \ }) =20 #define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ ({ \ @@ -1126,11 +1126,12 @@ static void dispc_set_num_datalines(struct dispc_de= vice *dispc, default: WARN_ON(1); v =3D 3; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, 10, 8); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, + GENMASK(10, 8)); } =20 static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_vid= eoport, const struct dispc_bus_format *fmt) { @@ -1253,16 +1254,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, FIELD_PREP(GENMASK(11, 0), mode->hdisplay - 1) | FIELD_PREP(GENMASK(27, 16), mode->vdisplay - 1)); =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 0, 0); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + GENMASK(0, 0)); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, 0, 0); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, + GENMASK(0, 0)); } =20 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) { if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) { @@ -1279,11 +1282,12 @@ bool dispc_vp_go_busy(struct dispc_device *dispc, u= 32 hw_videoport) } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, 5, 5); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, + GENMASK(5, 5)); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) @@ -2453,11 +2457,11 @@ static void dispc_vp_init(struct dispc_device *disp= c) =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* Enable the gamma Shadow bit-field for all VPs*/ for (i =3D 0; i < dispc->feat->num_vps; i++) - VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, 2, 2); + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, GENMASK(2, 2)); } =20 static void dispc_initial_config(struct dispc_device *dispc) { dispc_plane_init(dispc); @@ -2686,12 +2690,12 @@ static void dispc_k2g_vp_set_ctm(struct dispc_devic= e *dispc, u32 hw_videoport, dispc_k2g_cpr_from_ctm(ctm, &cpr); dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); cprenable =3D 1; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, - cprenable, 15, 15); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, cprenable, + GENMASK(15, 15)); } =20 static s16 dispc_S31_32_to_s3_8(s64 coef) { u64 sign_bit =3D 1ULL << 63; @@ -2752,12 +2756,12 @@ static void dispc_k3_vp_set_ctm(struct dispc_device= *dispc, u32 hw_videoport, dispc_csc_from_ctm(ctm, &csc); dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); colorconvenable =3D 1; } =20 - VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, - colorconvenable, 24, 24); + VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable, + GENMASK(24, 24)); } =20 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state, @@ -2904,11 +2908,12 @@ static void dispc_softreset_k2g(struct dispc_device= *dispc) dispc_set_irqenable(dispc, 0); dispc_read_and_clear_irqstatus(dispc); spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags); =20 for (unsigned int vp_idx =3D 0; vp_idx < dispc->feat->num_vps; ++vp_idx) - VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, 0, 0); + VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, + GENMASK(0, 0)); } =20 static int dispc_softreset(struct dispc_device *dispc) { u32 val; --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9BC031E115 for ; Wed, 20 Aug 2025 14:02:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698556; cv=none; b=BG+bS5uJpu9Qr/7/D+DaZbiccdy0B3RBYQEl6H2It+enjpK7P0ObMytYPQujp9rmx+nTZVaftnu0cg7RdCK8kgqZZLhoT9eI3J6PbsvnT4JIgIWh1nJ5HtbvZOhTL03DGNkQ4fOR8Zjiit25fubKvqxOcauElKR4zuCSDLG+FnY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698556; c=relaxed/simple; bh=s2llZ0k+yYexhA4HqHlu5vUMb5GbEApSzgjjYzPkoHQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GN/Gd5prUFw121oE8BXBT3eCqwkJrhE6iYMmqzdoAu429/Bm8vu/R35bhnqQrWrxvAJEw45x3T6nW++URBt7y58hAzce9vod+zyIgXfRL0Ax+O+FJjjfKIDhLcnMEqrlHnefLR+2/xkHOvNzSxcT7s2O9trfyCyFLWc32Yy1EVE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pwJiw6Pn; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pwJiw6Pn" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4A880C116B1; Wed, 20 Aug 2025 14:02:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698556; bh=s2llZ0k+yYexhA4HqHlu5vUMb5GbEApSzgjjYzPkoHQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=pwJiw6Pns/UXg1TBsc42AYgtcJ9Xatj5vqaukipq2fqO75PKrRH2ikEiN78ORKusW 2W2JPSB5n6CJthc6EHUyOyHo+/pdz1rNSkKTpcBeAMpjzaQj/a4t4tLwNXcBB2WrMj bba4BWlffUtJyVACmYvQ8aof/BqBG3yuyoxNEYJbAo/1Cnx/JEgADjpLmpC/oNpcR/ UNMH4tuGTL/8WnSKQQcCx1SbkAe8w+w79ztydDSF9yQZj2bILb2w+uv68Ww8lgAOI9 nxsGjREHrWRhCKGI9LDYJkX26149AEkZ9zgksuzvS6DG4Kxc1wuzaUq2Ndv2yuFzjH Zynj19z7bg37Q== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:53 +0200 Subject: [PATCH v2 13/14] drm/tidss: dispc: Switch OVR_REG_FLD_MOD to using a mask Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-13-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3457; i=mripard@kernel.org; h=from:subject:message-id; bh=s2llZ0k+yYexhA4HqHlu5vUMb5GbEApSzgjjYzPkoHQ=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLr4bksKTnPg05JSo4OcL9vmPOkWMM51VmBV8V/+ryn vPmxZNhHVNZGIQ5GWTFFFmeyISdXt6+uMrBfuUPmDmsTCBDGLg4BWAiBi8Ya3i5Hm75E71ZpZQv 6MfWYF8tSYboTz4sgTsC7JXP3Fh99XF78Bke2WIVn33NnAlaDb9zGOsMfB70LFis27fTd+melXm WJ1/x6tfaF+seyT7H++zh3fbg6t0C95gZHZzKhFT/TnxfxAoA X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D The OVR_REG_FLD_MOD function takes the start and end bits as parameter and will generate a mask out of them. This makes it difficult to share the masks between callers, since we now need two arguments and to keep them consistent. Let's change OVR_REG_FLD_MOD to take the mask as an argument instead, and let the caller create the mask. Eventually, this mask will be moved to a define. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index c5cad1ddcccfbf1d0b6fb53773bb3aff428ef493..99d3a84a5b40e1e791300199d6b= 3da9a12d11f80 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -645,17 +645,17 @@ void tidss_disable_oldi(struct tidss_device *tidss, u= 32 hw_videoport) u32 _reg =3D dispc_vp_read(_dispc, _vp, _idx); \ FIELD_MODIFY((mask), &_reg, (val)); \ dispc_vp_write(_dispc, _vp, _idx, _reg); \ }) =20 -#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, start, end) \ +#define OVR_REG_FLD_MOD(dispc, ovr, idx, val, mask) \ ({ \ struct dispc_device *_dispc =3D (dispc); \ u32 _ovr =3D (ovr); \ u32 _idx =3D (idx); \ u32 _reg =3D dispc_ovr_read(_dispc, _ovr, _idx); \ - FIELD_MODIFY(GENMASK((start), (end)), &_reg, (val)); \ + FIELD_MODIFY((mask), &_reg, (val)); \ dispc_ovr_write(_dispc, _ovr, _idx, _reg); \ }) =20 static dispc_irq_t dispc_vp_irq_from_raw(u32 stat, u32 hw_videoport) { @@ -1483,29 +1483,29 @@ static void dispc_am65x_ovr_set_plane(struct dispc_= device *dispc, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, 4, 1); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - x, 17, 6); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - y, 30, 19); + hw_id, GENMASK(4, 1)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, + GENMASK(17, 6)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y, + GENMASK(30, 19)); } =20 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, 4, 1); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), - x, 13, 0); - OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), - y, 29, 16); + hw_id, GENMASK(4, 1)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x, + GENMASK(13, 0)); + OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y, + GENMASK(29, 16)); } =20 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { @@ -1536,11 +1536,11 @@ void dispc_ovr_enable_layer(struct dispc_device *di= spc, { if (dispc->feat->subrev =3D=3D DISPC_K2G) return; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - !!enable, 0, 0); + !!enable, GENMASK(0, 0)); } =20 /* CSC */ enum csc_ctm { CSC_RR, CSC_RG, CSC_RB, --=20 2.50.1 From nobody Sat Oct 4 03:15:47 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D49C31E115 for ; Wed, 20 Aug 2025 14:02:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698560; cv=none; b=harrDgDpxEIj0RUkoH46TH+3xUP92sSkl8Atofv3DahSmUJyaSELkaMupr7lXRtvz3Li4Qu7yRwGw17YvGU2bLDhp1hKgwmgEC4KBZiaa476cxvYQnIwyaA5WtRK/KH+xXJ8bFWgTVjZ5yYpdm21/h38pSRJ3fMNlpytecYt4TQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755698560; c=relaxed/simple; bh=1U6td10MZ6Sot3eSolPL6E5L84KYZGzHP6qgsUCCVH4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=evKIWIhckzX8/ajXs+Og5sMrDi3fvPgZuPPRUaWhCIm/vLrbKQQrwpmFkqRtF2GHPwCDjRO/1KwMXJn75DgYc7QnSk5qmuLCCvfVi7x/s8wrHWNajx6BIA3rRMoR7rxfcPw8hSSc6xrk/tRGyxEe2O+Y1q5BbkH2RnBPfLA9UE0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F2Fn2V3O; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F2Fn2V3O" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 36B64C116B1; Wed, 20 Aug 2025 14:02:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755698559; bh=1U6td10MZ6Sot3eSolPL6E5L84KYZGzHP6qgsUCCVH4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=F2Fn2V3O8XeCu6EWYKrxeKRzqngc1yrhMtNC5yzbWBEYHt6TvoMURNIs5Eb5QePBy bP030FnrQYLhansrwhhJJUdp5Hc3SLq607JbEWhzAwG7VqZShitceWDv0PKdFB1vAW cm32pxfSp83lYDgPMwszzFWEOXDOY/6IJqu25q/+tVr9FifQJfrmOxZzXq2QyQxc6z Vgtvtc07hEX5GnEEeg7YHMcNZkj5Mu6eO/Pvk5wJEe2UdgNbTLiPzlWgPqU52GhaSm Vh/otFlQzMQmpqNUgyBJXD6Z4lpXLmNo0Nu7caIpXbUzNudZ7ESOvmjoNX8YCUR7xu XMIDIai31tpHQ== From: Maxime Ripard Date: Wed, 20 Aug 2025 16:01:54 +0200 Subject: [PATCH v2 14/14] drm/tidss: dispc: Define field masks being used Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-drm-tidss-field-api-v2-14-43cab671c648@kernel.org> References: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> In-Reply-To: <20250820-drm-tidss-field-api-v2-0-43cab671c648@kernel.org> To: Jyri Sarha , Tomi Valkeinen , Maarten Lankhorst , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Maxime Ripard X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=27034; i=mripard@kernel.org; h=from:subject:message-id; bh=1U6td10MZ6Sot3eSolPL6E5L84KYZGzHP6qgsUCCVH4=; b=owGbwMvMwCmsHn9OcpHtvjLG02pJDBlLr4aW9++X2+G00vuh2otN0vn/Plb1XVwTkLKyz/6fQ /jbGSabO6ayMAhzMsiKKbI8kQk7vbx9cZWD/cofMHNYmUCGMHBxCsBErI4z1pcq8bwsEwsoijM+ 9lqo8Y2ZftfRauc1Ol/efplXlM67fm5d7WO11gsqx6RXhzFU+fRJMtbKrfbgUDQyeHaac8nMxvS qjSYycfet/2ffFhOIZ3W/c5az9+TyULdZt8Lf6T1+/P/9T18A X-Developer-Key: i=mripard@kernel.org; a=openpgp; fpr=BE5675C37E818C8B5764241C254BCFC56BF6CE8D Now that we have all the accessors taking masks, we can create defines for them and reuse them as needed. It makes the driver easier to read, less prone to consistency issues, and allows to reuse defines when needed. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/tidss/tidss_dispc.c | 137 +++++++++++++++++----------= ---- drivers/gpu/drm/tidss/tidss_dispc_regs.h | 76 +++++++++++++++++ 2 files changed, 152 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/tidss/tidss_dispc.c b/drivers/gpu/drm/tidss/ti= dss_dispc.c index 99d3a84a5b40e1e791300199d6b3da9a12d11f80..246c875160de7cc73b471d4dfc1= b0cdb55c53a05 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc.c +++ b/drivers/gpu/drm/tidss/tidss_dispc.c @@ -1127,11 +1127,11 @@ static void dispc_set_num_datalines(struct dispc_de= vice *dispc, WARN_ON(1); v =3D 3; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, v, - GENMASK(10, 8)); + DISPC_VP_CONTROL_DATALINES_MASK); } =20 static void dispc_enable_am65x_oldi(struct dispc_device *dispc, u32 hw_vid= eoport, const struct dispc_bus_format *fmt) { @@ -1150,11 +1150,12 @@ static void dispc_enable_am65x_oldi(struct dispc_de= vice *dispc, u32 hw_videoport dev_warn(dispc->dev, "%s: %d port width not supported\n", __func__, fmt->data_width); =20 oldi_cfg |=3D BIT(7); /* DEPOL */ =20 - FIELD_MODIFY(GENMASK(3, 1), &oldi_cfg, fmt->am65x_oldi_mode_reg_val); + FIELD_MODIFY(DISPC_VP_DSS_OLDI_CFG_MAP_MASK, &oldi_cfg, + fmt->am65x_oldi_mode_reg_val); =20 oldi_cfg |=3D BIT(12); /* SOFTRST */ =20 oldi_cfg |=3D BIT(0); /* ENABLE */ =20 @@ -1212,18 +1213,18 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, vfp =3D mode->vsync_start - mode->vdisplay; vsw =3D mode->vsync_end - mode->vsync_start; vbp =3D mode->vtotal - mode->vsync_end; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_H, - FIELD_PREP(GENMASK(7, 0), hsw - 1) | - FIELD_PREP(GENMASK(19, 8), hfp - 1) | - FIELD_PREP(GENMASK(31, 20), hbp - 1)); + FIELD_PREP(DISPC_VP_TIMING_H_SYNC_PULSE_MASK, hsw - 1) | + FIELD_PREP(DISPC_VP_TIMING_H_FRONT_PORCH_MASK, hfp - 1) | + FIELD_PREP(DISPC_VP_TIMING_H_BACK_PORCH_MASK, hbp - 1)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_TIMING_V, - FIELD_PREP(GENMASK(7, 0), vsw - 1) | - FIELD_PREP(GENMASK(19, 8), vfp) | - FIELD_PREP(GENMASK(31, 20), vbp)); + FIELD_PREP(DISPC_VP_TIMING_V_SYNC_PULSE_MASK, vsw - 1) | + FIELD_PREP(DISPC_VP_TIMING_V_FRONT_PORCH_MASK, vfp) | + FIELD_PREP(DISPC_VP_TIMING_V_BACK_PORCH_MASK, vbp)); =20 ivs =3D !!(mode->flags & DRM_MODE_FLAG_NVSYNC); =20 ihs =3D !!(mode->flags & DRM_MODE_FLAG_NHSYNC); =20 @@ -1242,30 +1243,30 @@ void dispc_vp_enable(struct dispc_device *dispc, u3= 2 hw_videoport, /* always use DE_HIGH for OLDI */ if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) ieo =3D false; =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_POL_FREQ, - FIELD_PREP(GENMASK(18, 18), align) | - FIELD_PREP(GENMASK(17, 17), onoff) | - FIELD_PREP(GENMASK(16, 16), rf) | - FIELD_PREP(GENMASK(15, 15), ieo) | - FIELD_PREP(GENMASK(14, 14), ipc) | - FIELD_PREP(GENMASK(13, 13), ihs) | - FIELD_PREP(GENMASK(12, 12), ivs)); + FIELD_PREP(DISPC_VP_POL_FREQ_ALIGN_MASK, align) | + FIELD_PREP(DISPC_VP_POL_FREQ_ONOFF_MASK, onoff) | + FIELD_PREP(DISPC_VP_POL_FREQ_RF_MASK, rf) | + FIELD_PREP(DISPC_VP_POL_FREQ_IEO_MASK, ieo) | + FIELD_PREP(DISPC_VP_POL_FREQ_IPC_MASK, ipc) | + FIELD_PREP(DISPC_VP_POL_FREQ_IHS_MASK, ihs) | + FIELD_PREP(DISPC_VP_POL_FREQ_IVS_MASK, ivs)); =20 dispc_vp_write(dispc, hw_videoport, DISPC_VP_SIZE_SCREEN, - FIELD_PREP(GENMASK(11, 0), mode->hdisplay - 1) | - FIELD_PREP(GENMASK(27, 16), mode->vdisplay - 1)); + FIELD_PREP(DISPC_VP_SIZE_SCREEN_HDISPLAY_MASK, mode->hdisplay - 1= ) | + FIELD_PREP(DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK, mode->vdisplay - 1= )); =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport) { VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 0, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport) { if (dispc->feat->vp_bus_type[hw_videoport] =3D=3D DISPC_VP_OLDI_AM65X) { @@ -1276,18 +1277,19 @@ void dispc_vp_unprepare(struct dispc_device *dispc,= u32 hw_videoport) } =20 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport) { return VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, - GENMASK(5, 5)); + DISPC_VP_CONTROL_GOBIT_MASK); } =20 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport) { - WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, GENMASK(5, 5))); + WARN_ON(VP_REG_GET(dispc, hw_videoport, DISPC_VP_CONTROL, + DISPC_VP_CONTROL_GOBIT_MASK)); VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONTROL, 1, - GENMASK(5, 5)); + DISPC_VP_CONTROL_GOBIT_MASK); } =20 enum c8_to_c12_mode { C8_TO_C12_REPLICATE, C8_TO_C12_MAX, C8_TO_C12_MIN }; =20 static u16 c8_to_c12(u8 c8, enum c8_to_c12_mode mode) @@ -1483,29 +1485,29 @@ static void dispc_am65x_ovr_set_plane(struct dispc_= device *dispc, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, GENMASK(4, 1)); + hw_id, DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), x, - GENMASK(17, 6)); + DISPC_OVR_ATTRIBUTES_POSX_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), y, - GENMASK(30, 19)); + DISPC_OVR_ATTRIBUTES_POSY_MASK); } =20 static void dispc_j721e_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { u32 hw_id =3D dispc->feat->vid_info[hw_plane].hw_id; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - hw_id, GENMASK(4, 1)); + hw_id, DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), x, - GENMASK(13, 0)); + DISPC_OVR_ATTRIBUTES2_POSX_MASK); OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES2(layer), y, - GENMASK(29, 16)); + DISPC_OVR_ATTRIBUTES2_POSY_MASK); } =20 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane, u32 hw_videoport, u32 x, u32 y, u32 layer) { @@ -1536,11 +1538,11 @@ void dispc_ovr_enable_layer(struct dispc_device *di= spc, { if (dispc->feat->subrev =3D=3D DISPC_K2G) return; =20 OVR_REG_FLD_MOD(dispc, hw_videoport, DISPC_OVR_ATTRIBUTES(layer), - !!enable, GENMASK(0, 0)); + !!enable, DISPC_OVR_ATTRIBUTES_ENABLE_MASK); } =20 /* CSC */ enum csc_ctm { CSC_RR, CSC_RG, CSC_RB, @@ -1760,11 +1762,11 @@ static void dispc_vid_csc_setup(struct dispc_device= *dispc, u32 hw_plane, =20 static void dispc_vid_csc_enable(struct dispc_device *dispc, u32 hw_plane, bool enable) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, - GENMASK(9, 9)); + DISPC_VID_ATTRIBUTES_COLORCONVENABLE_MASK); } =20 /* SCALER */ =20 static u32 dispc_calc_fir_inc(u32 in, u32 out) @@ -2018,23 +2020,23 @@ static void dispc_vid_set_scaling(struct dispc_devi= ce *dispc, struct dispc_scaling_params *sp, u32 fourcc) { /* HORIZONTAL RESIZE ENABLE */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_x, - GENMASK(7, 7)); + DISPC_VID_ATTRIBUTES_HRESIZEENABLE_MASK); =20 /* VERTICAL RESIZE ENABLE */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->scale_y, - GENMASK(8, 8)); + DISPC_VID_ATTRIBUTES_VRESIZEENABLE_MASK); =20 /* Skip the rest if no scaling is used */ if (!sp->scale_x && !sp->scale_y) return; =20 /* VERTICAL 5-TAPS */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, sp->five_taps, - GENMASK(21, 21)); + DISPC_VID_ATTRIBUTES_VERTICALTAPS_MASK); =20 if (dispc_fourcc_is_yuv(fourcc)) { if (sp->scale_x) { dispc_vid_write(dispc, hw_plane, DISPC_VID_FIRH2, sp->fir_xinc_uv); @@ -2120,11 +2122,11 @@ static void dispc_plane_set_pixel_format(struct dis= pc_device *dispc, =20 for (i =3D 0; i < ARRAY_SIZE(dispc_color_formats); ++i) { if (dispc_color_formats[i].fourcc =3D=3D fourcc) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, dispc_color_formats[i].dss_code, - GENMASK(6, 1)); + DISPC_VID_ATTRIBUTES_FORMAT_MASK); return; } } =20 WARN_ON(1); @@ -2242,11 +2244,12 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_0, (u64)dma_addr >> 32); dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_1, dma_addr & 0xffffffff); dispc_vid_write(dispc, hw_plane, DISPC_VID_BA_EXT_1, (u64)dma_addr >> 32); =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PICTURE_SIZE, - (scale.in_w - 1) | ((scale.in_h - 1) << 16)); + FIELD_PREP(DISPC_VID_PICTURE_SIZE_MEMSIZEY_MASK, scale.in_h - 1) | + FIELD_PREP(DISPC_VID_PICTURE_SIZE_MEMSIZEX_MASK, scale.in_w - 1)); =20 /* For YUV422 format we use the macropixel size for pixel inc */ if (fourcc =3D=3D DRM_FORMAT_YUYV || fourcc =3D=3D DRM_FORMAT_UYVY) dispc_vid_write(dispc, hw_plane, DISPC_VID_PIXEL_INC, pixinc(scale.xinc, cpp * 2)); @@ -2279,12 +2282,14 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, cpp_uv)); } =20 if (!lite) { dispc_vid_write(dispc, hw_plane, DISPC_VID_SIZE, - (state->crtc_w - 1) | - ((state->crtc_h - 1) << 16)); + FIELD_PREP(DISPC_VID_SIZE_SIZEY_MASK, + state->crtc_h - 1) | + FIELD_PREP(DISPC_VID_SIZE_SIZEX_MASK, + state->crtc_w - 1)); =20 dispc_vid_set_scaling(dispc, hw_plane, &scale, fourcc); } =20 /* enable YUV->RGB color conversion */ @@ -2294,56 +2299,63 @@ void dispc_plane_setup(struct dispc_device *dispc, = u32 hw_plane, } else { dispc_vid_csc_enable(dispc, hw_plane, false); } =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_GLOBAL_ALPHA, - 0xFF & (state->alpha >> 8)); + FIELD_PREP(DISPC_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK, + state->alpha >> 8)); =20 if (state->pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - GENMASK(28, 28)); + DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK); else VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - GENMASK(28, 28)); + DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK); } =20 void dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool ena= ble) { VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, !!enable, - GENMASK(0, 0)); + DISPC_VID_ATTRIBUTES_ENABLE_MASK); } =20 static u32 dispc_vid_get_fifo_size(struct dispc_device *dispc, u32 hw_plan= e) { return VID_REG_GET(dispc, hw_plane, DISPC_VID_BUF_SIZE_STATUS, - GENMASK(15, 0)); + DISPC_VID_BUF_SIZE_STATUS_BUFSIZE_MASK); } =20 static void dispc_vid_set_mflag_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_MFLAG_THRESHOLD, - FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); + FIELD_PREP(DISPC_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK, high) | + FIELD_PREP(DISPC_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK, low)); } =20 static void dispc_vid_set_buf_threshold(struct dispc_device *dispc, u32 hw_plane, u32 low, u32 high) { dispc_vid_write(dispc, hw_plane, DISPC_VID_BUF_THRESHOLD, - FIELD_PREP(GENMASK(31, 16), high) | FIELD_PREP(GENMASK(15, 0), low)); + FIELD_PREP(DISPC_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK, + high) | + FIELD_PREP(DISPC_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK, + low)); } =20 static void dispc_k2g_plane_init(struct dispc_device *dispc) { unsigned int hw_plane; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2376,11 +2388,11 @@ static void dispc_k2g_plane_init(struct dispc_devic= e *dispc) * Prefetch up to fifo high-threshold value to minimize the * possibility of underflows. Note that this means the PRELOAD * register is ignored. */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 1, - GENMASK(19, 19)); + DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK); } } =20 static void dispc_k3_plane_init(struct dispc_device *dispc) { @@ -2388,17 +2400,19 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) u32 cba_lo_pri =3D 1; u32 cba_hi_pri =3D 0; =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, GENMASK(2, 0)); - REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, GENMASK(5, 3)); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_lo_pri, DSS_CBA_CFG_PRI_LO_MASK); + REG_FLD_MOD(dispc, DSS_CBA_CFG, cba_hi_pri, DSS_CBA_CFG_PRI_HI_MASK); =20 /* MFLAG_CTRL =3D ENABLED */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, GENMASK(1, 0)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 2, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK); /* MFLAG_START =3D MFLAGNORMALSTARTMODE */ - REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, GENMASK(6, 6)); + REG_FLD_MOD(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, 0, + DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK); =20 for (hw_plane =3D 0; hw_plane < dispc->feat->num_vids; hw_plane++) { u32 size =3D dispc_vid_get_fifo_size(dispc, hw_plane); u32 thr_low, thr_high; u32 mflag_low, mflag_high; @@ -2427,11 +2441,11 @@ static void dispc_k3_plane_init(struct dispc_device= *dispc) =20 dispc_vid_write(dispc, hw_plane, DISPC_VID_PRELOAD, preload); =20 /* Prefech up to PRELOAD value */ VID_REG_FLD_MOD(dispc, hw_plane, DISPC_VID_ATTRIBUTES, 0, - GENMASK(19, 19)); + DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK); } } =20 static void dispc_plane_init(struct dispc_device *dispc) { @@ -2457,23 +2471,24 @@ static void dispc_vp_init(struct dispc_device *disp= c) =20 dev_dbg(dispc->dev, "%s()\n", __func__); =20 /* Enable the gamma Shadow bit-field for all VPs*/ for (i =3D 0; i < dispc->feat->num_vps; i++) - VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, GENMASK(2, 2)); + VP_REG_FLD_MOD(dispc, i, DISPC_VP_CONFIG, 1, + DISPC_VP_CONFIG_GAMMAENABLE_MASK); } =20 static void dispc_initial_config(struct dispc_device *dispc) { dispc_plane_init(dispc); dispc_vp_init(dispc); =20 /* Note: Hardcoded DPI routing on J721E for now */ if (dispc->feat->subrev =3D=3D DISPC_J721E) { dispc_write(dispc, DISPC_CONNECTIONS, - FIELD_PREP(GENMASK(3, 0), 2) | /* VP1 to DPI0 */ - FIELD_PREP(GENMASK(7, 4), 8) /* VP3 to DPI1 */ + FIELD_PREP(DISPC_CONNECTIONS_DPI_0_CONN_MASK, 2) | /* VP1 to DPI0 = */ + FIELD_PREP(DISPC_CONNECTIONS_DPI_1_CONN_MASK, 8) /* VP3 to DPI1 */ ); } } =20 static void dispc_k2g_vp_write_gamma_table(struct dispc_device *dispc, @@ -2691,11 +2706,11 @@ static void dispc_k2g_vp_set_ctm(struct dispc_devic= e *dispc, u32 hw_videoport, dispc_k2g_vp_write_csc(dispc, hw_videoport, &cpr); cprenable =3D 1; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, cprenable, - GENMASK(15, 15)); + DISPC_VP_CONFIG_CPR_MASK); } =20 static s16 dispc_S31_32_to_s3_8(s64 coef) { u64 sign_bit =3D 1ULL << 63; @@ -2757,11 +2772,11 @@ static void dispc_k3_vp_set_ctm(struct dispc_device= *dispc, u32 hw_videoport, dispc_k3_vp_write_csc(dispc, hw_videoport, &csc); colorconvenable =3D 1; } =20 VP_REG_FLD_MOD(dispc, hw_videoport, DISPC_VP_CONFIG, colorconvenable, - GENMASK(24, 24)); + DISPC_VP_CONFIG_COLORCONVENABLE_MASK); } =20 static void dispc_vp_set_color_mgmt(struct dispc_device *dispc, u32 hw_videoport, const struct drm_crtc_state *state, @@ -2812,11 +2827,11 @@ int dispc_runtime_resume(struct dispc_device *dispc) { dev_dbg(dispc->dev, "resume\n"); =20 clk_prepare_enable(dispc->fclk); =20 - if (REG_GET(dispc, DSS_SYSSTATUS, GENMASK(0, 0)) =3D=3D 0) + if (REG_GET(dispc, DSS_SYSSTATUS, DSS_SYSSTATUS_DISPC_FUNC_RESETDONE) =3D= =3D 0) dev_warn(dispc->dev, "DSS FUNC RESET not done!\n"); =20 dev_dbg(dispc->dev, "OMAP DSS7 rev 0x%x\n", dispc_read(dispc, DSS_REVISION)); =20 @@ -2831,11 +2846,11 @@ int dispc_runtime_resume(struct dispc_device *dispc) REG_GET(dispc, DSS_SYSSTATUS, GENMASK(5, 5)), REG_GET(dispc, DSS_SYSSTATUS, GENMASK(6, 6)), REG_GET(dispc, DSS_SYSSTATUS, GENMASK(7, 7))); =20 dev_dbg(dispc->dev, "DISPC IDLE %d\n", - REG_GET(dispc, DSS_SYSSTATUS, GENMASK(9, 9))); + REG_GET(dispc, DSS_SYSSTATUS, DSS_SYSSTATUS_DISPC_IDLE_STATUS)); =20 dispc_initial_config(dispc); =20 dispc->is_enabled =3D true; =20 @@ -2909,11 +2924,11 @@ static void dispc_softreset_k2g(struct dispc_device= *dispc) dispc_read_and_clear_irqstatus(dispc); spin_unlock_irqrestore(&dispc->tidss->irq_lock, flags); =20 for (unsigned int vp_idx =3D 0; vp_idx < dispc->feat->num_vps; ++vp_idx) VP_REG_FLD_MOD(dispc, vp_idx, DISPC_VP_CONTROL, 0, - GENMASK(0, 0)); + DISPC_VP_CONTROL_ENABLE_MASK); } =20 static int dispc_softreset(struct dispc_device *dispc) { u32 val; @@ -2923,11 +2938,11 @@ static int dispc_softreset(struct dispc_device *dis= pc) dispc_softreset_k2g(dispc); return 0; } =20 /* Soft reset */ - REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, GENMASK(1, 1)); + REG_FLD_MOD(dispc, DSS_SYSCONFIG, 1, DSS_SYSCONFIG_SOFTRESET_MASK); /* Wait for reset to complete */ ret =3D readl_poll_timeout(dispc->base_common + DSS_SYSSTATUS, val, val & 1, 100, 5000); if (ret) { dev_err(dispc->dev, "failed to reset dispc\n"); diff --git a/drivers/gpu/drm/tidss/tidss_dispc_regs.h b/drivers/gpu/drm/tid= ss/tidss_dispc_regs.h index 50a3f28250efe61f1d98a456bf8907000109411c..382027dddce894b3b7d11172e23= bf11883e25958 100644 --- a/drivers/gpu/drm/tidss/tidss_dispc_regs.h +++ b/drivers/gpu/drm/tidss/tidss_dispc_regs.h @@ -54,11 +54,16 @@ enum dispc_common_regs { =20 #define REG(r) (dispc_common_regmap[r ## _OFF]) =20 #define DSS_REVISION REG(DSS_REVISION) #define DSS_SYSCONFIG REG(DSS_SYSCONFIG) +#define DSS_SYSCONFIG_SOFTRESET_MASK GENMASK(1, 1) + #define DSS_SYSSTATUS REG(DSS_SYSSTATUS) +#define DSS_SYSSTATUS_DISPC_IDLE_STATUS GENMASK(9, 9) +#define DSS_SYSSTATUS_DISPC_FUNC_RESETDONE GENMASK(0, 0) + #define DISPC_IRQ_EOI REG(DISPC_IRQ_EOI) #define DISPC_IRQSTATUS_RAW REG(DISPC_IRQSTATUS_RAW) #define DISPC_IRQSTATUS REG(DISPC_IRQSTATUS) #define DISPC_IRQENABLE_SET REG(DISPC_IRQENABLE_SET) #define DISPC_IRQENABLE_CLR REG(DISPC_IRQENABLE_CLR) @@ -68,13 +73,19 @@ enum dispc_common_regs { #define DISPC_VP_IRQSTATUS(n) (REG(DISPC_VP_IRQSTATUS) + (n) * 4) #define WB_IRQENABLE REG(WB_IRQENABLE) #define WB_IRQSTATUS REG(WB_IRQSTATUS) =20 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE REG(DISPC_GLOBAL_MFLAG_ATTRIBUTE) +#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_START_MASK GENMASK(6, 6) +#define DISPC_GLOBAL_MFLAG_ATTRIBUTE_MFLAG_CTRL_MASK GENMASK(1, 0) + #define DISPC_GLOBAL_OUTPUT_ENABLE REG(DISPC_GLOBAL_OUTPUT_ENABLE) #define DISPC_GLOBAL_BUFFER REG(DISPC_GLOBAL_BUFFER) #define DSS_CBA_CFG REG(DSS_CBA_CFG) +#define DSS_CBA_CFG_PRI_HI_MASK GENMASK(5, 3) +#define DSS_CBA_CFG_PRI_LO_MASK GENMASK(2, 0) + #define DISPC_DBG_CONTROL REG(DISPC_DBG_CONTROL) #define DISPC_DBG_STATUS REG(DISPC_DBG_STATUS) #define DISPC_CLKGATING_DISABLE REG(DISPC_CLKGATING_DISABLE) #define DISPC_SECURE_DISABLE REG(DISPC_SECURE_DISABLE) =20 @@ -86,10 +97,13 @@ enum dispc_common_regs { #define FBDC_REVISION_6 REG(FBDC_REVISION_6) #define FBDC_COMMON_CONTROL REG(FBDC_COMMON_CONTROL) #define FBDC_CONSTANT_COLOR_0 REG(FBDC_CONSTANT_COLOR_0) #define FBDC_CONSTANT_COLOR_1 REG(FBDC_CONSTANT_COLOR_1) #define DISPC_CONNECTIONS REG(DISPC_CONNECTIONS) +#define DISPC_CONNECTIONS_DPI_1_CONN_MASK GENMASK(7, 4) +#define DISPC_CONNECTIONS_DPI_0_CONN_MASK GENMASK(3, 0) + #define DISPC_MSS_VP1 REG(DISPC_MSS_VP1) #define DISPC_MSS_VP3 REG(DISPC_MSS_VP3) =20 /* VID */ =20 @@ -100,17 +114,31 @@ enum dispc_common_regs { #define DISPC_VID_ACCUV_0 0x10 #define DISPC_VID_ACCUV_1 0x14 #define DISPC_VID_ACCUV2_0 0x18 #define DISPC_VID_ACCUV2_1 0x1c #define DISPC_VID_ATTRIBUTES 0x20 +#define DISPC_VID_ATTRIBUTES_PREMULTIPLYALPHA_MASK GENMASK(28, 28) +#define DISPC_VID_ATTRIBUTES_VERTICALTAPS_MASK GENMASK(21, 21) +#define DISPC_VID_ATTRIBUTES_BUFPRELOAD_MASK GENMASK(19, 19) +#define DISPC_VID_ATTRIBUTES_COLORCONVENABLE_MASK GENMASK(9, 9) +#define DISPC_VID_ATTRIBUTES_VRESIZEENABLE_MASK GENMASK(8, 8) +#define DISPC_VID_ATTRIBUTES_HRESIZEENABLE_MASK GENMASK(7, 7) +#define DISPC_VID_ATTRIBUTES_FORMAT_MASK GENMASK(6, 1) +#define DISPC_VID_ATTRIBUTES_ENABLE_MASK GENMASK(0, 0) + #define DISPC_VID_ATTRIBUTES2 0x24 #define DISPC_VID_BA_0 0x28 #define DISPC_VID_BA_1 0x2c #define DISPC_VID_BA_UV_0 0x30 #define DISPC_VID_BA_UV_1 0x34 #define DISPC_VID_BUF_SIZE_STATUS 0x38 +#define DISPC_VID_BUF_SIZE_STATUS_BUFSIZE_MASK GENMASK(15, 0) + #define DISPC_VID_BUF_THRESHOLD 0x3c +#define DISPC_VID_BUF_THRESHOLD_BUFHIGHTHRESHOLD_MASK GENMASK(31, 16) +#define DISPC_VID_BUF_THRESHOLD_BUFLOWTHRESHOLD_MASK GENMASK(15, 0) + #define DISPC_VID_CSC_COEF(n) (0x40 + (n) * 4) =20 #define DISPC_VID_FIRH 0x5c #define DISPC_VID_FIRH2 0x60 #define DISPC_VID_FIRV 0x64 @@ -135,19 +163,30 @@ enum dispc_common_regs { #define DISPC_VID_FIR_COEF_V12(phase) (0x17c + (phase) * 4) #define DISPC_VID_FIR_COEFS_V12_C 0x1bc #define DISPC_VID_FIR_COEF_V12_C(phase) (0x1bc + (phase) * 4) =20 #define DISPC_VID_GLOBAL_ALPHA 0x1fc +#define DISPC_VID_GLOBAL_ALPHA_GLOBALALPHA_MASK GENMASK(7, 0) + #define DISPC_VID_K2G_IRQENABLE 0x200 /* K2G */ #define DISPC_VID_K2G_IRQSTATUS 0x204 /* K2G */ #define DISPC_VID_MFLAG_THRESHOLD 0x208 +#define DISPC_VID_MFLAG_THRESHOLD_HT_MFLAG_MASK GENMASK(31, 16) +#define DISPC_VID_MFLAG_THRESHOLD_LT_MFLAG_MASK GENMASK(15, 0) + #define DISPC_VID_PICTURE_SIZE 0x20c +#define DISPC_VID_PICTURE_SIZE_MEMSIZEY_MASK GENMASK(27, 16) +#define DISPC_VID_PICTURE_SIZE_MEMSIZEX_MASK GENMASK(11, 0) + #define DISPC_VID_PIXEL_INC 0x210 #define DISPC_VID_K2G_POSITION 0x214 /* K2G */ #define DISPC_VID_PRELOAD 0x218 #define DISPC_VID_ROW_INC 0x21c #define DISPC_VID_SIZE 0x220 +#define DISPC_VID_SIZE_SIZEY_MASK GENMASK(27, 16) +#define DISPC_VID_SIZE_SIZEX_MASK GENMASK(11, 0) + #define DISPC_VID_BA_EXT_0 0x22c #define DISPC_VID_BA_EXT_1 0x230 #define DISPC_VID_BA_UV_EXT_0 0x234 #define DISPC_VID_BA_UV_EXT_1 0x238 #define DISPC_VID_CSC_COEF7 0x23c @@ -171,15 +210,31 @@ enum dispc_common_regs { #define DISPC_OVR_TRANS_COLOR_MAX 0x10 #define DISPC_OVR_TRANS_COLOR_MAX2 0x14 #define DISPC_OVR_TRANS_COLOR_MIN 0x18 #define DISPC_OVR_TRANS_COLOR_MIN2 0x1c #define DISPC_OVR_ATTRIBUTES(n) (0x20 + (n) * 4) +#define DISPC_OVR_ATTRIBUTES_POSY_MASK GENMASK(30, 19) +#define DISPC_OVR_ATTRIBUTES_POSX_MASK GENMASK(17, 6) +#define DISPC_OVR_ATTRIBUTES_CHANNELIN_MASK GENMASK(4, 1) +#define DISPC_OVR_ATTRIBUTES_ENABLE_MASK GENMASK(0, 0) + #define DISPC_OVR_ATTRIBUTES2(n) (0x34 + (n) * 4) /* J721E */ +#define DISPC_OVR_ATTRIBUTES2_POSY_MASK GENMASK(29, 16) +#define DISPC_OVR_ATTRIBUTES2_POSX_MASK GENMASK(13, 0) + /* VP */ =20 #define DISPC_VP_CONFIG 0x0 +#define DISPC_VP_CONFIG_COLORCONVENABLE_MASK GENMASK(24, 24) +#define DISPC_VP_CONFIG_CPR_MASK GENMASK(15, 15) +#define DISPC_VP_CONFIG_GAMMAENABLE_MASK GENMASK(2, 2) + #define DISPC_VP_CONTROL 0x4 +#define DISPC_VP_CONTROL_DATALINES_MASK GENMASK(10, 8) +#define DISPC_VP_CONTROL_GOBIT_MASK GENMASK(5, 5) +#define DISPC_VP_CONTROL_ENABLE_MASK GENMASK(0, 0) + #define DISPC_VP_CSC_COEF0 0x8 #define DISPC_VP_CSC_COEF1 0xc #define DISPC_VP_CSC_COEF2 0x10 #define DISPC_VP_DATA_CYCLE_0 0x14 #define DISPC_VP_DATA_CYCLE_1 0x18 @@ -187,13 +242,32 @@ enum dispc_common_regs { #define DISPC_VP_K2G_IRQENABLE 0x3c /* K2G */ #define DISPC_VP_K2G_IRQSTATUS 0x40 /* K2G */ #define DISPC_VP_DATA_CYCLE_2 0x1c #define DISPC_VP_LINE_NUMBER 0x44 #define DISPC_VP_POL_FREQ 0x4c +#define DISPC_VP_POL_FREQ_ALIGN_MASK GENMASK(18, 18) +#define DISPC_VP_POL_FREQ_ONOFF_MASK GENMASK(17, 17) +#define DISPC_VP_POL_FREQ_RF_MASK GENMASK(16, 16) +#define DISPC_VP_POL_FREQ_IEO_MASK GENMASK(15, 15) +#define DISPC_VP_POL_FREQ_IPC_MASK GENMASK(14, 14) +#define DISPC_VP_POL_FREQ_IHS_MASK GENMASK(13, 13) +#define DISPC_VP_POL_FREQ_IVS_MASK GENMASK(12, 12) + #define DISPC_VP_SIZE_SCREEN 0x50 +#define DISPC_VP_SIZE_SCREEN_HDISPLAY_MASK GENMASK(11, 0) +#define DISPC_VP_SIZE_SCREEN_VDISPLAY_MASK GENMASK(27, 16) + #define DISPC_VP_TIMING_H 0x54 +#define DISPC_VP_TIMING_H_SYNC_PULSE_MASK GENMASK(7, 0) +#define DISPC_VP_TIMING_H_FRONT_PORCH_MASK GENMASK(19, 8) +#define DISPC_VP_TIMING_H_BACK_PORCH_MASK GENMASK(31, 20) + #define DISPC_VP_TIMING_V 0x58 +#define DISPC_VP_TIMING_V_SYNC_PULSE_MASK GENMASK(7, 0) +#define DISPC_VP_TIMING_V_FRONT_PORCH_MASK GENMASK(19, 8) +#define DISPC_VP_TIMING_V_BACK_PORCH_MASK GENMASK(31, 20) + #define DISPC_VP_CSC_COEF3 0x5c #define DISPC_VP_CSC_COEF4 0x60 #define DISPC_VP_CSC_COEF5 0x64 #define DISPC_VP_CSC_COEF6 0x68 #define DISPC_VP_CSC_COEF7 0x6c @@ -218,10 +292,12 @@ enum dispc_common_regs { #define DISPC_VP_SAFETY_SIZE_2 0xf8 #define DISPC_VP_SAFETY_SIZE_3 0xfc #define DISPC_VP_SAFETY_LFSR_SEED 0x110 #define DISPC_VP_GAMMA_TABLE 0x120 #define DISPC_VP_DSS_OLDI_CFG 0x160 +#define DISPC_VP_DSS_OLDI_CFG_MAP_MASK GENMASK(3, 1) + #define DISPC_VP_DSS_OLDI_STATUS 0x164 #define DISPC_VP_DSS_OLDI_LB 0x168 #define DISPC_VP_DSS_MERGE_SPLIT 0x16c /* J721E */ #define DISPC_VP_DSS_DMA_THREADSIZE 0x170 /* J721E */ #define DISPC_VP_DSS_DMA_THREADSIZE_STATUS 0x174 /* J721E */ --=20 2.50.1