From nobody Sat Oct 4 03:17:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5C09626E6E2; Wed, 20 Aug 2025 14:15:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699322; cv=none; b=Z8joIzdCo7WsJPgZmJmyodsWNM9kcjVK3jCmP1anwOge2O9gHY90dMnxpeOF/K2LvDnaERRtKqS657s81S5up3RFhT73I1Uatr8qK+V5GrEHbaohWjUw9T80JzlygQvtc62mUtTmJxqZWJ0RKY6gYZOqSy2ziq8HwyQFibXnVR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699322; c=relaxed/simple; bh=OQQckPddTneOzG/6ku3q22aHRtDHjLTy5HAplDzg1tg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IXCxe9taBSnqsqA0oeOqkJMeSdJXLRIgx0ovzDs01nPhRL5mhy8Dab2qWGiBrmQ88zd7IH3gHVwH52GZyAxc6OOrPt0HFwvqGU3L8VLeCzX4RyzJz5xAssBN/AVWO+y+WvsqggfZ1k4JM3me7gvDSiieFLpZmNjweb9smh4zPm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GNWEv3kR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GNWEv3kR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 919EAC116B1; Wed, 20 Aug 2025 14:15:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755699321; bh=OQQckPddTneOzG/6ku3q22aHRtDHjLTy5HAplDzg1tg=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=GNWEv3kRuhJHrg6O8tl9v9XZLUFLD5DX16vsK30S6lje+sJFYSmjGbB5HpZj/VPgh TDjZKX/ifXH7uGh2e+lt7646z7sUlNbnz6+lOCG8Mz8jXy7MI8j1YuGTTbZ6xvJH57 jipPJ0uow4hRXRF1c9KdTNVp7S/7eHElmjC41cq9gGl5NWpuyuvWT/+siB4JT/9bLe /aNUEQKLFu8uTm2VkYmAVmqpyepUEFvJtP7oB+4uX3e0gzpo1f3/X+2vkk3/0bUNcC ONwDv7rhR+cpmmZAq0WBuge5vLArgQg88mDxDZj2kF5TweQ54w0nK3wrsLdzD07/Gh iecJL+cNHgT6g== From: Mark Brown Date: Wed, 20 Aug 2025 15:14:41 +0100 Subject: [PATCH v15 1/6] arm64/gcs: Ensure FGTs for EL1 GCS instructions are disabled Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-arm64-gcs-v15-1-5e334da18b84@kernel.org> References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> In-Reply-To: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-cff91 X-Developer-Signature: v=1; a=openpgp-sha256; l=828; i=broonie@kernel.org; h=from:subject:message-id; bh=OQQckPddTneOzG/6ku3q22aHRtDHjLTy5HAplDzg1tg=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBopdhuIy7mFDmV+0H0uG28RgkPLA3n2FYlocioI EkRcIIBg3qJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaKXYbgAKCRAk1otyXVSH 0EAMB/9fwOu0l6w/AEd6V5PAmGwzmw1euLwLI/cTXKU6biaBsNLRTXJ/0qSF5OuHWpuYaFtAvb7 5JVxDwGYoBJUtTP4kv7zLeHbkkP1xc3a3HFYU7tMh7YhvCyxsIIFFGT1wIHS2NW00PUT91fY+hy OZnNkn2ndCuLB0FXpxCyUhYzLPtOnPai3lWS6jy4CY2PAjpILWDLWIYP9C65647CGACa9rgKi3+ vE5zmbmP0py0s0vB+n7RJZOPZvS/FoTmL8bZTf0fGuUap+2ssl3Lt8NCHDc3u8Kc+AUZ5qaOdHt XS1223r7Fnm1G2lVW4qLxjwGKhlABshmaJQ1tpwiRIKjHWoT X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB The initial EL2 setup for GCS did not include disabling of EL1 usage of GCS instructions, also disable these traps. This is the first disabling of instruction traps, use x2 to store the value to be written. Signed-off-by: Mark Brown --- arch/arm64/include/asm/el2_setup.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index 46033027510c..0ac14ea4dbc8 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -355,6 +355,10 @@ =20 .Lskip_gce_fgt_\@: =20 + orr x2, x2, #HFGITR_EL2_nGCSEPP_MASK + orr x2, x2, #HFGITR_EL2_nGCSSTR_EL1_MASK + orr x2, x2, #HFGITR_EL2_nGCSPUSHM_EL1_MASK + .Lset_fgt_\@: msr_s SYS_HFGRTR_EL2, x0 msr_s SYS_HFGWTR_EL2, x0 --=20 2.39.5 From nobody Sat Oct 4 03:17:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 40AFF1DDC07; Wed, 20 Aug 2025 14:15:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699327; cv=none; b=YfX/jTDzrkLs0GLFunapnLAixhjePflaHYUx7IJZwJvEzJ9gwXVrJj9PsGgZYz3XiVFIZwqBy/bsh4LqlUKZ/37kAmEyZ0KUbgu2MfqnMzE/Y3j5+p7OSvuNTWTvop3jdhZASnioyxU4EuvUMePg4Sbmb1YZpI441InQXdakSW0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699327; c=relaxed/simple; bh=B4WhVhWlQUV3RpMfPy1jJwJQZNUp60IegucsTo4ATog=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Zx1QJCyvj9xx8D6Wat2S5MHaoy0RKoMpo3RmQJacLKdhXLsm3FpaMtcAgAbSkcTvPMoiLOZIB3RzBJMSs32HEuEHt1EH5vnzdIVk2+f52T3i7NL0g5YpYwOhJYkWnTm5Ir41QVA8Zl92sa96PED+1TL00PnCXTQjAHm3qTYDlqU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=nUDpos7x; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="nUDpos7x" Received: by smtp.kernel.org (Postfix) with ESMTPSA id B65ADC4CEEB; Wed, 20 Aug 2025 14:15:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755699326; bh=B4WhVhWlQUV3RpMfPy1jJwJQZNUp60IegucsTo4ATog=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=nUDpos7xrXgjtqzp3CDyvOXF6pQiYoh/KaWKpyPkwFCY9YliG0GAg5Nguy6yhRgg6 5JkLElC6leZZgB8o5qUwa5VrkvwHVf7v6yibqOPJj5EYMBqiTM7JvOjmENzHBZszdr BaVfXQK4xmxcuWsShzyl2QRjGEmltkd4Ie/Dj4vU0gE+1rI9MXAfprRdZs15vRsJFQ DWWclEGnpJ1TVS4aLKpP3WRmfJygHitmpnLjStcug8ZOIlci3gBpgugOVXbfbI+OPH kIaZFdbk9/jNliUbCznYU/dcVxNg+L4awte9Hd48JA/eBeoxCWZJJV+FK0ZOJOjB9O F97ii1moXTTtw== From: Mark Brown Date: Wed, 20 Aug 2025 15:14:42 +0100 Subject: [PATCH v15 2/6] KVM: arm64: Manage GCS access and registers for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-arm64-gcs-v15-2-5e334da18b84@kernel.org> References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> In-Reply-To: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-cff91 X-Developer-Signature: v=1; a=openpgp-sha256; l=11187; i=broonie@kernel.org; h=from:subject:message-id; bh=B4WhVhWlQUV3RpMfPy1jJwJQZNUp60IegucsTo4ATog=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBopdhviGgNplkjClTHjWrZtr1pJS4vcCbdGO3Zz CtQQ6PD83KJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaKXYbwAKCRAk1otyXVSH 0KTuB/0ax7Wx15WnfHmcHCsYRmxPIS95dIb20hblOakOgbr9FGsksE8YJG5pdqm2uAH5526sgse sa6tO9TkQywXAom79DNd4K3uy6QeRaiJj2YPLAh2Ohi8gWLh8udHB55Wc8xoOAkowHObyHW0hJK ZcWJZrre0ZtupoLLUGH/yzGuqn1Xd18CH4FEo9XWXw5ftWKSjQANpUjpozxWyT8sm3fF9H51j+G C5+URaUA9iAfMDvWGV2/tlK60Q1F4iLWKFIMpz/3a+6oFqsuDA5ZdSBssfnhmjq1aCv+Mc2VPPD fFcHGQjiew+vCrJbWjb07oI8/84B9MDA5BVpWxX1InLaDUAX X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS introduces a number of system registers for EL1 and EL0, on systems with GCS we need to context switch them and expose them to VMMs to allow guests to use GCS. In order to allow guests to use GCS we also need to configure HCRX_EL2.GCSEn, if this is not set GCS instructions will be noops and CHKFEAT will report GCS as disabled. Also enable fine grained traps for access to the GCS registers by guests which do not have the feature enabled. In order to allow userspace to control availability of the feature to guests we enable writability for only ID_AA64PFR1_EL1.GCS, this is a deliberately conservative choice to avoid errors due to oversights. Further fields should be made writable in future. Signed-off-by: Mark Brown --- arch/arm64/include/asm/kvm_emulate.h | 3 +++ arch/arm64/include/asm/kvm_host.h | 14 ++++++++++++++ arch/arm64/include/asm/vncr_mapping.h | 2 ++ arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h | 31 ++++++++++++++++++++++++++= ++++ arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 10 ++++++++++ arch/arm64/kvm/sys_regs.c | 31 ++++++++++++++++++++++++++= +++- 6 files changed, 90 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/kvm_emulate.h b/arch/arm64/include/asm/= kvm_emulate.h index fa8a08a1ccd5..9ab1e7616854 100644 --- a/arch/arm64/include/asm/kvm_emulate.h +++ b/arch/arm64/include/asm/kvm_emulate.h @@ -672,6 +672,9 @@ static inline void vcpu_set_hcrx(struct kvm_vcpu *vcpu) =20 if (kvm_has_sctlr2(kvm)) vcpu->arch.hcrx_el2 |=3D HCRX_EL2_SCTLR2En; + + if (kvm_has_gcs(kvm)) + vcpu->arch.hcrx_el2 |=3D HCRX_EL2_GCSEn; } } #endif /* __ARM64_KVM_EMULATE_H__ */ diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm= _host.h index 2f2394cce24e..22a3fa9d97aa 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -480,6 +480,10 @@ enum vcpu_sysreg { =20 POR_EL0, /* Permission Overlay Register 0 (EL0) */ =20 + /* Guarded Control Stack registers */ + GCSCRE0_EL1, /* Guarded Control Stack Control (EL0) */ + GCSPR_EL0, /* Guarded Control Stack Pointer (EL0) */ + /* FP/SIMD/SVE */ SVCR, FPMR, @@ -502,6 +506,8 @@ enum vcpu_sysreg { PIRE0_EL2, /* Permission Indirection Register 0 (EL2) */ PIR_EL2, /* Permission Indirection Register 1 (EL2) */ POR_EL2, /* Permission Overlay Register 2 (EL2) */ + GCSCR_EL2, /* Guarded Control Stack Control Register (EL2) */ + GCSPR_EL2, /* Guarded Control Stack Pointer Register (EL2) */ SPSR_EL2, /* EL2 saved program status register */ ELR_EL2, /* EL2 exception link register */ AFSR0_EL2, /* Auxiliary Fault Status Register 0 (EL2) */ @@ -571,6 +577,10 @@ enum vcpu_sysreg { VNCR(VDISR_EL2), VNCR(VSESR_EL2), =20 + /* Guarded Control Stack registers */ + VNCR(GCSPR_EL1), /* Guarded Control Stack Pointer (EL1) */ + VNCR(GCSCR_EL1), /* Guarded Control Stack Control (EL1) */ + VNCR(HFGRTR_EL2), VNCR(HFGWTR_EL2), VNCR(HFGITR_EL2), @@ -1697,6 +1707,10 @@ void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64= val); #define kvm_has_sctlr2(k) \ (kvm_has_feat((k), ID_AA64MMFR3_EL1, SCTLRX, IMP)) =20 +#define kvm_has_gcs(k) \ + (system_supports_gcs() && \ + kvm_has_feat((k), ID_AA64PFR1_EL1, GCS, IMP)) + static inline bool kvm_arch_has_irq_bypass(void) { return true; diff --git a/arch/arm64/include/asm/vncr_mapping.h b/arch/arm64/include/asm= /vncr_mapping.h index f6ec500ad3fa..e9fac6218d44 100644 --- a/arch/arm64/include/asm/vncr_mapping.h +++ b/arch/arm64/include/asm/vncr_mapping.h @@ -95,6 +95,8 @@ #define VNCR_PMSIRR_EL1 0x840 #define VNCR_PMSLATFR_EL1 0x848 #define VNCR_TRFCR_EL1 0x880 +#define VNCR_GCSPR_EL1 0x8C0 +#define VNCR_GCSCR_EL1 0x8D0 #define VNCR_MPAM1_EL1 0x900 #define VNCR_MPAMHCR_EL2 0x930 #define VNCR_MPAMVPMV_EL2 0x938 diff --git a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h b/arch/arm64/kvm/hy= p/include/hyp/sysreg-sr.h index a17cbe7582de..053d7b3c5104 100644 --- a/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h +++ b/arch/arm64/kvm/hyp/include/hyp/sysreg-sr.h @@ -17,6 +17,7 @@ #include =20 static inline bool ctxt_has_s1poe(struct kvm_cpu_context *ctxt); +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt); =20 static inline struct kvm_vcpu *ctxt_to_vcpu(struct kvm_cpu_context *ctxt) { @@ -67,6 +68,11 @@ static inline void __sysreg_save_user_state(struct kvm_c= pu_context *ctxt) { ctxt_sys_reg(ctxt, TPIDR_EL0) =3D read_sysreg(tpidr_el0); ctxt_sys_reg(ctxt, TPIDRRO_EL0) =3D read_sysreg(tpidrro_el0); + + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL0) =3D read_sysreg_s(SYS_GCSPR_EL0); + ctxt_sys_reg(ctxt, GCSCRE0_EL1) =3D read_sysreg_s(SYS_GCSCRE0_EL1); + } } =20 static inline bool ctxt_has_mte(struct kvm_cpu_context *ctxt) @@ -131,6 +137,17 @@ static inline bool ctxt_has_sctlr2(struct kvm_cpu_cont= ext *ctxt) return kvm_has_sctlr2(kern_hyp_va(vcpu->kvm)); } =20 +static inline bool ctxt_has_gcs(struct kvm_cpu_context *ctxt) +{ + struct kvm_vcpu *vcpu; + + if (!cpus_have_final_cap(ARM64_HAS_GCS)) + return false; + + vcpu =3D ctxt_to_vcpu(ctxt); + return kvm_has_feat(kern_hyp_va(vcpu->kvm), ID_AA64PFR1_EL1, GCS, IMP); +} + static inline void __sysreg_save_el1_state(struct kvm_cpu_context *ctxt) { ctxt_sys_reg(ctxt, SCTLR_EL1) =3D read_sysreg_el1(SYS_SCTLR); @@ -144,6 +161,10 @@ static inline void __sysreg_save_el1_state(struct kvm_= cpu_context *ctxt) if (ctxt_has_s1pie(ctxt)) { ctxt_sys_reg(ctxt, PIR_EL1) =3D read_sysreg_el1(SYS_PIR); ctxt_sys_reg(ctxt, PIRE0_EL1) =3D read_sysreg_el1(SYS_PIRE0); + if (ctxt_has_gcs(ctxt)) { + ctxt_sys_reg(ctxt, GCSPR_EL1) =3D read_sysreg_el1(SYS_GCSPR); + ctxt_sys_reg(ctxt, GCSCR_EL1) =3D read_sysreg_el1(SYS_GCSCR); + } } =20 if (ctxt_has_s1poe(ctxt)) @@ -206,6 +227,11 @@ static inline void __sysreg_restore_user_state(struct = kvm_cpu_context *ctxt) { write_sysreg(ctxt_sys_reg(ctxt, TPIDR_EL0), tpidr_el0); write_sysreg(ctxt_sys_reg(ctxt, TPIDRRO_EL0), tpidrro_el0); + if (ctxt_has_gcs(ctxt)) { + write_sysreg_s(ctxt_sys_reg(ctxt, GCSPR_EL0), SYS_GCSPR_EL0); + write_sysreg_s(ctxt_sys_reg(ctxt, GCSCRE0_EL1), + SYS_GCSCRE0_EL1); + } } =20 static inline void __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt, @@ -239,6 +265,11 @@ static inline void __sysreg_restore_el1_state(struct k= vm_cpu_context *ctxt, if (ctxt_has_s1pie(ctxt)) { write_sysreg_el1(ctxt_sys_reg(ctxt, PIR_EL1), SYS_PIR); write_sysreg_el1(ctxt_sys_reg(ctxt, PIRE0_EL1), SYS_PIRE0); + + if (ctxt_has_gcs(ctxt)) { + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSPR_EL1), SYS_GCSPR); + write_sysreg_el1(ctxt_sys_reg(ctxt, GCSCR_EL1), SYS_GCSCR); + } } =20 if (ctxt_has_s1poe(ctxt)) diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sy= sreg-sr.c index f28c6cf4fe1b..e63b473d66d1 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -61,6 +61,11 @@ static void __sysreg_save_vel2_state(struct kvm_vcpu *vc= pu) =20 if (ctxt_has_s1poe(&vcpu->arch.ctxt)) __vcpu_assign_sys_reg(vcpu, POR_EL2, read_sysreg_el1(SYS_POR)); + + if (ctxt_has_gcs(&vcpu->arch.ctxt)) { + __vcpu_assign_sys_reg(vcpu, GCSCR_EL2, read_sysreg_el1(SYS_GCSCR)); + __vcpu_assign_sys_reg(vcpu, GCSPR_EL2, read_sysreg_el1(SYS_GCSPR)); + } } =20 /* @@ -133,6 +138,11 @@ static void __sysreg_restore_vel2_state(struct kvm_vcp= u *vcpu) =20 if (ctxt_has_s1poe(&vcpu->arch.ctxt)) write_sysreg_el1(__vcpu_sys_reg(vcpu, POR_EL2), SYS_POR); + + if (ctxt_has_gcs(&vcpu->arch.ctxt)) { + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSCR_EL2), SYS_GCSCR); + write_sysreg_el1(__vcpu_sys_reg(vcpu, GCSPR_EL2), SYS_GCSPR); + } } =20 write_sysreg_el1(__vcpu_sys_reg(vcpu, ESR_EL2), SYS_ESR); diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 82ffb3b3b3cf..592cb5d6497a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -138,6 +138,8 @@ static bool get_el2_to_el1_mapping(unsigned int reg, MAPPED_EL2_SYSREG(PIR_EL2, PIR_EL1, NULL ); MAPPED_EL2_SYSREG(PIRE0_EL2, PIRE0_EL1, NULL ); MAPPED_EL2_SYSREG(POR_EL2, POR_EL1, NULL ); + MAPPED_EL2_SYSREG(GCSCR_EL2, GCSCR_EL1, NULL ); + MAPPED_EL2_SYSREG(GCSPR_EL2, GCSPR_EL1, NULL ); MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL ); MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL ); MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL ); @@ -2654,6 +2656,21 @@ static unsigned int s1pie_el2_visibility(const struc= t kvm_vcpu *vcpu, return __el2_visibility(vcpu, rd, s1pie_visibility); } =20 +static unsigned int gcs_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *r) +{ + if (kvm_has_gcs(vcpu->kvm)) + return 0; + + return REG_HIDDEN; +} + +static unsigned int gcs_el2_visibility(const struct kvm_vcpu *vcpu, + const struct sys_reg_desc *rd) +{ + return __el2_visibility(vcpu, rd, gcs_visibility); +} + static bool access_mdcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -2936,7 +2953,6 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { ~(ID_AA64PFR1_EL1_PFAR | ID_AA64PFR1_EL1_MTEX | ID_AA64PFR1_EL1_THE | - ID_AA64PFR1_EL1_GCS | ID_AA64PFR1_EL1_MTE_frac | ID_AA64PFR1_EL1_NMI | ID_AA64PFR1_EL1_RNDR_trap | @@ -3048,6 +3064,13 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { PTRAUTH_KEY(APDB), PTRAUTH_KEY(APGA), =20 + { SYS_DESC(SYS_GCSCR_EL1), NULL, reset_val, GCSCR_EL1, 0, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_GCSPR_EL1), NULL, reset_unknown, GCSPR_EL1, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_GCSCRE0_EL1), NULL, reset_val, GCSCRE0_EL1, 0, + .visibility =3D gcs_visibility }, + { SYS_DESC(SYS_SPSR_EL1), access_spsr}, { SYS_DESC(SYS_ELR_EL1), access_elr}, =20 @@ -3162,6 +3185,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { CTR_EL0_DminLine_MASK | CTR_EL0_L1Ip_MASK | CTR_EL0_IminLine_MASK), + { SYS_DESC(SYS_GCSPR_EL0), NULL, reset_unknown, GCSPR_EL0, + .visibility =3D gcs_visibility }, { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility =3D s= me_visibility }, { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility =3D f= p8_visibility }, =20 @@ -3401,6 +3426,10 @@ static const struct sys_reg_desc sys_reg_descs[] =3D= { EL2_REG_FILTERED(VNCR_EL2, bad_vncr_trap, reset_val, 0, vncr_el2_visibility), =20 + EL2_REG_FILTERED(GCSCR_EL2, access_rw, reset_val, 0, + gcs_el2_visibility), + EL2_REG_FILTERED(GCSPR_EL2, access_rw, reset_val, 0, + gcs_el2_visibility), { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 }, EL2_REG_VNCR_FILT(HDFGRTR2_EL2, fgt2_visibility), EL2_REG_VNCR_FILT(HDFGWTR2_EL2, fgt2_visibility), --=20 2.39.5 From nobody Sat Oct 4 03:17:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5548B2DEA9E; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-arm64-gcs-v15-3-5e334da18b84@kernel.org> References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> In-Reply-To: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-cff91 X-Developer-Signature: v=1; a=openpgp-sha256; l=1263; i=broonie@kernel.org; h=from:subject:message-id; bh=/H6Cuxewkf3ZOoM+h+m1Hnboxh9fXQ17PaC0xmbP9d8=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBopdhw9a8PwftR7e7KTrbNQNhA2EWwxbNtGK3+O uDaajVqAxqJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaKXYcAAKCRAk1otyXVSH 0JS+B/wNzWs53o4ozEZ+UVZObC3L+hU7WGSpojmSDhHzVYkpqAFOywHJUwUe+8/kJmKC2Ct/VzX ZIxMGWpO7E5OHGJDMbT3yRXqGkMs0kHvt3kkoXjn6Y6dddqtFqWYXaqwkY2ZOLxbSGPJRDn3eb3 kvQdUSWxwaRwrTeuLEGsGm2pLoaTRVVCJaUTAWwV5DpUPjuwuIYuM9nBPWZHzB5sWuKU02iw0jE gqhqavT9QJPnLdf9K3EMhPfixEkK+XraEgf9MtzpLcGJfzTmL+CjakifA4gK3Nsvmf84TGNFDCE eGwHOfQggzSd0F6ijq6Edd84QEfFJtMQICcL60sMNnDY78SE X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS can generate exceptions with an EC of 0x2D (GCS Data Check Exception) when data validation checks fail. When running a nested guest which has access to GCS such exceptions can be directed from EL0 to EL2 and therefore need to be forwarded to the guest hypervisor, add handling for this. Signed-off-by: Mark Brown --- arch/arm64/kvm/handle_exit.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c index a598072f36d2..2f5aef84b294 100644 --- a/arch/arm64/kvm/handle_exit.c +++ b/arch/arm64/kvm/handle_exit.c @@ -301,10 +301,18 @@ static int handle_svc(struct kvm_vcpu *vcpu) =20 static int kvm_handle_gcs(struct kvm_vcpu *vcpu) { - /* We don't expect GCS, so treat it with contempt */ - if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, GCS, IMP)) - WARN_ON_ONCE(1); + if (!kvm_has_gcs(vcpu->kvm)) { + kvm_inject_undefined(vcpu); + return 1; + } =20 + if (vcpu_has_nv(vcpu) && !is_hyp_ctxt(vcpu)) { + kvm_inject_nested_sync(vcpu, kvm_vcpu_get_esr(vcpu)); + return 1; + } + + /* We shouldn't have generated a trap in this case */ + WARN_ON_ONCE(1); kvm_inject_undefined(vcpu); return 1; } --=20 2.39.5 From nobody Sat Oct 4 03:17:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2931E2E2EF7; Wed, 20 Aug 2025 14:15:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699335; cv=none; b=L/BbWfawt22DnDoVFDgV+1Tb+w2Ga5BzQk6bCI01uHHm9+8psIvRacywh5YcZp7xPv7PoYLsdAq/MrQ3PUIiSrzARvW5Nc2qhVNlWxLtuqVGtpr5Zkt/v4rxJ1p6ObcH7ODtr7lnIeEQHL3EmSn6k4vrDlPsO+wJrj37Tf2Up60= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699335; c=relaxed/simple; bh=XqW9QBgR4CO7JeWk2qq6fqCcQ8Tlv6hAbg0b3Fasmt0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=OXtFGvCDCet6ZkMBtf84KTl3kgowWc//0eJtXKOg03obMwb24n+dX7Xq4h0ZNimrGoQLrJt5MpCFBX5I6oA3c7TY3RbR1Xvdgtk3hFYi+7mU+RqgV3seSz0ERQD7GGQE2tQNMGAPnbRvZa3XuEW6LlHtHAWQlyHGrP34MHU203U= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=vCwpma3J; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="vCwpma3J" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CAD10C116B1; Wed, 20 Aug 2025 14:15:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755699334; bh=XqW9QBgR4CO7JeWk2qq6fqCcQ8Tlv6hAbg0b3Fasmt0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=vCwpma3JIbrl27GHSb4cgxBnxXzWGcgbBXnp4Re99GnN6+gSCkCCNgm+qthDWFflp t3h8uJC555VPrSBsf9bU9rcyJW9lQ6a18h/PrtHcoaxMQV88d3WTx9uBcJbUvXrzp2 3fzVrmlTCIk59kd92DXAjgqARsCPUPgh3ySCYIJsn+b2UoYVseHA8eRNDEhKvn83H2 alhAhdh3pCJSrzzHAedbpwZEaPrUJytt0YE2TbCD9sWqyoJ3f38lPhVzRkUMLSf+5j 93JFlIa2c52vKFZsgthtBvkvfKFD3tzFz4ZXUVOfB6B6CRs4paTm8SXfN9Ex0expN6 KYdf2gX4yTLNQ== From: Mark Brown Date: Wed, 20 Aug 2025 15:14:44 +0100 Subject: [PATCH v15 4/6] KVM: arm64: Set PSTATE.EXLOCK when entering an exception Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-arm64-gcs-v15-4-5e334da18b84@kernel.org> References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> In-Reply-To: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-cff91 X-Developer-Signature: v=1; a=openpgp-sha256; l=2724; i=broonie@kernel.org; h=from:subject:message-id; bh=XqW9QBgR4CO7JeWk2qq6fqCcQ8Tlv6hAbg0b3Fasmt0=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBopdhxAZ4L+7YVt+YSme0YvQpLtyjywwn/lGMy4 cGWlmL3oQeJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaKXYcQAKCRAk1otyXVSH 0Du4B/0RDICVNAmNTsMAD3fmXlzD8V7yZ3k1cuhEFKlFN3oWsTwuBbYnsPFpMWpfvytpIh5+PDJ kjY3j1Q5tPoC85EtQyaC3sRJV0vN8adm+jbTs7czxbRfjZjHjMq28vnTMznqQ+/MbnJIktcjIVN i6ZxKpdt9HiX1JpDq2q4QWFcEueIZFZY06vYCaKn5BbXafIwHPczDloB0+Pv8pIPr8ZUCvNKYGj qvhgeZpFb17ejFruJ03OF1jH2rxGGhWKi4nR+/y3I+nWsJRBYqW0IY3VXUheN1C0xiIjLHBuQLf 9XmyV3waTjLQddrme1VsAnKUz5p/FiEqcBD8hMTxtEIVJmin X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB As per DDI 0487 RWTXBY we need to manage PSTATE.EXLOCK when entering an exception, when the exception is entered from a lower EL the bit is cleared while if entering from the same EL it is set to GCSCR_ELx.EXLOCKEN. Implement this behaviour in enter_exception64(). Signed-off-by: Mark Brown --- arch/arm64/include/uapi/asm/ptrace.h | 1 + arch/arm64/kvm/hyp/exception.c | 37 ++++++++++++++++++++++++++++++++= ++++ 2 files changed, 38 insertions(+) diff --git a/arch/arm64/include/uapi/asm/ptrace.h b/arch/arm64/include/uapi= /asm/ptrace.h index 0f39ba4f3efd..f2fb029fb61a 100644 --- a/arch/arm64/include/uapi/asm/ptrace.h +++ b/arch/arm64/include/uapi/asm/ptrace.h @@ -56,6 +56,7 @@ #define PSR_C_BIT 0x20000000 #define PSR_Z_BIT 0x40000000 #define PSR_N_BIT 0x80000000 +#define PSR_EXLOCK_BIT 0x400000000 =20 #define PSR_BTYPE_SHIFT 10 =20 diff --git a/arch/arm64/kvm/hyp/exception.c b/arch/arm64/kvm/hyp/exception.c index 95d186e0bf54..46e1d0c3038c 100644 --- a/arch/arm64/kvm/hyp/exception.c +++ b/arch/arm64/kvm/hyp/exception.c @@ -73,6 +73,38 @@ static void __vcpu_write_spsr_und(struct kvm_vcpu *vcpu,= u64 val) vcpu->arch.ctxt.spsr_und =3D val; } =20 +static unsigned long enter_exception64_gcs(struct kvm_vcpu *vcpu, + unsigned long mode, + unsigned long target_mode) +{ + u64 gcscr; + + if (!kvm_has_gcs(kern_hyp_va(vcpu->kvm))) + return 0; + + /* GCS can't be enabled for 32 bit */ + if (mode & PSR_MODE32_BIT) + return 0; + + /* When taking an exception to a higher EL EXLOCK is cleared. */ + if ((mode | PSR_MODE_THREAD_BIT) !=3D target_mode) + return 0; + + /* + * When taking an exception to the same EL EXLOCK is set to + * the effective value of GCSR_ELx.EXLOCKEN. + */ + if (vcpu_is_el2(vcpu)) + gcscr =3D __vcpu_read_sys_reg(vcpu, GCSCR_EL2); + else + gcscr =3D __vcpu_read_sys_reg(vcpu, GCSCR_EL1); + + if (gcscr & GCSCR_ELx_EXLOCKEN) + return PSR_EXLOCK_BIT; + + return 0; +} + /* * This performs the exception entry at a given EL (@target_mode), stashin= g PC * and PSTATE into ELR and SPSR respectively, and compute the new PC/PSTAT= E. @@ -162,6 +194,11 @@ static void enter_exception64(struct kvm_vcpu *vcpu, u= nsigned long target_mode, // PSTATE.BTYPE is set to zero upon any exception to AArch64 // See ARM DDI 0487E.a, pages D1-2293 to D1-2294. =20 + // PSTATE.EXLOCK is set to 0 upon any exception to a higher + // EL, or to GCSCR_ELx.EXLOCKEN for an exception to the same + // exception level. See ARM DDI 0487 RWTXBY, D.1.3.2 in K.a. + new |=3D enter_exception64_gcs(vcpu, mode, target_mode); + new |=3D PSR_D_BIT; new |=3D PSR_A_BIT; new |=3D PSR_I_BIT; --=20 2.39.5 From nobody Sat Oct 4 03:17:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 677022749E4; Wed, 20 Aug 2025 14:15:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699338; cv=none; b=ZPkbS0DvYxOmqW0LbmIZFumxyPNccCVLAgYHUXAxGlbvy/rdMMvltl+koA6yCSZvVmaKNcq3xeKI9epYAvYJrMhzmqZ74iCeYV/KBm3IFTRYCGxpOqy0i+w9r3JCG2fakByo5D+mntZFY9j14fbyusbV3uhFhtFdQ0bjLf+5fUU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699338; c=relaxed/simple; bh=giAvZ3PXu+lP80aoBjb8+UDhRd3O2Wn5C1lPnTF310M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=EgXSDkEDdQ3jmt5WmvSZjb8ds3HPAFJC9Kn1jkhba8HCVQbRRkNeNYEI4cuopClMinWqD0R+c2214das+2N/RaBHdbQM0lAGDbwd8qEXF/Fn6RSXTNVkoYRF3HTscuoqyF6TgVMf+0FVdfaNi2oRiTpkAmfXEwpnpawSGO2o+WY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Ip7Z3xpd; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Ip7Z3xpd" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3746AC4CEE7; Wed, 20 Aug 2025 14:15:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755699337; bh=giAvZ3PXu+lP80aoBjb8+UDhRd3O2Wn5C1lPnTF310M=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Ip7Z3xpdlFPHciRTuRtQr5IwnCqHeEVZBsfuT33VPsVwORgPcE5VL6xry2ycBwpnd wfBPtNKzobitDyFkEXyvXYap5Kra9svY1TfddY4I4irNGLvzmRcxlMUBh99Ael7sU8 SK+XA+yakGm+PIHDRFCFMZyrhPF8nySXfrgOgIkZDBsw201vk0XO5AICUYWx7VptbN hByEQ21LL0p6tg46AYAWXjAlMcG3aBED1qTOc+/kK3Ek/LC9fK2Z+tLxA+C+4375mo 7xKRYz/OlI0qfEhw4k40+IqULuiHrWMtVLhK6GS1x5sXNcFLXyDGzM5HGCS8kHO+s7 ERSO2efDs5Oyg== From: Mark Brown Date: Wed, 20 Aug 2025 15:14:45 +0100 Subject: [PATCH v15 5/6] KVM: arm64: Allow GCS to be enabled for guests Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-arm64-gcs-v15-5-5e334da18b84@kernel.org> References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> In-Reply-To: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown X-Mailer: b4 0.15-dev-cff91 X-Developer-Signature: v=1; a=openpgp-sha256; l=906; i=broonie@kernel.org; h=from:subject:message-id; bh=giAvZ3PXu+lP80aoBjb8+UDhRd3O2Wn5C1lPnTF310M=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBopdhxlIgAp7F1QJGg1SOe2olWOjR5Wq6td61O9 Z/r5ZBJiICJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaKXYcQAKCRAk1otyXVSH 0NFaB/sF6rAfJ/JA1Bq6Q2rjkPRJZTG7XGBeVzum/UOih8m/VQc5dqu0fxeJ/fLgNHKhqoVXi6Z OgYtSBmD0PQ5dHOixeZv6jLVpecMm+JccC3XfHFYJ7B1FOvWomyHCxCX3Wjf9yq+/pMXuUrXUzT 4Rnxzh24AOsgIY6Oylf2Pcq4/IVf15AZypVVWVnauFa7aamAL7FksYJemt0HGaRUANCsj8OnaDm LQN3slY54dDZpGVMxE6tK/FArCwalKvvRKvG2F0eNCMNrfm4cySAFsgKfYLlNW6kmbFmp1w56OZ GQnZYsoILY2BPity3gkWlDxgBnNpzw/IOxtuh84UNXEz492q X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Now that required functionality for GCS is in place expose ID_AA64PFR1_EL1.GCS, allowing guests to be given the feature. Signed-off-by: Mark Brown --- arch/arm64/kvm/sys_regs.c | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 592cb5d6497a..60e234422064 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1616,7 +1616,6 @@ static u64 __kvm_read_sanitised_id_reg(const struct k= vm_vcpu *vcpu, val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI); - val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX); val &=3D ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR); --=20 2.39.5 From nobody Sat Oct 4 03:17:12 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD57E2749F2; Wed, 20 Aug 2025 14:15:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699341; cv=none; b=QYzkoajAfvwXfCDE7VZCi0xW/4Mv3ln1INqzBBBhtXW4gg+FrK3bguArZjgjiLo7k5NgplkKtmxsiSJeijNEBbAuj2ZJiK14Z+Mc+3W2IGoPuPmYm1EPhGudRE2+w6ZjXh8XZKbzGpe6j8sIwhYhGQv1LFodJqr+ZeV+VZWRllw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755699341; c=relaxed/simple; bh=wPIUPLpFKWSmMu1QEu+vJJQNc+kUEEHQOoRK1NZ2vDM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PE+5osj37JK6QutJCqDqjdTIphnrNTy0zGu3acYrlUZB3b3DNK5kWpyfkce9BMlfLoZR0xiNYUtaWPrsO2gWdd56bqqs2KC+5akYHsninK/OyMXFEDf8DmtszUiHx5Y+RgrOUgPSthFC1wsV/yNQv8zzDtL5o+MwOzaRg50qoo4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=kmZG5J1q; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="kmZG5J1q" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 55887C113CF; Wed, 20 Aug 2025 14:15:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755699341; bh=wPIUPLpFKWSmMu1QEu+vJJQNc+kUEEHQOoRK1NZ2vDM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=kmZG5J1qK2IASLSC9mmUOZ03asyugO1XYS9QXbUYj7hzWDAftRxSWzgXb7rspMogX OR6YFX3iiB03FFpMQC8UVHqnM//31MFpHx84cI/CA7CJ8ErLGhKOO9Pk8zrdc8b2G/ nQmnM6xGxK+xMk4f/nQjvDSf2xnn4uCO2T7GIqczwWcvNgwJw9THh9Dtq4iwx+6WOC W23dtailrymU0UkjCsep8wnmn4eEOP+Z67BzabSfviRn23bOCztChy6Ar0cEkZoz2E WUqYhs+tt5K40GuNrOHyTEO97gyeNEsP0K0Xqs2JdzguSFZNOgx3+DAGmbPPi7broO VN6uJ87kqIM5Q== From: Mark Brown Date: Wed, 20 Aug 2025 15:14:46 +0100 Subject: [PATCH v15 6/6] KVM: selftests: arm64: Add GCS registers to get-reg-list Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-arm64-gcs-v15-6-5e334da18b84@kernel.org> References: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> In-Reply-To: <20250820-arm64-gcs-v15-0-5e334da18b84@kernel.org> To: Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Shuah Khan Cc: linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown , Thiago Jung Bauermann X-Mailer: b4 0.15-dev-cff91 X-Developer-Signature: v=1; a=openpgp-sha256; l=2417; i=broonie@kernel.org; h=from:subject:message-id; bh=wPIUPLpFKWSmMu1QEu+vJJQNc+kUEEHQOoRK1NZ2vDM=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBopdhyDAaZhoeX2SX98ztHnen6rpOaISQ1qMMre 6NxPNHBo6eJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCaKXYcgAKCRAk1otyXVSH 0AftB/46SR8tYmd+0v3pKWE2DpZHe/5YMDZVHA8BTogrK9IHwuJVIkSjUEBRHmqPttGu8KIbZo4 lrHgSwjBt1UK8VOvAgX/9esEE8/B59viGamL3g6J9vVJo9s2HLRyQuai7Ybo6ZOjlkAKht+yaAb G1jn8n2CizjWCoc4yHry7YebxDZzUapJtaFhCNVmQtOhL9Nb121y0pCNIabpVANuzhOd0MPWSJy OyRxiiPSMcuu16IlXl2sNUwtRAVoR5w6nTGwFgevJe3NlnI73YZ2oAVmakF6w1dDKbw9HSbFPzN UTi2C7fk83+lN+i//BCOUl+tbey0qi4f7gAgJAD/Sa1oG3dj X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB GCS adds new registers GCSCR_EL1, GCSCRE0_EL1, GCSPR_EL1 and GCSPR_EL0. Add these to those validated by get-reg-list. Reviewed-by: Thiago Jung Bauermann Signed-off-by: Mark Brown --- tools/testing/selftests/kvm/arm64/get-reg-list.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/get-reg-list.c b/tools/testi= ng/selftests/kvm/arm64/get-reg-list.c index 011fad95dd02..9bf33064377b 100644 --- a/tools/testing/selftests/kvm/arm64/get-reg-list.c +++ b/tools/testing/selftests/kvm/arm64/get-reg-list.c @@ -42,6 +42,12 @@ struct feature_id_reg { static struct feature_id_reg feat_id_regs[] =3D { REG_FEAT(TCR2_EL1, ID_AA64MMFR3_EL1, TCRX, IMP), REG_FEAT(TCR2_EL2, ID_AA64MMFR3_EL1, TCRX, IMP), + REG_FEAT(GCSPR_EL0, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSPR_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSPR_EL2, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCRE0_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCR_EL1, ID_AA64PFR1_EL1, GCS, IMP), + REG_FEAT(GCSCR_EL2, ID_AA64PFR1_EL1, GCS, IMP), REG_FEAT(PIRE0_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), REG_FEAT(PIRE0_EL2, ID_AA64MMFR3_EL1, S1PIE, IMP), REG_FEAT(PIR_EL1, ID_AA64MMFR3_EL1, S1PIE, IMP), @@ -486,6 +492,9 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 2, 0, 1), /* TTBR1_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 2), /* TCR_EL1 */ ARM64_SYS_REG(3, 0, 2, 0, 3), /* TCR2_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 0), /* GCSCR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 1), /* GCSPR_EL1 */ + ARM64_SYS_REG(3, 0, 2, 5, 2), /* GCSCRE0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 0), /* AFSR0_EL1 */ ARM64_SYS_REG(3, 0, 5, 1, 1), /* AFSR1_EL1 */ ARM64_SYS_REG(3, 0, 5, 2, 0), /* ESR_EL1 */ @@ -502,6 +511,7 @@ static __u64 base_regs[] =3D { ARM64_SYS_REG(3, 0, 13, 0, 4), /* TPIDR_EL1 */ ARM64_SYS_REG(3, 0, 14, 1, 0), /* CNTKCTL_EL1 */ ARM64_SYS_REG(3, 2, 0, 0, 0), /* CSSELR_EL1 */ + ARM64_SYS_REG(3, 3, 2, 5, 1), /* GCSPR_EL0 */ ARM64_SYS_REG(3, 3, 10, 2, 4), /* POR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 2), /* TPIDR_EL0 */ ARM64_SYS_REG(3, 3, 13, 0, 3), /* TPIDRRO_EL0 */ @@ -740,6 +750,8 @@ static __u64 el2_regs[] =3D { SYS_REG(PIRE0_EL2), SYS_REG(PIR_EL2), SYS_REG(POR_EL2), + SYS_REG(GCSPR_EL2), + SYS_REG(GCSCR_EL2), SYS_REG(AMAIR_EL2), SYS_REG(VBAR_EL2), SYS_REG(CONTEXTIDR_EL2), --=20 2.39.5