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While SM6150 currently shares the same configuration as SC7180, its hardware capabilities differ. Explicitly listing it ensures clarity and avoids potential issues if SC7180 support evolves in the future. Signed-off-by: Xiangxu Yin --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 9923b065323bbab99de5079b674a0317f3074373..996d0132e084d401db85014a1a4= e445d00d62ed8 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -27,6 +27,7 @@ properties: - qcom,sc8280xp-dp - qcom,sc8280xp-edp - qcom,sdm845-dp + - qcom,sm6150-dp - qcom,sm8350-dp - qcom,sm8650-dp - items: --=20 2.34.1 From nobody Sat Oct 4 04:59:43 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B61F22E0924 for ; Wed, 20 Aug 2025 09:35:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed4ec100sm20954305ad.116.2025.08.20.02.35.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 02:35:46 -0700 (PDT) From: Xiangxu Yin Date: Wed, 20 Aug 2025 17:34:44 +0800 Subject: [PATCH v3 02/14] dt-bindings: phy: Add QMP USB3+DP PHY for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-add-displayport-support-for-qcs615-platform-v3-2-a43bd25ec39c@oss.qualcomm.com> References: <20250820-add-displayport-support-for-qcs615-platform-v3-0-a43bd25ec39c@oss.qualcomm.com> In-Reply-To: <20250820-add-displayport-support-for-qcs615-platform-v3-0-a43bd25ec39c@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , quic_lliu6@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755682520; l=3426; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=955LdwJghMXcL5Oa+X/F1FbgTdWO2XwHgQyUzbm6CDw=; b=nRN16ajcM4hDuEKG4MGhqYaO9MQPThBPfr7/k5iQv2p8RAz3Bpvm3qgoHRjh9h0AQnJ7Lr8uJ zPjRkWKFQ6FDsj88aANvA9/ugZbqSMVWLWriyLXGLLoVvPm0Bkvhv/o X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIwMDAxMyBTYWx0ZWRfXzTwTyDEVvWI6 roZP027ruMU2nKzs/bcwTsiKaVYBp9+nzCDSQJ4GEsfovt4S1cjInkDAYY+ns3uSh4Ys04oSr6K 9jcUIcLtM43T2UUkym2r4R2fmwOY3oNF0TEB85eAQ5+EsczmA9x9/5SDSO2ZHQExLcNRBY2wuUM M1ywCoh1Z4C3u8tATSDYLsgOkASHrqEnFzv2K5QzXf00zadc0WEScU2Wrd7zloEPFuAkqebH6HZ 84JY3N4WOBlBrH8LH2wKqaG7FJZQtNr1dOOhdoNp3d3+hUbSbhFPKtuSlbdbPyPWRAkjWOiEeIl aSDuDBead8HpjrAdMv3qu5JTLNkhLviAIbS+O5Y/FSiOFdypnDYiaX3j1yxpGEj3V8M3Ok9mYYx VvcxnGYINGmohAhx397NHjXH+X9m7Q== X-Proofpoint-ORIG-GUID: 4gm83GrwLcF5ODIakKjaRajcoVX6DIcd X-Proofpoint-GUID: 4gm83GrwLcF5ODIakKjaRajcoVX6DIcd X-Authority-Analysis: v=2.4 cv=SoXJKPO0 c=1 sm=1 tr=0 ts=68a596f4 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=W1uZXkYdwnJCVkvvQWQA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-20_03,2025-08-20_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 adultscore=0 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 malwarescore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2508110000 definitions=main-2508200013 Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY on QCS615 Platform. This PHY supports both USB3 and DP functionality over USB-C, with PHY mode switching capability. It does not support combo mode. Signed-off-by: Xiangxu Yin --- .../bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml | 108 +++++++++++++++++= ++++ 1 file changed, 108 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-p= hy.yaml b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.= yaml new file mode 100644 index 0000000000000000000000000000000000000000..c2b1fbab2930f0653f4ddb95f7b= 54d8fe994f92d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom,qcs615-qmp-usb3dp-phy.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/qcom,qcs615-qmp-usb3dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QMP USB3-DP PHY controller (DP, QCS615) + +maintainers: + - Vinod Koul + +description: + The QMP PHY controller supports physical layer functionality for both + USB3 and DisplayPort over USB-C. While it enables mode switching + between USB3 and DisplayPort, but does not support combo mode. + +properties: + compatible: + enum: + - qcom,qcs615-qmp-usb3-dp-phy + + reg: + maxItems: 1 + + clocks: + maxItems: 2 + + clock-names: + items: + - const: cfg_ahb + - const: ref + + resets: + maxItems: 2 + + reset-names: + items: + - const: phy_phy + - const: dp_phy + + vdda-phy-supply: true + + vdda-pll-supply: true + + "#clock-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + "#phy-cells": + const: 1 + description: + See include/dt-bindings/phy/phy-qcom-qmp.h + + qcom,tcsr-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to TCSR hardware block + - description: offset of the VLS CLAMP register + - items: + - description: phandle to TCSR hardware block + - description: offset of the DP PHY mode register + description: Clamp and PHY mode register present in the TCSR + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - vdda-phy-supply + - vdda-pll-supply + - "#clock-cells" + - "#phy-cells" + - qcom,tcsr-reg + +additionalProperties: false + +examples: + - | + #include + #include + + phy@88e8000 { + compatible =3D "qcom,qcs615-qmp-usb3-dp-phy"; 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This is a preparatory cleanup to enable USB + DP dual mode. Signed-off-by: Xiangxu Yin Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 50 ++++++++++++++++------------= ---- 1 file changed, 25 insertions(+), 25 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 5e7fcb26744a4401c3076960df9c0dcbec7fdef7..e484caec2be20121cfe287c507b= 17af28fb9f211 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -454,7 +454,7 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 -static int qmp_usbc_init(struct phy *phy) +static int qmp_usbc_com_init(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -504,7 +504,7 @@ static int qmp_usbc_init(struct phy *phy) return ret; } =20 -static int qmp_usbc_exit(struct phy *phy) +static int qmp_usbc_com_exit(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -518,7 +518,7 @@ static int qmp_usbc_exit(struct phy *phy) return 0; } =20 -static int qmp_usbc_power_on(struct phy *phy) +static int qmp_usbc_usb_power_on(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -566,7 +566,7 @@ static int qmp_usbc_power_on(struct phy *phy) return ret; } =20 -static int qmp_usbc_power_off(struct phy *phy) +static int qmp_usbc_usb_power_off(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -587,20 +587,20 @@ static int qmp_usbc_power_off(struct phy *phy) return 0; } =20 -static int qmp_usbc_enable(struct phy *phy) +static int qmp_usbc_usb_enable(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); int ret; =20 mutex_lock(&qmp->phy_mutex); =20 - ret =3D qmp_usbc_init(phy); + ret =3D qmp_usbc_com_init(phy); if (ret) goto out_unlock; =20 - ret =3D qmp_usbc_power_on(phy); + ret =3D qmp_usbc_usb_power_on(phy); if (ret) { - qmp_usbc_exit(phy); + qmp_usbc_com_exit(phy); goto out_unlock; } =20 @@ -611,19 +611,19 @@ static int qmp_usbc_enable(struct phy *phy) return ret; } =20 -static int qmp_usbc_disable(struct phy *phy) +static int qmp_usbc_usb_disable(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); int ret; =20 qmp->usb_init_count--; - ret =3D qmp_usbc_power_off(phy); + ret =3D qmp_usbc_usb_power_off(phy); if (ret) return ret; - return qmp_usbc_exit(phy); + return qmp_usbc_com_exit(phy); } =20 -static int qmp_usbc_set_mode(struct phy *phy, enum phy_mode mode, int subm= ode) +static int qmp_usbc_usb_set_mode(struct phy *phy, enum phy_mode mode, int = submode) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); =20 @@ -632,10 +632,10 @@ static int qmp_usbc_set_mode(struct phy *phy, enum ph= y_mode mode, int submode) return 0; } =20 -static const struct phy_ops qmp_usbc_phy_ops =3D { - .init =3D qmp_usbc_enable, - .exit =3D qmp_usbc_disable, - .set_mode =3D qmp_usbc_set_mode, +static const struct phy_ops qmp_usbc_usb_phy_ops =3D { + .init =3D qmp_usbc_usb_enable, + .exit =3D qmp_usbc_usb_disable, + .set_mode =3D qmp_usbc_usb_set_mode, .owner =3D THIS_MODULE, }; =20 @@ -865,11 +865,11 @@ static int qmp_usbc_typec_switch_set(struct typec_swi= tch_dev *sw, qmp->orientation =3D orientation; =20 if (qmp->usb_init_count) { - qmp_usbc_power_off(qmp->phy); - qmp_usbc_exit(qmp->phy); + qmp_usbc_usb_power_off(qmp->phy); + qmp_usbc_com_exit(qmp->phy); =20 - qmp_usbc_init(qmp->phy); - qmp_usbc_power_on(qmp->phy); + qmp_usbc_com_init(qmp->phy); + qmp_usbc_usb_power_on(qmp->phy); } =20 mutex_unlock(&qmp->phy_mutex); @@ -907,7 +907,7 @@ static int qmp_usbc_typec_switch_register(struct qmp_us= bc *qmp) } #endif =20 -static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qmp, struct device_no= de *np) +static int qmp_usbc_parse_usb_dt_legacy(struct qmp_usbc *qmp, struct devic= e_node *np) { struct platform_device *pdev =3D to_platform_device(qmp->dev); struct device *dev =3D qmp->dev; @@ -969,7 +969,7 @@ static int qmp_usbc_parse_dt_legacy(struct qmp_usbc *qm= p, struct device_node *np return 0; } =20 -static int qmp_usbc_parse_dt(struct qmp_usbc *qmp) +static int qmp_usbc_parse_usb_dt(struct qmp_usbc *qmp) { struct platform_device *pdev =3D to_platform_device(qmp->dev); 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Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index e484caec2be20121cfe287c507b17af28fb9f211..5afe090b546977a11265bbffa7c= 355feb8c72dfa 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -284,6 +284,11 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; =20 +enum qmp_phy_usbc_type { + QMP_PHY_USBC_USB3_ONLY, + QMP_PHY_USBC_USB3_DP, +}; + struct qmp_usbc_offsets { u16 serdes; u16 pcs; @@ -298,6 +303,7 @@ struct qmp_usbc_offsets { /* struct qmp_phy_cfg - per-PHY initialization config */ struct qmp_phy_cfg { const struct qmp_usbc_offsets *offsets; + const enum qmp_phy_usbc_type type; =20 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; @@ -408,6 +414,7 @@ static const struct qmp_usbc_offsets qmp_usbc_offsets_v= 3_qcm2290 =3D { =20 static const struct qmp_phy_cfg msm8998_usb3phy_cfg =3D { .offsets =3D &qmp_usbc_offsets_v3_qcm2290, + .type =3D QMP_PHY_USBC_USB3_ONLY, =20 .serdes_tbl =3D msm8998_usb3_serdes_tbl, .serdes_tbl_num =3D ARRAY_SIZE(msm8998_usb3_serdes_tbl), @@ -424,6 +431,7 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg =3D= { =20 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg =3D { .offsets =3D &qmp_usbc_offsets_v3_qcm2290, + .type =3D QMP_PHY_USBC_USB3_ONLY, =20 .serdes_tbl =3D qcm2290_usb3_serdes_tbl, .serdes_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_serdes_tbl), @@ -440,6 +448,7 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg =3D= { =20 static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D { .offsets =3D &qmp_usbc_offsets_v3_qcm2290, + .type =3D QMP_PHY_USBC_USB3_ONLY, =20 .serdes_tbl =3D qcm2290_usb3_serdes_tbl, .serdes_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_serdes_tbl), --=20 2.34.1 From nobody Sat Oct 4 04:59:43 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC1BC2DCC11 for ; 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Also update qmp_usbc struct to track DP-related resources and state. This enables support for USB/DP switchable Type-C PHYs that operate in either mode. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 73 ++++++++++++++++++++++++----= ---- 1 file changed, 55 insertions(+), 18 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 5afe090b546977a11265bbffa7c355feb8c72dfa..6b0e86ec43ded3d850f68f248a7= 4c39f74ecb5bb 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -298,14 +298,19 @@ struct qmp_usbc_offsets { /* for PHYs with >=3D 2 lanes */ u16 tx2; u16 rx2; + + u16 dp_serdes; + u16 dp_txa; + u16 dp_txb; + u16 dp_dp_phy; }; =20 -/* struct qmp_phy_cfg - per-PHY initialization config */ +struct qmp_usbc; struct qmp_phy_cfg { const struct qmp_usbc_offsets *offsets; const enum qmp_phy_usbc_type type; =20 - /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ + /* Init sequence for USB PHY blocks - serdes, tx, rx, pcs */ const struct qmp_phy_init_tbl *serdes_tbl; int serdes_tbl_num; const struct qmp_phy_init_tbl *tx_tbl; @@ -315,6 +320,27 @@ struct qmp_phy_cfg { const struct qmp_phy_init_tbl *pcs_tbl; int pcs_tbl_num; =20 + /* Init sequence for DP PHY blocks - serdes, tx, rbr, hbr, hbr2 */ + const struct qmp_phy_init_tbl *dp_serdes_tbl; + int dp_serdes_tbl_num; + const struct qmp_phy_init_tbl *dp_tx_tbl; + int dp_tx_tbl_num; + const struct qmp_phy_init_tbl *serdes_tbl_rbr; + int serdes_tbl_rbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr; + int serdes_tbl_hbr_num; + const struct qmp_phy_init_tbl *serdes_tbl_hbr2; + int serdes_tbl_hbr2_num; + + const u8 (*swing_tbl)[4][4]; + const u8 (*pre_emphasis_tbl)[4][4]; + + /* DP PHY callbacks */ + void (*dp_aux_init)(struct qmp_usbc *qmp); + void (*configure_dp_tx)(struct qmp_usbc *qmp); + int (*configure_dp_phy)(struct qmp_usbc *qmp); + int (*calibrate_dp_phy)(struct qmp_usbc *qmp); + /* regulators to be requested */ const char * const *vreg_list; int num_vregs; @@ -335,25 +361,36 @@ struct qmp_usbc { void __iomem *rx; void __iomem *tx2; void __iomem *rx2; - - struct regmap *tcsr_map; - u32 vls_clamp_reg; + void __iomem *dp_dp_phy; + void __iomem *dp_tx; + void __iomem *dp_tx2; + void __iomem *dp_serdes; =20 struct clk *pipe_clk; + struct clk_fixed_rate pipe_clk_fixed; + + struct clk_hw dp_link_hw; + struct clk_hw dp_pixel_hw; struct clk_bulk_data *clks; int num_clks; int num_resets; struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; =20 + struct regmap *tcsr_map; + u32 vls_clamp_reg; + u32 dp_phy_mode_reg; + struct mutex phy_mutex; =20 + struct phy *usb_phy; enum phy_mode mode; unsigned int usb_init_count; =20 - struct phy *phy; - - struct clk_fixed_rate pipe_clk_fixed; + struct phy *dp_phy; + unsigned int dp_aux_cfg; + struct phy_configure_opts_dp dp_opts; + unsigned int dp_init_count; =20 struct typec_switch_dev *sw; enum typec_orientation orientation; @@ -699,7 +736,7 @@ static int __maybe_unused qmp_usbc_runtime_suspend(stru= ct device *dev) =20 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); =20 - if (!qmp->phy->init_count) { + if (!qmp->usb_init_count && !qmp->dp_init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } @@ -719,7 +756,7 @@ static int __maybe_unused qmp_usbc_runtime_resume(struc= t device *dev) =20 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); =20 - if (!qmp->phy->init_count) { + if (!qmp->usb_init_count && !qmp->dp_init_count) { dev_vdbg(dev, "PHY not initialized, bailing out\n"); return 0; } @@ -874,11 +911,11 @@ static int qmp_usbc_typec_switch_set(struct typec_swi= tch_dev *sw, qmp->orientation =3D orientation; =20 if (qmp->usb_init_count) { - qmp_usbc_usb_power_off(qmp->phy); - qmp_usbc_com_exit(qmp->phy); + qmp_usbc_usb_power_off(qmp->usb_phy); + qmp_usbc_com_exit(qmp->usb_phy); =20 - qmp_usbc_com_init(qmp->phy); - qmp_usbc_usb_power_on(qmp->phy); + qmp_usbc_com_init(qmp->usb_phy); + qmp_usbc_usb_power_on(qmp->usb_phy); } =20 mutex_unlock(&qmp->phy_mutex); @@ -1106,14 +1143,14 @@ static int qmp_usbc_probe(struct platform_device *p= dev) if (ret) goto err_node_put; =20 - qmp->phy =3D devm_phy_create(dev, np, &qmp_usbc_usb_phy_ops); - if (IS_ERR(qmp->phy)) { - ret =3D PTR_ERR(qmp->phy); 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Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 139 +++++++++++++++++++++++++++= ++++ 1 file changed, 139 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 6b0e86ec43ded3d850f68f248a74c39f74ecb5bb..61128d606238321d1b573655b3b= 987226aa2d594 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -284,6 +284,86 @@ static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_= tbl[] =3D { QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), }; =20 +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x37), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x0e), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_CTRL, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x06), + QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), + QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), + QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x40), + QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x08), + QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x05), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x02), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_rbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x2c), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xbf), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x21), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x24), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x69), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x80), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x07), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x3f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x38), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_serdes_tbl_hbr2[] =3D { + QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x20), + QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x8c), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x0a), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x7f), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x70), + QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc4), +}; + +static const struct qmp_phy_init_tbl qcs615_qmp_dp_tx_tbl[] =3D { + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x2b), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x2f), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x12), + QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x12), +}; + enum qmp_phy_usbc_type { QMP_PHY_USBC_USB3_ONLY, QMP_PHY_USBC_USB3_DP, @@ -449,6 +529,34 @@ static const struct qmp_usbc_offsets qmp_usbc_offsets_= v3_qcm2290 =3D { .rx2 =3D 0x800, }; =20 +static const struct qmp_usbc_offsets qmp_usbc_usb3dp_offsets_qcs615 =3D { + .serdes =3D 0x0, + .pcs =3D 0xc00, + .pcs_misc =3D 0xa00, + .tx =3D 0x200, + .rx =3D 0x400, + .tx2 =3D 0x600, + .rx2 =3D 0x800, + .dp_serdes =3D 0x1c00, + .dp_txa =3D 0x1400, + .dp_txb =3D 0x1800, + .dp_dp_phy =3D 0x1000, +}; + +static const u8 qmp_dp_pre_emphasis_hbr2_rbr[4][4] =3D { + {0x00, 0x0b, 0x12, 0xff}, + {0x00, 0x0a, 0x12, 0xff}, + {0x00, 0x0c, 0xff, 0xff}, + {0xff, 0xff, 0xff, 0xff} +}; + +static const u8 qmp_dp_voltage_swing_hbr2_rbr[4][4] =3D { + {0x07, 0x0f, 0x14, 0xff}, + {0x11, 0x1d, 0x1f, 0xff}, + {0x18, 0x1f, 0xff, 0xff}, + {0xff, 0xff, 0xff, 0xff} +}; + static const struct qmp_phy_cfg msm8998_usb3phy_cfg =3D { .offsets =3D &qmp_usbc_offsets_v3_qcm2290, .type =3D QMP_PHY_USBC_USB3_ONLY, @@ -500,6 +608,37 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D= { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 +static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg =3D { + .offsets =3D &qmp_usbc_usb3dp_offsets_qcs615, + .type =3D QMP_PHY_USBC_USB3_DP, + + .serdes_tbl =3D qcm2290_usb3_serdes_tbl, + .serdes_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_serdes_tbl), + .tx_tbl =3D qcm2290_usb3_tx_tbl, + .tx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_tx_tbl), + .rx_tbl =3D qcm2290_usb3_rx_tbl, + .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), + .pcs_tbl =3D qcm2290_usb3_pcs_tbl, + .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), + + .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, + + .dp_serdes_tbl =3D qcs615_qmp_dp_serdes_tbl, + .dp_serdes_tbl_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl), + .dp_tx_tbl =3D qcs615_qmp_dp_tx_tbl, + .dp_tx_tbl_num =3D ARRAY_SIZE(qcs615_qmp_dp_tx_tbl), + + .serdes_tbl_rbr =3D qcs615_qmp_dp_serdes_tbl_rbr, + .serdes_tbl_rbr_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_rbr), + .serdes_tbl_hbr =3D qcs615_qmp_dp_serdes_tbl_hbr, + .serdes_tbl_hbr_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr), + .serdes_tbl_hbr2 =3D qcs615_qmp_dp_serdes_tbl_hbr2, + .serdes_tbl_hbr2_num =3D ARRAY_SIZE(qcs615_qmp_dp_serdes_tbl_hbr2), + + .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, + .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, +}; 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This enables per-PHY customization and simplifies initialization logic for USB-only and USB/DP switchable PHYs. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 108 +++++++++++++++------------= ---- 1 file changed, 53 insertions(+), 55 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 61128d606238321d1b573655b3b987226aa2d594..4e797b7e65da0e3a827efa9a179= f1c150c1b8b00 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -421,8 +421,9 @@ struct qmp_phy_cfg { int (*configure_dp_phy)(struct qmp_usbc *qmp); int (*calibrate_dp_phy)(struct qmp_usbc *qmp); =20 - /* regulators to be requested */ - const char * const *vreg_list; + const char * const *reset_list; + int num_resets; + const struct regulator_bulk_data *vreg_list; int num_vregs; =20 /* array of registers with different offsets */ @@ -453,7 +454,6 @@ struct qmp_usbc { struct clk_hw dp_pixel_hw; struct clk_bulk_data *clks; int num_clks; - int num_resets; struct reset_control_bulk_data *resets; struct regulator_bulk_data *vregs; =20 @@ -514,9 +514,18 @@ static const char * const usb3phy_reset_l[] =3D { "phy_phy", "phy", }; =20 -/* list of regulators */ -static const char * const qmp_phy_vreg_l[] =3D { - "vdda-phy", "vdda-pll", +static const char * const usb3dpphy_reset_l[] =3D { + "phy_phy", "dp_phy", +}; + +static const struct regulator_bulk_data qmp_phy_usb_vreg_l[] =3D { + { .supply =3D "vdda-phy" }, + { .supply =3D "vdda-pll" }, +}; + +static const struct regulator_bulk_data qmp_phy_usbdp_vreg_l[] =3D { + { .supply =3D "vdda-phy", .init_load_uA =3D 21800 }, + { .supply =3D "vdda-phy", .init_load_uA =3D 36000 }, }; =20 static const struct qmp_usbc_offsets qmp_usbc_offsets_v3_qcm2290 =3D { @@ -569,8 +578,10 @@ static const struct qmp_phy_cfg msm8998_usb3phy_cfg = =3D { .rx_tbl_num =3D ARRAY_SIZE(msm8998_usb3_rx_tbl), .pcs_tbl =3D msm8998_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(msm8998_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .reset_list =3D usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3phy_reset_l), + .vreg_list =3D qmp_phy_usb_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_usb_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout, }; =20 @@ -586,8 +597,10 @@ static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = =3D { .rx_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .reset_list =3D usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3phy_reset_l), + .vreg_list =3D qmp_phy_usb_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_usb_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 @@ -603,8 +616,10 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D= { .rx_tbl_num =3D ARRAY_SIZE(sdm660_usb3_rx_tbl), .pcs_tbl =3D qcm2290_usb3_pcs_tbl, .pcs_tbl_num =3D ARRAY_SIZE(qcm2290_usb3_pcs_tbl), - .vreg_list =3D qmp_phy_vreg_l, - .num_vregs =3D ARRAY_SIZE(qmp_phy_vreg_l), + .reset_list =3D usb3phy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3phy_reset_l), + .vreg_list =3D qmp_phy_usb_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_usb_vreg_l), .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 @@ -637,6 +652,11 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = =3D { =20 .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, + + .reset_list =3D usb3dpphy_reset_l, + .num_resets =3D ARRAY_SIZE(usb3dpphy_reset_l), + .vreg_list =3D qmp_phy_usbdp_vreg_l, + .num_vregs =3D ARRAY_SIZE(qmp_phy_usbdp_vreg_l), }; =20 static int qmp_usbc_com_init(struct phy *phy) @@ -653,13 +673,13 @@ static int qmp_usbc_com_init(struct phy *phy) return ret; } =20 - ret =3D reset_control_bulk_assert(qmp->num_resets, qmp->resets); + ret =3D reset_control_bulk_assert(cfg->num_resets, qmp->resets); if (ret) { dev_err(qmp->dev, "reset assert failed\n"); goto err_disable_regulators; } =20 - ret =3D reset_control_bulk_deassert(qmp->num_resets, qmp->resets); + ret =3D reset_control_bulk_deassert(cfg->num_resets, qmp->resets); if (ret) { dev_err(qmp->dev, "reset deassert failed\n"); goto err_disable_regulators; @@ -682,7 +702,7 @@ static int qmp_usbc_com_init(struct phy *phy) return 0; =20 err_assert_reset: - reset_control_bulk_assert(qmp->num_resets, qmp->resets); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); err_disable_regulators: regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 @@ -694,7 +714,7 @@ static int qmp_usbc_com_exit(struct phy *phy) struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; =20 - reset_control_bulk_assert(qmp->num_resets, qmp->resets); + reset_control_bulk_assert(cfg->num_resets, qmp->resets); =20 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); =20 @@ -921,42 +941,22 @@ static const struct dev_pm_ops qmp_usbc_pm_ops =3D { qmp_usbc_runtime_resume, NULL) }; =20 -static int qmp_usbc_vreg_init(struct qmp_usbc *qmp) +static int qmp_usbc_reset_init(struct qmp_usbc *qmp) { const struct qmp_phy_cfg *cfg =3D qmp->cfg; - struct device *dev =3D qmp->dev; - int num =3D cfg->num_vregs; - int i; - - qmp->vregs =3D devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); - if (!qmp->vregs) - return -ENOMEM; - - for (i =3D 0; i < num; i++) - qmp->vregs[i].supply =3D cfg->vreg_list[i]; - - return devm_regulator_bulk_get(dev, num, qmp->vregs); -} - -static int qmp_usbc_reset_init(struct qmp_usbc *qmp, - const char *const *reset_list, - int num_resets) -{ struct device *dev =3D qmp->dev; int i; int ret; =20 - qmp->resets =3D devm_kcalloc(dev, num_resets, + qmp->resets =3D devm_kcalloc(dev, cfg->num_resets, sizeof(*qmp->resets), GFP_KERNEL); if (!qmp->resets) return -ENOMEM; =20 - for (i =3D 0; i < num_resets; i++) - qmp->resets[i].id =3D reset_list[i]; + for (i =3D 0; i < cfg->num_resets; i++) + qmp->resets[i].id =3D cfg->reset_list[i]; =20 - qmp->num_resets =3D num_resets; - - ret =3D devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->reset= s); + ret =3D devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->= resets); if (ret) return dev_err_probe(dev, ret, "failed to get resets\n"); =20 @@ -1146,11 +1146,6 @@ static int qmp_usbc_parse_usb_dt_legacy(struct qmp_u= sbc *qmp, struct device_node =20 qmp->num_clks =3D ret; =20 - ret =3D qmp_usbc_reset_init(qmp, usb3phy_legacy_reset_l, - ARRAY_SIZE(usb3phy_legacy_reset_l)); - if (ret) - return ret; - return 0; } =20 @@ -1187,14 +1182,9 @@ static int qmp_usbc_parse_usb_dt(struct qmp_usbc *qm= p) qmp->pipe_clk =3D devm_clk_get(dev, "pipe"); if (IS_ERR(qmp->pipe_clk)) { return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), - "failed to get pipe clock\n"); + "failed to get pipe clock\n"); } =20 - ret =3D qmp_usbc_reset_init(qmp, usb3phy_reset_l, - ARRAY_SIZE(usb3phy_reset_l)); - if (ret) - return ret; - return 0; } =20 @@ -1228,6 +1218,7 @@ static int qmp_usbc_probe(struct platform_device *pde= v) struct phy_provider *phy_provider; struct device_node *np; struct qmp_usbc *qmp; + const struct qmp_phy_cfg *cfg; int ret; =20 qmp =3D devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -1239,13 +1230,20 @@ static int qmp_usbc_probe(struct platform_device *p= dev) =20 qmp->orientation =3D TYPEC_ORIENTATION_NORMAL; =20 - qmp->cfg =3D of_device_get_match_data(dev); - if (!qmp->cfg) + cfg =3D of_device_get_match_data(dev); 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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed4ec100sm20954305ad.116.2025.08.20.02.36.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 02:36:36 -0700 (PDT) From: Xiangxu Yin Date: Wed, 20 Aug 2025 17:34:50 +0800 Subject: [PATCH v3 08/14] phy: qcom: qmp-usbc: Add DP PHY configuration support for QCS615 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-add-displayport-support-for-qcs615-platform-v3-8-a43bd25ec39c@oss.qualcomm.com> References: <20250820-add-displayport-support-for-qcs615-platform-v3-0-a43bd25ec39c@oss.qualcomm.com> In-Reply-To: <20250820-add-displayport-support-for-qcs615-platform-v3-0-a43bd25ec39c@oss.qualcomm.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Kuogee Hsieh , Vinod Koul , Kishon Vijay Abraham I , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com, Bjorn Andersson , Konrad Dybcio , Dmitry Baryshkov , quic_lliu6@quicinc.com, Xiangxu Yin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755682521; l=10287; i=xiangxu.yin@oss.qualcomm.com; s=20241125; h=from:subject:message-id; bh=Au5j4uIKg5CFe2fNrABPgg+lLTFB0b1BIdCK5Ts5W+c=; b=guwW8rllyedPULooM5NTzerFgU+BA/4+KLRsVf2pixoMYW2Fuaeqy/UQZMYnDcs+OPKrjppTW +04HNfdiJpbAWiniy5aI6csA5/zHli4yR+cqTcHESnxgLA5bE+Esw/C X-Developer-Key: i=xiangxu.yin@oss.qualcomm.com; a=ed25519; pk=F1TwipJzpywfbt3n/RPi4l/A4AVF+QC89XzCHgZYaOc= X-Authority-Analysis: v=2.4 cv=ZJKOWX7b c=1 sm=1 tr=0 ts=68a59726 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=ewgvXcV7Hd3kUc6h8x0A:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: 5-oBvOqQsocf2V_9Tr8X5kWgX8e_ccfG X-Proofpoint-GUID: 5-oBvOqQsocf2V_9Tr8X5kWgX8e_ccfG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIwMDAxMyBTYWx0ZWRfX71337hi2u4CW ARIPX3COcOxTj2Z45FhijQBzQM+Y+yoQuRrfn9nIsrXWLGw7NLQfHfYcC/zctPt8P1QOuQwEmD5 0RXIxtnwYGEtoYSK8wVU1WwTlihSpOuApn7nHoluJXUodvTTdV/krdlGE9MjBHkpbfFlY9Ba1j6 WANkZxtKbtQhsLJtD2Bl5KCSuye4zorq1qLN8yO0nt0WXcRpph8hpfR5pYVqWJ0zBIlETIxDulW UOqTkqC06+ZJH7wQOoq7UqUJPuYLiba0YofgoS+AbDg/I2EjSj3yvGhhzM0Si2LxbVx9mI+ppMN Qj7UzP6vziwoVXuqUBqsgRjMna8my9js9IX+Rjp5UIS+9Un2ccg+GT3hSnU4JVMAq3NiiMvlUaz xyQydyuyIRpWw76kIkVTn4Rgn2zf9g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-20_03,2025-08-20_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 adultscore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 clxscore=1015 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2508110000 definitions=main-2508200013 Introduce DisplayPort PHY configuration routines for QCS615, including aux channel setup, lane control, voltage swing tuning, clock programming and calibration. These callbacks are registered via qmp_phy_cfg to enable DP mode on USB/DP switchable Type-C PHYs. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 251 +++++++++++++++++++++++++= ++++ 2 files changed, 252 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h b/drivers/phy/qualc= omm/phy-qcom-qmp-dp-phy.h index 0ebd405bcaf0cac8215550bfc9b226f30cc43a59..59885616405f878885d0837838a= 0bac1899fb69f 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-dp-phy.h @@ -25,6 +25,7 @@ #define QSERDES_DP_PHY_AUX_CFG7 0x03c #define QSERDES_DP_PHY_AUX_CFG8 0x040 #define QSERDES_DP_PHY_AUX_CFG9 0x044 +#define QSERDES_DP_PHY_VCO_DIV 0x068 =20 /* QSERDES COM_BIAS_EN_CLKBUFLR_EN bits */ # define QSERDES_V3_COM_BIAS_EN 0x0001 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 4e797b7e65da0e3a827efa9a179f1c150c1b8b00..1508a4a5f57aff85318485b7952= 8325f28a825a4 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -28,6 +28,9 @@ #include "phy-qcom-qmp.h" #include "phy-qcom-qmp-pcs-misc-v3.h" =20 +#include "phy-qcom-qmp-dp-phy.h" +#include "phy-qcom-qmp-dp-phy-v3.h" + #define PHY_INIT_COMPLETE_TIMEOUT 10000 =20 /* set of registers with offsets different per-PHY */ @@ -623,6 +626,11 @@ static const struct qmp_phy_cfg sdm660_usb3phy_cfg =3D= { .regs =3D qmp_v3_usb3phy_regs_layout_qcm2290, }; =20 +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp); +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp); +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp); +static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp); + static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg =3D { .offsets =3D &qmp_usbc_usb3dp_offsets_qcs615, .type =3D QMP_PHY_USBC_USB3_DP, @@ -653,6 +661,11 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = =3D { .swing_tbl =3D &qmp_dp_voltage_swing_hbr2_rbr, .pre_emphasis_tbl =3D &qmp_dp_pre_emphasis_hbr2_rbr, =20 + .dp_aux_init =3D qcs615_qmp_dp_aux_init, + .configure_dp_tx =3D qcs615_qmp_configure_dp_tx, + .configure_dp_phy =3D qcs615_qmp_configure_dp_phy, + .calibrate_dp_phy =3D qcs615_qmp_calibrate_dp_phy, + .reset_list =3D usb3dpphy_reset_l, .num_resets =3D ARRAY_SIZE(usb3dpphy_reset_l), .vreg_list =3D qmp_phy_usbdp_vreg_l, @@ -723,6 +736,244 @@ static int qmp_usbc_com_exit(struct phy *phy) return 0; } =20 +static void qcs615_qmp_dp_aux_init(struct qmp_usbc *qmp) +{ + writel(DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN, + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_CTL_LANE_2_3_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN, + qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0); + writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1); + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2); + writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3); + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4); + writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5); + writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6); + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7); + writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8); + writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9); + qmp->dp_aux_cfg =3D 0; + + writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK | + PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK | + PHY_AUX_REQ_ERR_MASK, + qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK); +} + +static int qcs615_qmp_configure_dp_swing(struct qmp_usbc *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; + void __iomem *tx =3D qmp->dp_tx; + void __iomem *tx2 =3D qmp->dp_tx2; + unsigned int v_level =3D 0, p_level =3D 0; + u8 voltage_swing_cfg, pre_emphasis_cfg; + int i; + + if (dp_opts->lanes > 4) { + dev_err(qmp->dev, "Invalid lane_num(%d)\n", dp_opts->lanes); + return -EINVAL; + } + + for (i =3D 0; i < dp_opts->lanes; i++) { + v_level =3D max(v_level, dp_opts->voltage[i]); + p_level =3D max(p_level, dp_opts->pre[i]); + } + + if (v_level > 4 || p_level > 4) { + dev_err(qmp->dev, "Invalid v(%d) | p(%d) level)\n", + v_level, p_level); + return -EINVAL; + } + + voltage_swing_cfg =3D (*cfg->swing_tbl)[v_level][p_level]; + pre_emphasis_cfg =3D (*cfg->pre_emphasis_tbl)[v_level][p_level]; + + voltage_swing_cfg |=3D DP_PHY_TXn_TX_DRV_LVL_MUX_EN; + pre_emphasis_cfg |=3D DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN; + + if (voltage_swing_cfg =3D=3D 0xff && pre_emphasis_cfg =3D=3D 0xff) + return -EINVAL; + + writel(voltage_swing_cfg, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(voltage_swing_cfg, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(pre_emphasis_cfg, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + + return 0; +} + +static void qmp_usbc_configure_dp_mode(struct qmp_usbc *qmp) +{ + bool reverse =3D (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE); + u32 val; + + val =3D DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | + DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_LANE_0_1_PWRDN | DP_PHY_PD_= CTL_LANE_2_3_PWRDN; + + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + if (reverse) + writel(0xc9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); + else + writel(0xd9, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE); +} + +static int qmp_usbc_configure_dp_clocks(struct qmp_usbc *qmp) +{ + const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; + u32 phy_vco_div; + unsigned long pixel_freq; + + switch (dp_opts->link_rate) { + case 1620: + phy_vco_div =3D 0x1; + pixel_freq =3D 1620000000UL / 2; + break; + case 2700: + phy_vco_div =3D 0x1; + pixel_freq =3D 2700000000UL / 2; + break; + case 5400: + phy_vco_div =3D 0x2; + pixel_freq =3D 5400000000UL / 4; + break; + default: + dev_err(qmp->dev, "link rate:%d not supported\n", dp_opts->link_rate); + return -EINVAL; + } + writel(phy_vco_div, qmp->dp_dp_phy + QSERDES_DP_PHY_VCO_DIV); + + clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000); + clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq); + + return 0; +} + +static void qcs615_qmp_configure_dp_tx(struct qmp_usbc *qmp) +{ + void __iomem *tx =3D qmp->dp_tx; + void __iomem *tx2 =3D qmp->dp_tx2; + + /* program default setting first */ + writel(0x2a, tx + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx + QSERDES_V3_TX_TX_EMP_POST1_LVL); + writel(0x2a, tx2 + QSERDES_V3_TX_TX_DRV_LVL); + writel(0x20, tx2 + QSERDES_V3_TX_TX_EMP_POST1_LVL); + + qcs615_qmp_configure_dp_swing(qmp); +} + +static int qcs615_qmp_configure_dp_phy(struct qmp_usbc *qmp) +{ + u32 status; + int ret; + + qmp_usbc_configure_dp_mode(qmp); + + writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL); + writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL); + + ret =3D qmp_usbc_configure_dp_clocks(qmp); + if (ret) + return ret; + + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + writel(0x20, qmp->dp_serdes + QSERDES_COM_RESETSM_CNTRL); + + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_C_READY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)) { + dev_err(qmp->dev, "C_READY not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "FREQ_DONE not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(qmp->dp_serdes + QSERDES_COM_CMN_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PLL_LOCKED not ready\n"); + return -ETIMEDOUT; + } + + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(0)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "TSYNC_DONE not ready\n"); + return -ETIMEDOUT; + } + + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PHY_READY not ready\n"); + return -ETIMEDOUT; + } + + writel(0x3f, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(0x10, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(0x0a, qmp->dp_tx + QSERDES_V3_TX_TX_POL_INV); + writel(0x3f, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN); + writel(0x10, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN); + writel(0x0a, qmp->dp_tx2 + QSERDES_V3_TX_TX_POL_INV); + + writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG); + + if (readl_poll_timeout(qmp->dp_dp_phy + QSERDES_V3_DP_PHY_STATUS, + status, + ((status & BIT(1)) > 0), + 500, + 10000)){ + dev_err(qmp->dev, "PHY_READY not ready\n"); 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Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 163 +++++++++++++++++++++++++++= ++++ 1 file changed, 163 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 1508a4a5f57aff85318485b79528325f28a825a4..a1495a2029cf038bb65c36e42d0= a4f633e544558 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -22,6 +22,8 @@ #include #include #include +#include +#include =20 #include "phy-qcom-qmp-common.h" =20 @@ -1088,6 +1090,157 @@ static int qmp_usbc_usb_set_mode(struct phy *phy, e= num phy_mode mode, int submod return 0; } =20 +static int qmp_usbc_dp_enable(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int ret; + + if (qmp->dp_init_count) { + dev_err(qmp->dev, "DP already inited\n"); + return 0; + } + + mutex_lock(&qmp->phy_mutex); + + ret =3D qmp_usbc_com_init(phy); + if (ret) + goto dp_init_unlock; + + cfg->dp_aux_init(qmp); + + qmp->dp_init_count++; + +dp_init_unlock: + mutex_unlock(&qmp->phy_mutex); + return ret; +} + +static int qmp_usbc_dp_disable(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + + mutex_lock(&qmp->phy_mutex); + + qmp_usbc_com_exit(phy); + + qmp->dp_init_count--; + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_configure(struct phy *phy, union phy_configure_opts= *opts) +{ + const struct phy_configure_opts_dp *dp_opts =3D &opts->dp; + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + + mutex_lock(&qmp->phy_mutex); + + memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts)); + if (qmp->dp_opts.set_voltages) { + cfg->configure_dp_tx(qmp); + qmp->dp_opts.set_voltages =3D 0; + } + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_calibrate(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + int ret =3D 0; + + mutex_lock(&qmp->phy_mutex); + + if (cfg->calibrate_dp_phy) { + ret =3D cfg->calibrate_dp_phy(qmp); + if (ret) { + dev_err(qmp->dev, "dp calibrate err(%d)\n", ret); + mutex_unlock(&qmp->phy_mutex); + return ret; + } + } + + mutex_unlock(&qmp->phy_mutex); + return 0; +} + +static int qmp_usbc_dp_serdes_init(struct qmp_usbc *qmp) +{ + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + void __iomem *serdes =3D qmp->dp_serdes; + const struct phy_configure_opts_dp *dp_opts =3D &qmp->dp_opts; + + qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl, + cfg->dp_serdes_tbl_num); + + switch (dp_opts->link_rate) { + case 1620: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr, + cfg->serdes_tbl_rbr_num); + break; + case 2700: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr, + cfg->serdes_tbl_hbr_num); + break; + case 5400: + qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2, + cfg->serdes_tbl_hbr2_num); + break; + default: + /* Other link rates aren't supported */ + return -EINVAL; + } + + return 0; +} + +static int qmp_usbc_dp_power_on(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + + void __iomem *tx =3D qmp->dp_tx; + void __iomem *tx2 =3D qmp->dp_tx2; + + mutex_lock(&qmp->phy_mutex); + + qmp_usbc_dp_serdes_init(qmp); + + qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1); + qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2); + + /* Configure special DP tx tunings */ + cfg->configure_dp_tx(qmp); + + /* Configure link rate, swing, etc. */ + cfg->configure_dp_phy(qmp); + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + +static int qmp_usbc_dp_power_off(struct phy *phy) +{ + struct qmp_usbc *qmp =3D phy_get_drvdata(phy); + + mutex_lock(&qmp->phy_mutex); + + /* Assert DP PHY power down */ + writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL); + + mutex_unlock(&qmp->phy_mutex); + + return 0; +} + static const struct phy_ops qmp_usbc_usb_phy_ops =3D { .init =3D qmp_usbc_usb_enable, .exit =3D qmp_usbc_usb_disable, @@ -1095,6 +1248,16 @@ static const struct phy_ops qmp_usbc_usb_phy_ops =3D= { .owner =3D THIS_MODULE, }; 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Introduce mutual exclusion between USB and DP PHY modes to prevent simultaneous activation. Also update com_init/com_exit to reflect DP mode initialization and cleanup. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 60 +++++++++++++++++++++++++---= ---- 1 file changed, 47 insertions(+), 13 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index a1495a2029cf038bb65c36e42d0a4f633e544558..821398653bef23e1915d9d3a3a2= 950b0bfbefb9a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -674,7 +674,7 @@ static const struct qmp_phy_cfg qcs615_usb3dp_phy_cfg = =3D { .num_vregs =3D ARRAY_SIZE(qmp_phy_usbdp_vreg_l), }; =20 -static int qmp_usbc_com_init(struct phy *phy) +static int qmp_usbc_com_init(struct phy *phy, bool is_dp) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); const struct qmp_phy_cfg *cfg =3D qmp->cfg; @@ -704,15 +704,20 @@ static int qmp_usbc_com_init(struct phy *phy) if (ret) goto err_assert_reset; =20 - qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); + if (!is_dp) { + qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); =20 #define SW_PORTSELECT_VAL BIT(0) #define SW_PORTSELECT_MUX BIT(1) - /* Use software based port select and switch on typec orientation */ - val =3D SW_PORTSELECT_MUX; - if (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE) - val |=3D SW_PORTSELECT_VAL; - writel(val, qmp->pcs_misc); + /* Use software based port select and switch on typec orientation */ + val =3D SW_PORTSELECT_MUX; + if (qmp->orientation =3D=3D TYPEC_ORIENTATION_REVERSE) + val |=3D SW_PORTSELECT_VAL; + writel(val, qmp->pcs_misc); + } + + if (qmp->tcsr_map && qmp->dp_phy_mode_reg) + regmap_write(qmp->tcsr_map, qmp->dp_phy_mode_reg, is_dp); =20 return 0; =20 @@ -733,6 +738,9 @@ static int qmp_usbc_com_exit(struct phy *phy) =20 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); =20 + if (qmp->tcsr_map && qmp->dp_phy_mode_reg) + regmap_write(qmp->tcsr_map, qmp->dp_phy_mode_reg, 0); + regulator_bulk_disable(cfg->num_vregs, qmp->vregs); =20 return 0; @@ -1045,6 +1053,17 @@ static int qmp_usbc_usb_power_off(struct phy *phy) return 0; } =20 +static int qmp_check_mutex_phy(struct qmp_usbc *qmp, bool is_dp) +{ + if ((is_dp && qmp->usb_init_count) || + (!is_dp && qmp->dp_init_count)) { + dev_err(qmp->dev, "%s PHY busy\n", is_dp ? "USB" : "DP"); + return -EBUSY; + } + + return 0; +} + static int qmp_usbc_usb_enable(struct phy *phy) { struct qmp_usbc *qmp =3D phy_get_drvdata(phy); @@ -1052,7 +1071,11 @@ static int qmp_usbc_usb_enable(struct phy *phy) =20 mutex_lock(&qmp->phy_mutex); =20 - ret =3D qmp_usbc_com_init(phy); + ret =3D qmp_check_mutex_phy(qmp, false); + if (ret) + goto out_unlock; + + ret =3D qmp_usbc_com_init(phy, false); if (ret) goto out_unlock; =20 @@ -1103,7 +1126,11 @@ static int qmp_usbc_dp_enable(struct phy *phy) =20 mutex_lock(&qmp->phy_mutex); =20 - ret =3D qmp_usbc_com_init(phy); + ret =3D qmp_check_mutex_phy(qmp, true); + if (ret) + goto dp_init_unlock; + + ret =3D qmp_usbc_com_init(phy, true); if (ret) goto dp_init_unlock; =20 @@ -1467,7 +1494,7 @@ static int qmp_usbc_typec_switch_set(struct typec_swi= tch_dev *sw, qmp_usbc_usb_power_off(qmp->usb_phy); qmp_usbc_com_exit(qmp->usb_phy); =20 - qmp_usbc_com_init(qmp->usb_phy); + qmp_usbc_com_init(qmp->usb_phy, false); qmp_usbc_usb_power_on(qmp->usb_phy); } =20 @@ -1602,13 +1629,13 @@ static int qmp_usbc_parse_usb_dt(struct qmp_usbc *q= mp) return 0; } =20 -static int qmp_usbc_parse_vls_clamp(struct qmp_usbc *qmp) +static int qmp_usbc_parse_tcsr(struct qmp_usbc *qmp) { struct of_phandle_args tcsr_args; struct device *dev =3D qmp->dev; int ret; =20 - /* for backwards compatibility ignore if there is no property */ + /* for backwards compatibility ignore if there is 1 or no property */ ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1= , 0, &tcsr_args); if (ret =3D=3D -ENOENT) @@ -1623,6 +1650,13 @@ static int qmp_usbc_parse_vls_clamp(struct qmp_usbc = *qmp) =20 qmp->vls_clamp_reg =3D tcsr_args.args[0]; =20 + ret =3D of_parse_phandle_with_fixed_args(dev->of_node, "qcom,tcsr-reg", 1= , 1, + &tcsr_args); + if (ret =3D=3D -ENOENT) + return 0; + + qmp->dp_phy_mode_reg =3D tcsr_args.args[0]; + return 0; } =20 @@ -1665,7 +1699,7 @@ static int qmp_usbc_probe(struct platform_device *pde= v) if (ret) return ret; =20 - ret =3D qmp_usbc_parse_vls_clamp(qmp); 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Implement clock provider logic for USB and DP branches, and extend PHY translation to support both USB and DP instances. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 331 +++++++++++++++++++++++++++= +--- 1 file changed, 299 insertions(+), 32 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 821398653bef23e1915d9d3a3a2950b0bfbefb9a..74b9f75c8864efe270f394bfbfd= 748793dada1f5 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -995,6 +995,11 @@ static int qmp_usbc_usb_power_on(struct phy *phy) qmp_configure(qmp->dev, qmp->serdes, cfg->serdes_tbl, cfg->serdes_tbl_num); =20 + if (IS_ERR(qmp->pipe_clk)) { + return dev_err_probe(qmp->dev, PTR_ERR(qmp->pipe_clk), + "pipe clock not defined\n"); + } + ret =3D clk_prepare_enable(qmp->pipe_clk); if (ret) { dev_err(qmp->dev, "pipe_clk enable failed err=3D%d\n", ret); @@ -1365,11 +1370,13 @@ static int __maybe_unused qmp_usbc_runtime_resume(s= truct device *dev) if (ret) return ret; =20 - ret =3D clk_prepare_enable(qmp->pipe_clk); - if (ret) { - dev_err(dev, "pipe_clk enable failed, err=3D%d\n", ret); - clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); - return ret; + if (!IS_ERR(qmp->pipe_clk)) { + ret =3D clk_prepare_enable(qmp->pipe_clk); + if (ret) { + dev_err(dev, "pipe_clk enable failed, err=3D%d\n", ret); + clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); + return ret; + } } =20 qmp_usbc_disable_autonomous_mode(qmp); @@ -1422,9 +1429,23 @@ static int qmp_usbc_clk_init(struct qmp_usbc *qmp) return devm_clk_bulk_get_optional(dev, num, qmp->clks); } =20 -static void phy_clk_release_provider(void *res) +static struct clk_hw *qmp_usbc_clks_hw_get(struct of_phandle_args *clkspec= , void *data) { - of_clk_del_provider(res); + struct qmp_usbc *qmp =3D data; + + if (clkspec->args_count =3D=3D 0) + return &qmp->pipe_clk_fixed.hw; + + switch (clkspec->args[0]) { + case QMP_USB43DP_USB3_PIPE_CLK: + return &qmp->pipe_clk_fixed.hw; + case QMP_USB43DP_DP_LINK_CLK: + return &qmp->dp_link_hw; + case QMP_USB43DP_DP_VCO_DIV_CLK: + return &qmp->dp_pixel_hw; + } + + return ERR_PTR(-EINVAL); } =20 /* @@ -1453,8 +1474,11 @@ static int phy_pipe_clk_register(struct qmp_usbc *qm= p, struct device_node *np) =20 ret =3D of_property_read_string(np, "clock-output-names", &init.name); if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); - return ret; + char name[64]; + + /* Clock name is not mandatory. */ + snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev)); + init.name =3D name; } =20 init.ops =3D &clk_fixed_rate_ops; @@ -1463,19 +1487,7 @@ static int phy_pipe_clk_register(struct qmp_usbc *qm= p, struct device_node *np) fixed->fixed_rate =3D 125000000; fixed->hw.init =3D &init; =20 - ret =3D devm_clk_hw_register(qmp->dev, &fixed->hw); - if (ret) - return ret; - - ret =3D of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); - if (ret) - return ret; - - /* - * Roll a devm action because the clock provider is the child node, but - * the child node is not actually a device. - */ - return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); + return devm_clk_hw_register(qmp->dev, &fixed->hw); } =20 #if IS_ENABLED(CONFIG_TYPEC) @@ -1660,6 +1672,235 @@ static int qmp_usbc_parse_tcsr(struct qmp_usbc *qmp) return 0; } =20 +static int qmp_usbc_parse_usb3dp_dt(struct qmp_usbc *qmp) +{ + struct platform_device *pdev =3D to_platform_device(qmp->dev); + const struct qmp_phy_cfg *cfg =3D qmp->cfg; + const struct qmp_usbc_offsets *offs =3D cfg->offsets; + struct device *dev =3D qmp->dev; + void __iomem *base; + int ret; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + qmp->dp_serdes =3D base + offs->dp_serdes; + qmp->dp_tx =3D base + offs->dp_txa; + qmp->dp_tx2 =3D base + offs->dp_txb; + qmp->dp_dp_phy =3D base + offs->dp_dp_phy; + qmp->serdes =3D base + offs->serdes; + qmp->pcs =3D base + offs->pcs; + if (offs->pcs_misc) + qmp->pcs_misc =3D base + offs->pcs_misc; + qmp->tx =3D base + offs->tx; + qmp->rx =3D base + offs->rx; + + qmp->tx2 =3D base + offs->tx2; + qmp->rx2 =3D base + offs->rx2; + + ret =3D qmp_usbc_clk_init(qmp); + if (ret) + return ret; + + qmp->pipe_clk =3D devm_clk_get(dev, "pipe"); + if (IS_ERR(qmp->pipe_clk)) { + /* usb3dp allow no pipe clk define */ + if (cfg->type =3D=3D QMP_PHY_USBC_USB3_ONLY) + return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), + "failed to get pipe clock\n"); + } + + return 0; +} + +/* + * Display Port PLL driver block diagram for branch clocks + * + * +------------------------------+ + * | DP_VCO_CLK | + * | | + * | +-------------------+ | + * | | (DP PLL/VCO) | | + * | +---------+---------+ | + * | v | + * | +----------+-----------+ | + * | | hsclk_divsel_clk_src | | + * | +----------+-----------+ | + * +------------------------------+ + * | + * +---------<---------v------------>----------+ + * | | + * +--------v----------------+ | + * | dp_phy_pll_link_clk | | + * | link_clk | | + * +--------+----------------+ | + * | | + * | | + * v v + * Input to DISPCC block | + * for link clk, crypto clk | + * and interface clock | + * | + * | + * +--------<------------+-----------------+---<---+ + * | | | + * +----v---------+ +--------v-----+ +--------v------+ + * | vco_divided | | vco_divided | | vco_divided | + * | _clk_src | | _clk_src | | _clk_src | + * | | | | | | + * |divsel_six | | divsel_two | | divsel_four | + * +-------+------+ +-----+--------+ +--------+------+ + * | | | + * v---->----------v-------------<------v + * | + * +----------+-----------------+ + * | dp_phy_pll_vco_div_clk | + * +---------+------------------+ + * | + * v + * Input to DISPCC block + * for DP pixel clock + * + */ +static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_r= ate_request *req) +{ + switch (req->rate) { + case 1620000000UL / 2: + case 2700000000UL / 2: + /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */ + return 0; + default: + return -EINVAL; + } +} + +static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsig= ned long parent_rate) +{ + const struct qmp_usbc *qmp; + const struct phy_configure_opts_dp *dp_opts; + + qmp =3D container_of(hw, struct qmp_usbc, dp_pixel_hw); + + dp_opts =3D &qmp->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + return 1620000000UL / 2; + case 2700: + return 2700000000UL / 2; + case 5400: + return 5400000000UL / 4; + default: + return 0; + } +} + +static const struct clk_ops qmp_dp_pixel_clk_ops =3D { + .determine_rate =3D qmp_dp_pixel_clk_determine_rate, + .recalc_rate =3D qmp_dp_pixel_clk_recalc_rate, +}; + +static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_ra= te_request *req) +{ + switch (req->rate) { + case 162000000: + case 270000000: + case 540000000: + return 0; + default: + return -EINVAL; + } +} + +static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsign= ed long parent_rate) +{ + const struct qmp_usbc *qmp; + const struct phy_configure_opts_dp *dp_opts; + + qmp =3D container_of(hw, struct qmp_usbc, dp_link_hw); + dp_opts =3D &qmp->dp_opts; + + switch (dp_opts->link_rate) { + case 1620: + case 2700: + case 5400: + return dp_opts->link_rate * 100000; + default: + return 0; + } +} + +static const struct clk_ops qmp_dp_link_clk_ops =3D { + .determine_rate =3D qmp_dp_link_clk_determine_rate, + .recalc_rate =3D qmp_dp_link_clk_recalc_rate, +}; + +static int phy_dp_clks_register(struct qmp_usbc *qmp, struct device_node *= np) +{ + struct clk_init_data init =3D { }; + char name[64]; + int ret; + + snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev)); + init.ops =3D &qmp_dp_link_clk_ops; + init.name =3D name; + qmp->dp_link_hw.init =3D &init; + ret =3D devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw); + if (ret < 0) { + dev_err(qmp->dev, "link clk reg fail ret=3D%d\n", ret); + return ret; + } + + snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev)); + init.ops =3D &qmp_dp_pixel_clk_ops; + init.name =3D name; + qmp->dp_pixel_hw.init =3D &init; + ret =3D devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw); + if (ret) { + dev_err(qmp->dev, "pxl clk reg fail ret=3D%d\n", ret); + return ret; + } + + return 0; +} + +static int qmp_usbc_register_clocks(struct qmp_usbc *qmp, struct device_no= de *np) +{ + int ret; + + if (!IS_ERR(qmp->pipe_clk)) { + ret =3D phy_pipe_clk_register(qmp, np); + if (ret) + return ret; + } + + if (qmp->cfg->type =3D=3D QMP_PHY_USBC_USB3_DP) { + ret =3D phy_dp_clks_register(qmp, np); + if (ret) + return ret; + } + + return devm_of_clk_add_hw_provider(qmp->dev, qmp_usbc_clks_hw_get, qmp); +} + +static struct phy *qmp_usbc_phy_xlate(struct device *dev, const struct of_= phandle_args *args) +{ + struct qmp_usbc *qmp =3D dev_get_drvdata(dev); + + if (args->args_count =3D=3D 0) + return qmp->usb_phy; + + switch (args->args[0]) { + case QMP_USB43DP_USB3_PHY: + return qmp->usb_phy; + case QMP_USB43DP_DP_PHY: + return qmp->dp_phy; + } + + return ERR_PTR(-EINVAL); +} + static int qmp_usbc_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -1703,16 +1944,32 @@ static int qmp_usbc_probe(struct platform_device *p= dev) if (ret) return ret; =20 - /* Check for legacy binding with child node. */ - np =3D of_get_child_by_name(dev->of_node, "phy"); - if (np) { - ret =3D qmp_usbc_parse_usb_dt_legacy(qmp, np); - } else { + if (qmp->cfg->type =3D=3D QMP_PHY_USBC_USB3_DP) { np =3D of_node_get(dev->of_node); - ret =3D qmp_usbc_parse_usb_dt(qmp); + + ret =3D qmp_usbc_parse_usb3dp_dt(qmp); + if (ret) { + dev_err(qmp->dev, "parse DP dt fail ret=3D%d\n", ret); + goto err_node_put; + } + + ret =3D drm_aux_bridge_register(dev); + if (ret) { + dev_err(qmp->dev, "aux bridge reg fail ret=3D%d\n", ret); + goto err_node_put; + } + } else { + /* Check for legacy binding with child node. */ + np =3D of_get_child_by_name(dev->of_node, "phy"); + if (np) { + ret =3D qmp_usbc_parse_usb_dt_legacy(qmp, np); + } else { + np =3D of_node_get(dev->of_node); + ret =3D qmp_usbc_parse_usb_dt(qmp); + } + if (ret) + goto err_node_put; } - if (ret) - goto err_node_put; =20 pm_runtime_set_active(dev); ret =3D devm_pm_runtime_enable(dev); @@ -1724,7 +1981,7 @@ static int qmp_usbc_probe(struct platform_device *pde= v) */ pm_runtime_forbid(dev); =20 - ret =3D phy_pipe_clk_register(qmp, np); + ret =3D qmp_usbc_register_clocks(qmp, np); if (ret) goto err_node_put; =20 @@ -1737,9 +1994,19 @@ static int qmp_usbc_probe(struct platform_device *pd= ev) =20 phy_set_drvdata(qmp->usb_phy, qmp); =20 + if (qmp->cfg->type =3D=3D QMP_PHY_USBC_USB3_DP) { + qmp->dp_phy =3D devm_phy_create(dev, np, &qmp_usbc_dp_phy_ops); + if (IS_ERR(qmp->dp_phy)) { + ret =3D PTR_ERR(qmp->dp_phy); + dev_err(dev, "failed to create PHY: %d\n", ret); + goto err_node_put; + } + phy_set_drvdata(qmp->dp_phy, qmp); + } + of_node_put(np); =20 - phy_provider =3D devm_of_phy_provider_register(dev, of_phy_simple_xlate); + phy_provider =3D devm_of_phy_provider_register(dev, qmp_usbc_phy_xlate); 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This enables the driver to apply the correct setup for PHYs that support mode switching between USB and DisplayPort. Signed-off-by: Xiangxu Yin --- drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcom= m/phy-qcom-qmp-usbc.c index 74b9f75c8864efe270f394bfbfd748793dada1f5..d56e334d58576d15a9ac047abe4= 0a479e790a324 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c @@ -2022,6 +2022,9 @@ static const struct of_device_id qmp_usbc_of_match_ta= ble[] =3D { }, { .compatible =3D "qcom,qcm2290-qmp-usb3-phy", .data =3D &qcm2290_usb3phy_cfg, + }, { + .compatible =3D "qcom,qcs615-qmp-usb3-dp-phy", + .data =3D &qcs615_usb3dp_phy_cfg, }, { .compatible =3D "qcom,qcs615-qmp-usb3-phy", .data =3D &qcm2290_usb3phy_cfg, --=20 2.34.1 From nobody Sat Oct 4 04:59:43 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACC8118991E for ; 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While SM6150 lacks some SC7180 features (e.g. HBR3), current msm_dp_desc_sc7180 data is sufficient. Listing it explicitly ensures future compatibility. Reviewed-by: Dmitry Baryshkov Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_display.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/d= p_display.c index d87d47cc7ec3eb757ac192c411000bc50b824c59..ddb22b50490035779904d4cab20= e2fee7e0f9657 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -196,6 +196,7 @@ static const struct of_device_id msm_dp_dt_match[] =3D { { .compatible =3D "qcom,sc8280xp-dp", .data =3D &msm_dp_desc_sc8280xp }, { .compatible =3D "qcom,sc8280xp-edp", .data =3D &msm_dp_desc_sc8280xp }, { .compatible =3D "qcom,sdm845-dp", .data =3D &msm_dp_desc_sdm845 }, + { .compatible =3D "qcom,sm6150-dp", .data =3D &msm_dp_desc_sc7180 }, { .compatible =3D "qcom,sm8350-dp", .data =3D &msm_dp_desc_sc7180 }, { .compatible =3D "qcom,sm8650-dp", .data =3D &msm_dp_desc_sm8650 }, { .compatible =3D "qcom,x1e80100-dp", .data =3D &msm_dp_desc_x1e80100 }, --=20 2.34.1 From nobody Sat Oct 4 04:59:43 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 193402DFF18 for ; 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Add lane mapping configuration for the DisplayPort (DP) controller on the QCS615 platform. QCS615 platform requires non-default logical-to-physical lane mapping due to its unique hardware routing. Unlike the standard mapping sequence <0 1 2 3>, QCS615 uses <3 2 0 1>, which necessitates explicit configuration via the data-lanes property in the device tree. This ensures correct signal routing between the DP controller and PHY. The DP PHY supports polarity inversion (PN swap) but does not support lane swapping. Therefore, lane mapping should be handled in the DP controller domain using REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING. Signed-off-by: Xiangxu Yin --- drivers/gpu/drm/msm/dp/dp_ctrl.c | 10 ++--- drivers/gpu/drm/msm/dp/dp_link.c | 71 +++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/dp/dp_link.h | 5 +++ drivers/gpu/drm/msm/dp/dp_panel.c | 78 +++++------------------------------= ---- drivers/gpu/drm/msm/dp/dp_panel.h | 3 -- 5 files changed, 90 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_c= trl.c index c42fd2c17a328f6deae211c9cd57cc7416a9365a..cbcc7c2f0ffc4696749b6c43818= d20853ddec069 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -423,13 +423,13 @@ static void msm_dp_ctrl_config_ctrl(struct msm_dp_ctr= l_private *ctrl) =20 static void msm_dp_ctrl_lane_mapping(struct msm_dp_ctrl_private *ctrl) { - u32 ln_0 =3D 0, ln_1 =3D 1, ln_2 =3D 2, ln_3 =3D 3; /* One-to-One mapping= */ + u32 *lane_map =3D ctrl->link->lane_map; u32 ln_mapping; =20 - ln_mapping =3D ln_0 << LANE0_MAPPING_SHIFT; - ln_mapping |=3D ln_1 << LANE1_MAPPING_SHIFT; - ln_mapping |=3D ln_2 << LANE2_MAPPING_SHIFT; - ln_mapping |=3D ln_3 << LANE3_MAPPING_SHIFT; + ln_mapping =3D lane_map[0] << LANE0_MAPPING_SHIFT; + ln_mapping |=3D lane_map[1] << LANE1_MAPPING_SHIFT; + ln_mapping |=3D lane_map[2] << LANE2_MAPPING_SHIFT; + ln_mapping |=3D lane_map[3] << LANE3_MAPPING_SHIFT; =20 msm_dp_write_link(ctrl, REG_DP_LOGICAL2PHYSICAL_LANE_MAPPING, ln_mapping); diff --git a/drivers/gpu/drm/msm/dp/dp_link.c b/drivers/gpu/drm/msm/dp/dp_l= ink.c index 66e1bbd80db3a28f5f16d083486752007ceaf3f7..7c7a4aa584eb42a0ca7c6ec45de= 585cde8639cb4 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.c +++ b/drivers/gpu/drm/msm/dp/dp_link.c @@ -6,12 +6,14 @@ #define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ =20 #include +#include #include =20 #include "dp_reg.h" #include "dp_link.h" #include "dp_panel.h" =20 +#define DP_LINK_RATE_HBR2 540000 /* kbytes */ #define DP_TEST_REQUEST_MASK 0x7F =20 enum audio_sample_rate { @@ -37,6 +39,7 @@ struct msm_dp_link_request { =20 struct msm_dp_link_private { u32 prev_sink_count; + struct device *dev; struct drm_device *drm_dev; struct drm_dp_aux *aux; struct msm_dp_link msm_dp_link; @@ -1210,10 +1213,73 @@ u32 msm_dp_link_get_test_bits_depth(struct msm_dp_l= ink *msm_dp_link, u32 bpp) return tbd; } =20 +static u32 msm_dp_link_link_frequencies(struct device_node *of_node) +{ + struct device_node *endpoint; + u64 frequency =3D 0; + int cnt; + + endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ + if (!endpoint) + return 0; + + cnt =3D of_property_count_u64_elems(endpoint, "link-frequencies"); + + if (cnt > 0) + of_property_read_u64_index(endpoint, "link-frequencies", + cnt - 1, &frequency); + of_node_put(endpoint); + + do_div(frequency, + 10 * /* from symbol rate to link rate */ + 1000); /* kbytes */ + + return frequency; +} + +static int msm_dp_link_parse_dt(struct msm_dp_link *msm_dp_link) +{ + struct msm_dp_link_private *link; + struct device_node *of_node; + int cnt; + u32 lane_map[DP_MAX_NUM_DP_LANES] =3D {0}; + + link =3D container_of(msm_dp_link, struct msm_dp_link_private, msm_dp_lin= k); + of_node =3D link->dev->of_node; + + /* + * data-lanes is the property of msm_dp_out endpoint + */ + cnt =3D drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LA= NES); + if (cnt < 0) { + /* legacy code, data-lanes is the property of mdss_dp node */ + cnt =3D drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); + } + + if (cnt > 0) { + struct device_node *endpoint; + + msm_dp_link->max_dp_lanes =3D cnt; + endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, -1); + of_property_read_u32_array(endpoint, "data-lanes", lane_map, cnt); + } else { + msm_dp_link->max_dp_lanes =3D DP_MAX_NUM_DP_LANES; /* 4 lanes */ + } + + memcpy(msm_dp_link->lane_map, lane_map, msm_dp_link->max_dp_lanes * sizeo= f(u32)); + + msm_dp_link->max_dp_link_rate =3D msm_dp_link_link_frequencies(of_node); + if (!msm_dp_link->max_dp_link_rate) + msm_dp_link->max_dp_link_rate =3D DP_LINK_RATE_HBR2; + + return 0; +} + struct msm_dp_link *msm_dp_link_get(struct device *dev, struct drm_dp_aux = *aux) { struct msm_dp_link_private *link; struct msm_dp_link *msm_dp_link; + int ret; =20 if (!dev || !aux) { DRM_ERROR("invalid input\n"); @@ -1225,9 +1291,14 @@ struct msm_dp_link *msm_dp_link_get(struct device *d= ev, struct drm_dp_aux *aux) return ERR_PTR(-ENOMEM); =20 link->aux =3D aux; + link->dev =3D dev; =20 mutex_init(&link->psm_mutex); msm_dp_link =3D &link->msm_dp_link; =20 + ret =3D msm_dp_link_parse_dt(msm_dp_link); + if (ret) + return ERR_PTR(ret); + return msm_dp_link; } diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_l= ink.h index ba47c6d19fbfacfc58031263e4a2f5a6d9c2c229..b1eb2de6d2a7693f17aa2f25665= 7110af839533d 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.h +++ b/drivers/gpu/drm/msm/dp/dp_link.h @@ -12,6 +12,7 @@ #define DS_PORT_STATUS_CHANGED 0x200 #define DP_TEST_BIT_DEPTH_UNKNOWN 0xFFFFFFFF #define DP_LINK_CAP_ENHANCED_FRAMING (1 << 0) +#define DP_MAX_NUM_DP_LANES 4 =20 struct msm_dp_link_info { unsigned char revision; @@ -72,6 +73,10 @@ struct msm_dp_link { struct msm_dp_link_test_audio test_audio; struct msm_dp_link_phy_params phy_params; struct msm_dp_link_info link_params; + + u32 lane_map[DP_MAX_NUM_DP_LANES]; + u32 max_dp_lanes; + u32 max_dp_link_rate; }; =20 /** diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_= panel.c index 15b7f6c7146e1176a80b5c9d25896b1c8ede3aed..ad5d55bf009dbe60e61ca4f4c10= 8116333129203 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -16,9 +16,6 @@ =20 #define DP_INTF_CONFIG_DATABUS_WIDEN BIT(4) =20 -#define DP_MAX_NUM_DP_LANES 4 -#define DP_LINK_RATE_HBR2 540000 /* kbytes */ - struct msm_dp_panel_private { struct device *dev; struct drm_device *drm_dev; @@ -91,6 +88,7 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel *ms= m_dp_panel) int rc, max_lttpr_lanes, max_lttpr_rate; struct msm_dp_panel_private *panel; struct msm_dp_link_info *link_info; + struct msm_dp_link *link; u8 *dpcd, major, minor; =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); @@ -105,16 +103,20 @@ static int msm_dp_panel_read_dpcd(struct msm_dp_panel= *msm_dp_panel) major =3D (link_info->revision >> 4) & 0x0f; minor =3D link_info->revision & 0x0f; =20 + link =3D panel->link; + drm_dbg_dp(panel->drm_dev, "max_lanes=3D%d max_link_rate=3D%d\n", + link->max_dp_lanes, link->max_dp_link_rate); + link_info->rate =3D drm_dp_max_link_rate(dpcd); link_info->num_lanes =3D drm_dp_max_lane_count(dpcd); =20 /* Limit data lanes from data-lanes of endpoint property of dtsi */ - if (link_info->num_lanes > msm_dp_panel->max_dp_lanes) - link_info->num_lanes =3D msm_dp_panel->max_dp_lanes; + if (link_info->num_lanes > link->max_dp_lanes) + link_info->num_lanes =3D link->max_dp_lanes; =20 /* Limit link rate from link-frequencies of endpoint property of dtsi */ - if (link_info->rate > msm_dp_panel->max_dp_link_rate) - link_info->rate =3D msm_dp_panel->max_dp_link_rate; + if (link_info->rate > link->max_dp_link_rate) + link_info->rate =3D link->max_dp_link_rate; =20 /* Limit data lanes from LTTPR capabilities, if any */ max_lttpr_lanes =3D drm_dp_lttpr_max_lane_count(panel->link->lttpr_common= _caps); @@ -173,9 +175,6 @@ int msm_dp_panel_read_sink_caps(struct msm_dp_panel *ms= m_dp_panel, =20 panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); =20 - drm_dbg_dp(panel->drm_dev, "max_lanes=3D%d max_link_rate=3D%d\n", - msm_dp_panel->max_dp_lanes, msm_dp_panel->max_dp_link_rate); - rc =3D msm_dp_panel_read_dpcd(msm_dp_panel); if (rc) { DRM_ERROR("read dpcd failed %d\n", rc); @@ -648,60 +647,6 @@ int msm_dp_panel_init_panel_info(struct msm_dp_panel *= msm_dp_panel) return 0; } =20 -static u32 msm_dp_panel_link_frequencies(struct device_node *of_node) -{ - struct device_node *endpoint; - u64 frequency =3D 0; - int cnt; - - endpoint =3D of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ - if (!endpoint) - return 0; - - cnt =3D of_property_count_u64_elems(endpoint, "link-frequencies"); - - if (cnt > 0) - of_property_read_u64_index(endpoint, "link-frequencies", - cnt - 1, &frequency); - of_node_put(endpoint); - - do_div(frequency, - 10 * /* from symbol rate to link rate */ - 1000); /* kbytes */ - - return frequency; -} - -static int msm_dp_panel_parse_dt(struct msm_dp_panel *msm_dp_panel) -{ - struct msm_dp_panel_private *panel; - struct device_node *of_node; - int cnt; - - panel =3D container_of(msm_dp_panel, struct msm_dp_panel_private, msm_dp_= panel); - of_node =3D panel->dev->of_node; - - /* - * data-lanes is the property of msm_dp_out endpoint - */ - cnt =3D drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LA= NES); - if (cnt < 0) { - /* legacy code, data-lanes is the property of mdss_dp node */ - cnt =3D drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); - } - - if (cnt > 0) - msm_dp_panel->max_dp_lanes =3D cnt; - else - msm_dp_panel->max_dp_lanes =3D DP_MAX_NUM_DP_LANES; /* 4 lanes */ - - msm_dp_panel->max_dp_link_rate =3D msm_dp_panel_link_frequencies(of_node); - if (!msm_dp_panel->max_dp_link_rate) - msm_dp_panel->max_dp_link_rate =3D DP_LINK_RATE_HBR2; - - return 0; -} - struct msm_dp_panel *msm_dp_panel_get(struct device *dev, struct drm_dp_au= x *aux, struct msm_dp_link *link, void __iomem *link_base, @@ -709,7 +654,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *de= v, struct drm_dp_aux *aux { struct msm_dp_panel_private *panel; struct msm_dp_panel *msm_dp_panel; - int ret; =20 if (!dev || !aux || !link) { DRM_ERROR("invalid input\n"); @@ -729,10 +673,6 @@ struct msm_dp_panel *msm_dp_panel_get(struct device *d= ev, struct drm_dp_aux *aux msm_dp_panel =3D &panel->msm_dp_panel; msm_dp_panel->max_bw_code =3D DP_LINK_BW_8_1; =20 - ret =3D msm_dp_panel_parse_dt(msm_dp_panel); - if (ret) - return ERR_PTR(ret); - return msm_dp_panel; } =20 diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_= panel.h index d2cf401506dcbaf553192d5e18c87207337664ab..921a296852d4df65f817665d3e1= 344f2f7c9ece7 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -41,9 +41,6 @@ struct msm_dp_panel { bool vsc_sdp_supported; u32 hw_revision; =20 - u32 max_dp_lanes; - u32 max_dp_link_rate; - u32 max_bw_code; }; =20 --=20 2.34.1