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[190.12.77.24]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-324e257809esm2606455a91.24.2025.08.20.07.59.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 07:59:25 -0700 (PDT) From: Denzeel Oliva Date: Wed, 20 Aug 2025 09:57:24 -0500 Subject: [PATCH v2 3/3] clk: samsung: exynos990: Fix PLL mux regs, add DPU/CMUREF Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250820-2-v2-3-bd45e196d4c4@gmail.com> References: <20250820-2-v2-0-bd45e196d4c4@gmail.com> In-Reply-To: <20250820-2-v2-0-bd45e196d4c4@gmail.com> To: Krzysztof Kozlowski , Sylwester Nawrocki , Chanwoo Choi , Alim Akhtar , Michael Turquette , Stephen Boyd , Rob Herring , Conor Dooley Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Denzeel Oliva X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755701949; l=12553; i=wachiturroxd150@gmail.com; s=20250819; h=from:subject:message-id; bh=75MeJfcBxXyVJ1uuKMywshUfE9yrQQgMLZJ8oZLt3BQ=; b=GNLgLwHOzJTaYMyZSnDeXi/AthRaY4rYpuwrZ13rHY/uV4RT8GklCA1jTQwa6h7hAHSSYfw9s k5x6RpduTeED2h+ug+FpeOK+DDOpypArXEKVHz12F/rO9tvrTh5rD8x X-Developer-Key: i=wachiturroxd150@gmail.com; a=ed25519; pk=qNvcL0Ehm3chrW9jFA2JaPVgubN5mHH//uriMxR/DlI= Switch PLL muxes to PLL_CON0 to correct parent selection and clock rates. Add DPU_BUS and CMUREF mux/div and their register hooks and parents. Signed-off-by: Denzeel Oliva --- drivers/clk/samsung/clk-exynos990.c | 121 ++++++++++++++++++++++++++++++++= ++++++++++++++---------------------------- 1 file changed, 75 insertions(+), 46 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos990.c b/drivers/clk/samsung/clk-= exynos990.c index a55991ebb77bcb2988071fc156dbe5c9b100215f..c5f1dbaf45b6a718994c1dfa9f2= 04cfccd74cb16 100644 --- a/drivers/clk/samsung/clk-exynos990.c +++ b/drivers/clk/samsung/clk-exynos990.c @@ -45,6 +45,7 @@ #define PLL_CON3_PLL_SHARED3 0x024c #define PLL_CON0_PLL_SHARED4 0x0280 #define PLL_CON3_PLL_SHARED4 0x028c +#define CLK_CON_MUX_CLKCMU_DPU_BUS 0x1000 #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1004 #define CLK_CON_MUX_MUX_CLKCMU_AUD_CPU 0x1008 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x100c @@ -103,6 +104,8 @@ #define CLK_CON_MUX_MUX_CLKCMU_SSP_BUS 0x10e0 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10e4 #define CLK_CON_MUX_MUX_CLKCMU_VRA_BUS 0x10e8 +#define CLK_CON_MUX_MUX_CLK_CMU_CMUREF 0x10f0 +#define CLK_CON_MUX_MUX_CMU_CMUREF 0x10f4 #define CLK_CON_DIV_CLKCMU_APM_BUS 0x1800 #define CLK_CON_DIV_CLKCMU_AUD_CPU 0x1804 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1808 @@ -162,6 +165,7 @@ #define CLK_CON_DIV_CLKCMU_VRA_BUS 0x18e0 #define CLK_CON_DIV_DIV_CLKCMU_DPU 0x18e8 #define CLK_CON_DIV_DIV_CLKCMU_DPU_ALT 0x18ec +#define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18f0 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x18f4 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x18f8 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x18fc @@ -239,13 +243,21 @@ static const unsigned long top_clk_regs[] __initconst= =3D { PLL_LOCKTIME_PLL_SHARED2, PLL_LOCKTIME_PLL_SHARED3, PLL_LOCKTIME_PLL_SHARED4, + PLL_CON0_PLL_G3D, PLL_CON3_PLL_G3D, + PLL_CON0_PLL_MMC, PLL_CON3_PLL_MMC, + PLL_CON0_PLL_SHARED0, PLL_CON3_PLL_SHARED0, + PLL_CON0_PLL_SHARED1, PLL_CON3_PLL_SHARED1, + PLL_CON0_PLL_SHARED2, PLL_CON3_PLL_SHARED2, + PLL_CON0_PLL_SHARED3, PLL_CON3_PLL_SHARED3, + PLL_CON0_PLL_SHARED4, PLL_CON3_PLL_SHARED4, + CLK_CON_MUX_CLKCMU_DPU_BUS, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, CLK_CON_MUX_MUX_CLKCMU_AUD_CPU, CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, @@ -304,6 +316,8 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_MUX_MUX_CLKCMU_SSP_BUS, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, + CLK_CON_MUX_MUX_CLK_CMU_CMUREF, + CLK_CON_MUX_MUX_CMU_CMUREF, CLK_CON_DIV_CLKCMU_APM_BUS, CLK_CON_DIV_CLKCMU_AUD_CPU, CLK_CON_DIV_CLKCMU_BUS0_BUS, @@ -363,6 +377,7 @@ static const unsigned long top_clk_regs[] __initconst = =3D { CLK_CON_DIV_CLKCMU_VRA_BUS, CLK_CON_DIV_DIV_CLKCMU_DPU, CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, CLK_CON_DIV_PLL_SHARED0_DIV2, CLK_CON_DIV_PLL_SHARED0_DIV3, CLK_CON_DIV_PLL_SHARED0_DIV4, @@ -434,6 +449,10 @@ static const unsigned long top_clk_regs[] __initconst = =3D { }; =20 static const struct samsung_pll_clock top_pll_clks[] __initconst =3D { + PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", + PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), + PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", + PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), PLL(pll_0717x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, NULL), PLL(pll_0717x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk", @@ -444,20 +463,18 @@ static const struct samsung_pll_clock top_pll_clks[] = __initconst =3D { PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3, NULL), PLL(pll_0717x, CLK_FOUT_SHARED4_PLL, "fout_shared4_pll", "oscclk", PLL_LOCKTIME_PLL_SHARED4, PLL_CON3_PLL_SHARED4, NULL), - PLL(pll_0732x, CLK_FOUT_MMC_PLL, "fout_mmc_pll", "oscclk", - PLL_LOCKTIME_PLL_MMC, PLL_CON3_PLL_MMC, NULL), - PLL(pll_0718x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", - PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), }; =20 /* Parent clock list for CMU_TOP muxes */ +PNAME(mout_pll_g3d_p) =3D { "oscclk", "fout_g3d_pll" }; +PNAME(mout_pll_mmc_p) =3D { "oscclk", "fout_mmc_pll" }; PNAME(mout_pll_shared0_p) =3D { "oscclk", "fout_shared0_pll" }; PNAME(mout_pll_shared1_p) =3D { "oscclk", "fout_shared1_pll" }; PNAME(mout_pll_shared2_p) =3D { "oscclk", "fout_shared2_pll" }; PNAME(mout_pll_shared3_p) =3D { "oscclk", "fout_shared3_pll" }; PNAME(mout_pll_shared4_p) =3D { "oscclk", "fout_shared4_pll" }; -PNAME(mout_pll_mmc_p) =3D { "oscclk", "fout_mmc_pll" }; -PNAME(mout_pll_g3d_p) =3D { "oscclk", "fout_g3d_pll" }; +PNAME(mout_cmu_dpu_bus_p) =3D { "dout_cmu_dpu", + "dout_cmu_dpu_alt" }; PNAME(mout_cmu_apm_bus_p) =3D { "dout_cmu_shared0_div2", "dout_cmu_shared2_div2" }; PNAME(mout_cmu_aud_cpu_p) =3D { "dout_cmu_shared0_div2", @@ -507,7 +524,7 @@ PNAME(mout_cmu_cpucl0_switch_p) =3D { "fout_shared4_pl= l", "dout_cmu_shared0_div2", "fout_shared2_pll", "dout_cmu_shared0_div4" }; -PNAME(mout_cmu_cpucl1_switch_p) =3D { "fout_shared4_pll", +PNAME(mout_cmu_cpucl1_switch_p) =3D { "fout_shared4_pll", "dout_cmu_shared0_div2", "fout_shared2_pll", "dout_cmu_shared0_div4" }; @@ -577,7 +594,7 @@ PNAME(mout_cmu_hsi1_bus_p) =3D { "dout_cmu_shared0_div= 3", "dout_cmu_shared4_div3", "dout_cmu_shared2_div2", "fout_mmc_pll", "oscclk", "oscclk" }; -PNAME(mout_cmu_hsi1_mmc_card_p) =3D { "oscclk", "fout_shared2_pll", +PNAME(mout_cmu_hsi1_mmc_card_p) =3D { "oscclk", "fout_shared2_pll", "fout_mmc_pll", "dout_cmu_shared0_div4" }; PNAME(mout_cmu_hsi1_pcie_p) =3D { "oscclk", "fout_shared2_pll" }; @@ -672,6 +689,12 @@ PNAME(mout_cmu_vra_bus_p) =3D { "dout_cmu_shared0_div= 3", "dout_cmu_shared4_div2", "dout_cmu_shared0_div4", "dout_cmu_shared4_div3" }; +PNAME(mout_cmu_cmuref_p) =3D { "oscclk", + "dout_cmu_clk_cmuref" }; +PNAME(mout_cmu_clk_cmuref_p) =3D { "dout_cmu_shared0_div4", + "dout_cmu_shared1_div4", + "dout_cmu_shared2_div2", + "oscclk" }; =20 /* * Register name to clock name mangling strategy used in this file @@ -688,20 +711,22 @@ PNAME(mout_cmu_vra_bus_p) =3D { "dout_cmu_shared0_di= v3", */ =20 static const struct samsung_mux_clock top_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p, + PLL_CON0_PLL_MMC, 4, 1), + MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p, + PLL_CON0_PLL_G3D, 4, 1), MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p, - PLL_CON3_PLL_SHARED0, 4, 1), + PLL_CON0_PLL_SHARED0, 4, 1), MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p, - PLL_CON3_PLL_SHARED1, 4, 1), + PLL_CON0_PLL_SHARED1, 4, 1), MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p, - PLL_CON3_PLL_SHARED2, 4, 1), + PLL_CON0_PLL_SHARED2, 4, 1), MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p, - PLL_CON3_PLL_SHARED3, 4, 1), + PLL_CON0_PLL_SHARED3, 4, 1), MUX(CLK_MOUT_PLL_SHARED4, "mout_pll_shared4", mout_pll_shared4_p, PLL_CON0_PLL_SHARED4, 4, 1), - MUX(CLK_MOUT_PLL_MMC, "mout_pll_mmc", mout_pll_mmc_p, - PLL_CON0_PLL_MMC, 4, 1), - MUX(CLK_MOUT_PLL_G3D, "mout_pll_g3d", mout_pll_g3d_p, - PLL_CON0_PLL_G3D, 4, 1), + MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", + mout_cmu_dpu_bus_p, CLK_CON_MUX_CLKCMU_DPU_BUS, 0, 1), MUX(CLK_MOUT_CMU_APM_BUS, "mout_cmu_apm_bus", mout_cmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1), MUX(CLK_MOUT_CMU_AUD_CPU, "mout_cmu_aud_cpu", @@ -830,37 +855,13 @@ static const struct samsung_mux_clock top_mux_clks[] = __initconst =3D { mout_cmu_tnr_bus_p, CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3), MUX(CLK_MOUT_CMU_VRA_BUS, "mout_cmu_vra_bus", mout_cmu_vra_bus_p, CLK_CON_MUX_MUX_CLKCMU_VRA_BUS, 0, 2), + MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", + mout_cmu_cmuref_p, CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1), + MUX(CLK_MOUT_CMU_CLK_CMUREF, "mout_cmu_clk_cmuref", + mout_cmu_clk_cmuref_p, CLK_CON_MUX_MUX_CLK_CMU_CMUREF, 0, 2), }; =20 static const struct samsung_div_clock top_div_clks[] __initconst =3D { - /* SHARED0 region*/ - DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0= ", - CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0= ", - CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0= _div2", - CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), - - /* SHARED1 region*/ - DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1= ", - CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1= ", - CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1= _div2", - CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), - - /* SHARED2 region */ - DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2= ", - CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), - - /* SHARED4 region*/ - DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4= ", - CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1), - DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4= ", - CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2), - DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "mout_pll_shared4= ", - CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), - DIV(CLK_DOUT_CMU_APM_BUS, "dout_cmu_apm_bus", "gout_cmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 2), DIV(CLK_DOUT_CMU_AUD_CPU, "dout_cmu_aud_cpu", "gout_cmu_aud_cpu", @@ -887,7 +888,7 @@ static const struct samsung_div_clock top_div_clks[] __= initconst =3D { CLK_CON_DIV_CLKCMU_CMU_BOOST, 0, 2), DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus", CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4), - DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_debug", + DIV(CLK_DOUT_CMU_CPUCL0_DBG_BUS, "dout_cmu_cpucl0_dbg_bus", "gout_cmu_cpucl0_dbg_bus", CLK_CON_DIV_CLKCMU_CPUCL0_DBG_BUS, 0, 4), DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch", @@ -972,8 +973,36 @@ static const struct samsung_div_clock top_div_clks[] _= _initconst =3D { CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4), DIV(CLK_DOUT_CMU_VRA_BUS, "dout_cmu_vra_bus", "gout_cmu_vra_bus", CLK_CON_DIV_CLKCMU_VRA_BUS, 0, 4), - DIV(CLK_DOUT_CMU_DPU, "dout_cmu_clkcmu_dpu", "gout_cmu_dpu", + DIV(CLK_DOUT_CMU_DPU, "dout_cmu_dpu", "gout_cmu_dpu", CLK_CON_DIV_DIV_CLKCMU_DPU, 0, 3), + DIV(CLK_DOUT_CMU_DPU_ALT, "dout_cmu_dpu_alt", "gout_cmu_dpu_bus", + CLK_CON_DIV_DIV_CLKCMU_DPU_ALT, 0, 4), + DIV(CLK_DOUT_CMU_CLK_CMUREF, "dout_cmu_clk_cmuref", "mout_cmu_clk_cmuref", + CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2), + /* SHARED0 region*/ + DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2", "mout_pll_shared0= ", + CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3", "mout_pll_shared0= ", + CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4", "dout_cmu_shared0= _div2", + CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1), + /* SHARED1 region*/ + DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2", "mout_pll_shared1= ", + CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3", "mout_pll_shared1= ", + CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4", "dout_cmu_shared1= _div2", + CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1), + /* SHARED2 region */ + DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2", "mout_pll_shared2= ", + CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1), + /* SHARED4 region*/ + DIV(CLK_DOUT_CMU_SHARED4_DIV2, "dout_cmu_shared4_div2", "mout_pll_shared4= ", + CLK_CON_DIV_PLL_SHARED4_DIV2, 0, 1), + DIV(CLK_DOUT_CMU_SHARED4_DIV3, "dout_cmu_shared4_div3", "mout_pll_shared4= ", + CLK_CON_DIV_PLL_SHARED4_DIV3, 0, 2), + DIV(CLK_DOUT_CMU_SHARED4_DIV4, "dout_cmu_shared4_div4", "dout_cmu_shared4= _div2", + CLK_CON_DIV_PLL_SHARED4_DIV4, 0, 1), }; =20 static const struct samsung_fixed_factor_clock cmu_top_ffactor[] __initcon= st =3D { --=20 2.49.0