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Tue, 19 Aug 2025 14:52:28 -0700 (PDT) Date: Tue, 19 Aug 2025 21:51:33 +0000 In-Reply-To: <20250819215156.2494305-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250819215156.2494305-1-smostafa@google.com> X-Mailer: git-send-email 2.51.0.rc1.167.g924127e9c0-goog Message-ID: <20250819215156.2494305-6-smostafa@google.com> Subject: [PATCH v4 05/28] iommu/io-pgtable-arm: Factor kernel specific code out From: Mostafa Saleh To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, jgg@ziepe.ca, mark.rutland@arm.com, praan@google.com, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Some of the currently used APIs are only part of the kernel and not available in the hypervisor, factor those out of the common file: - alloc/free memory - CMOs - virt/phys conversions Which is implemented by the kernel in io-pgtable-arm-kernel.c and similarly for the hypervisor later in this series. va/pa conversion kept as macros. Signed-off-by: Mostafa Saleh --- drivers/iommu/io-pgtable-arm-kernel.c | 89 ++++++++++++++++++++++++ drivers/iommu/io-pgtable-arm.c | 99 +++------------------------ drivers/iommu/io-pgtable-arm.h | 14 ++++ 3 files changed, 113 insertions(+), 89 deletions(-) diff --git a/drivers/iommu/io-pgtable-arm-kernel.c b/drivers/iommu/io-pgtab= le-arm-kernel.c index f3b869310964..d3056487b0f6 100644 --- a/drivers/iommu/io-pgtable-arm-kernel.c +++ b/drivers/iommu/io-pgtable-arm-kernel.c @@ -9,10 +9,99 @@ #define pr_fmt(fmt) "arm-lpae io-pgtable: " fmt =20 #include +#include #include #include =20 #include "io-pgtable-arm.h" +#include "iommu-pages.h" + +static dma_addr_t __arm_lpae_dma_addr(void *pages) +{ + return (dma_addr_t)virt_to_phys(pages); +} + +void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, + struct io_pgtable_cfg *cfg, + void *cookie) +{ + struct device *dev =3D cfg->iommu_dev; + size_t alloc_size; + dma_addr_t dma; + void *pages; + + /* + * For very small starting-level translation tables the HW requires a + * minimum alignment of at least 64 to cover all cases. + */ + alloc_size =3D max(size, 64); + if (cfg->alloc) + pages =3D cfg->alloc(cookie, alloc_size, gfp); + else + pages =3D iommu_alloc_pages_node_sz(dev_to_node(dev), gfp, + alloc_size); + + if (!pages) + return NULL; + + if (!cfg->coherent_walk) { + dma =3D dma_map_single(dev, pages, size, DMA_TO_DEVICE); + if (dma_mapping_error(dev, dma)) + goto out_free; + /* + * We depend on the IOMMU being able to work with any physical + * address directly, so if the DMA layer suggests otherwise by + * translating or truncating them, that bodes very badly... + */ + if (dma !=3D virt_to_phys(pages)) + goto out_unmap; + } + + return pages; + +out_unmap: + dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"= ); + dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); + +out_free: + if (cfg->free) + cfg->free(cookie, pages, size); + else + iommu_free_pages(pages); + + return NULL; +} + +void __arm_lpae_free_pages(void *pages, size_t size, + struct io_pgtable_cfg *cfg, + void *cookie) +{ + if (!cfg->coherent_walk) + dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages), + size, DMA_TO_DEVICE); + + if (cfg->free) + cfg->free(cookie, pages, size); + else + iommu_free_pages(pages); +} + +void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries, + struct io_pgtable_cfg *cfg) +{ + dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep), + sizeof(*ptep) * num_entries, DMA_TO_DEVICE); +} + +void *__arm_lpae_alloc_data(size_t size, gfp_t gfp) +{ + return kmalloc(size, gfp); +} + +void __arm_lpae_free_data(void *p) +{ + return kfree(p); +} =20 #ifdef CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST =20 diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c index 791a2c4ecb83..2ca09081c3b0 100644 --- a/drivers/iommu/io-pgtable-arm.c +++ b/drivers/iommu/io-pgtable-arm.c @@ -12,12 +12,10 @@ #include #include #include -#include =20 #include =20 #include "io-pgtable-arm.h" -#include "iommu-pages.h" =20 /* * Calculate the index at level l used to map virtual address a using the @@ -118,7 +116,7 @@ #define ARM_MALI_LPAE_MEMATTR_WRITE_ALLOC 0x8DULL =20 /* IOPTE accessors */ -#define iopte_deref(pte,d) __va(iopte_to_paddr(pte, d)) +#define iopte_deref(pte,d) __arm_lpae_phys_to_virt(iopte_to_paddr(pte, d)) =20 #define iopte_type(pte) \ (((pte) >> ARM_LPAE_PTE_TYPE_SHIFT) & ARM_LPAE_PTE_TYPE_MASK) @@ -208,83 +206,6 @@ static inline bool arm_lpae_concat_mandatory(struct io= _pgtable_cfg *cfg, (data->start_level =3D=3D 1) && (oas =3D=3D 40); } =20 -static dma_addr_t __arm_lpae_dma_addr(void *pages) -{ - return (dma_addr_t)virt_to_phys(pages); -} - -static void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, - struct io_pgtable_cfg *cfg, - void *cookie) -{ - struct device *dev =3D cfg->iommu_dev; - size_t alloc_size; - dma_addr_t dma; - void *pages; - - /* - * For very small starting-level translation tables the HW requires a - * minimum alignment of at least 64 to cover all cases. - */ - alloc_size =3D max(size, 64); - if (cfg->alloc) - pages =3D cfg->alloc(cookie, alloc_size, gfp); - else - pages =3D iommu_alloc_pages_node_sz(dev_to_node(dev), gfp, - alloc_size); - - if (!pages) - return NULL; - - if (!cfg->coherent_walk) { - dma =3D dma_map_single(dev, pages, size, DMA_TO_DEVICE); - if (dma_mapping_error(dev, dma)) - goto out_free; - /* - * We depend on the IOMMU being able to work with any physical - * address directly, so if the DMA layer suggests otherwise by - * translating or truncating them, that bodes very badly... - */ - if (dma !=3D virt_to_phys(pages)) - goto out_unmap; - } - - return pages; - -out_unmap: - dev_err(dev, "Cannot accommodate DMA translation for IOMMU page tables\n"= ); - dma_unmap_single(dev, dma, size, DMA_TO_DEVICE); - -out_free: - if (cfg->free) - cfg->free(cookie, pages, size); - else - iommu_free_pages(pages); - - return NULL; -} - -static void __arm_lpae_free_pages(void *pages, size_t size, - struct io_pgtable_cfg *cfg, - void *cookie) -{ - if (!cfg->coherent_walk) - dma_unmap_single(cfg->iommu_dev, __arm_lpae_dma_addr(pages), - size, DMA_TO_DEVICE); - - if (cfg->free) - cfg->free(cookie, pages, size); - else - iommu_free_pages(pages); -} - -static void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries, - struct io_pgtable_cfg *cfg) -{ - dma_sync_single_for_device(cfg->iommu_dev, __arm_lpae_dma_addr(ptep), - sizeof(*ptep) * num_entries, DMA_TO_DEVICE); -} - static void __arm_lpae_clear_pte(arm_lpae_iopte *ptep, struct io_pgtable_c= fg *cfg, int num_entries) { for (int i =3D 0; i < num_entries; i++) @@ -360,7 +281,7 @@ static arm_lpae_iopte arm_lpae_install_table(arm_lpae_i= opte *table, arm_lpae_iopte old, new; struct io_pgtable_cfg *cfg =3D &data->iop.cfg; =20 - new =3D paddr_to_iopte(__pa(table), data) | ARM_LPAE_PTE_TYPE_TABLE; + new =3D paddr_to_iopte(__arm_lpae_virt_to_phys(table), data) | ARM_LPAE_P= TE_TYPE_TABLE; if (cfg->quirks & IO_PGTABLE_QUIRK_ARM_NS) new |=3D ARM_LPAE_PTE_NSTABLE; =20 @@ -581,7 +502,7 @@ static void arm_lpae_free_pgtable(struct io_pgtable *io= p) struct arm_lpae_io_pgtable *data =3D io_pgtable_to_data(iop); =20 __arm_lpae_free_pgtable(data, data->start_level, data->pgd); - kfree(data); + __arm_lpae_free_data(data); } =20 static size_t __arm_lpae_unmap(struct arm_lpae_io_pgtable *data, @@ -895,7 +816,7 @@ arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg) if (cfg->oas > ARM_LPAE_MAX_ADDR_BITS) return NULL; =20 - data =3D kmalloc(sizeof(*data), GFP_KERNEL); + data =3D __arm_lpae_alloc_data(sizeof(*data), GFP_KERNEL); if (!data) return NULL; =20 @@ -1018,11 +939,11 @@ arm_64_lpae_alloc_pgtable_s1(struct io_pgtable_cfg *= cfg, void *cookie) wmb(); =20 /* TTBR */ - cfg->arm_lpae_s1_cfg.ttbr =3D virt_to_phys(data->pgd); + cfg->arm_lpae_s1_cfg.ttbr =3D __arm_lpae_virt_to_phys(data->pgd); return &data->iop; =20 out_free_data: - kfree(data); + __arm_lpae_free_data(data); return NULL; } =20 @@ -1114,11 +1035,11 @@ arm_64_lpae_alloc_pgtable_s2(struct io_pgtable_cfg = *cfg, void *cookie) wmb(); =20 /* VTTBR */ - cfg->arm_lpae_s2_cfg.vttbr =3D virt_to_phys(data->pgd); + cfg->arm_lpae_s2_cfg.vttbr =3D __arm_lpae_virt_to_phys(data->pgd); return &data->iop; =20 out_free_data: - kfree(data); + __arm_lpae_free_data(data); return NULL; } =20 @@ -1188,7 +1109,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cf= g, void *cookie) /* Ensure the empty pgd is visible before TRANSTAB can be written */ wmb(); =20 - cfg->arm_mali_lpae_cfg.transtab =3D virt_to_phys(data->pgd) | + cfg->arm_mali_lpae_cfg.transtab =3D __arm_lpae_virt_to_phys(data->pgd) | ARM_MALI_LPAE_TTBR_READ_INNER | ARM_MALI_LPAE_TTBR_ADRMODE_TABLE; if (cfg->coherent_walk) @@ -1197,7 +1118,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cf= g, void *cookie) return &data->iop; =20 out_free_data: - kfree(data); + __arm_lpae_free_data(data); return NULL; } =20 diff --git a/drivers/iommu/io-pgtable-arm.h b/drivers/iommu/io-pgtable-arm.h index a06a23543cff..7d9f0b759275 100644 --- a/drivers/iommu/io-pgtable-arm.h +++ b/drivers/iommu/io-pgtable-arm.h @@ -68,4 +68,18 @@ struct arm_lpae_io_pgtable { =20 typedef u64 arm_lpae_iopte; =20 +void __arm_lpae_sync_pte(arm_lpae_iopte *ptep, int num_entries, + struct io_pgtable_cfg *cfg); +void __arm_lpae_free_pages(void *pages, size_t size, + struct io_pgtable_cfg *cfg, + void *cookie); +void *__arm_lpae_alloc_pages(size_t size, gfp_t gfp, + struct io_pgtable_cfg *cfg, + void *cookie); +void *__arm_lpae_alloc_data(size_t size, gfp_t gfp); +void __arm_lpae_free_data(void *p); +#ifndef __KVM_NVHE_HYPERVISOR__ +#define __arm_lpae_virt_to_phys __pa +#define __arm_lpae_phys_to_virt __va +#endif /* !__KVM_NVHE_HYPERVISOR__ */ #endif /* IO_PGTABLE_ARM_H_ */ --=20 2.51.0.rc1.167.g924127e9c0-goog