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Tue, 19 Aug 2025 14:52:47 -0700 (PDT) Date: Tue, 19 Aug 2025 21:51:53 +0000 In-Reply-To: <20250819215156.2494305-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250819215156.2494305-1-smostafa@google.com> X-Mailer: git-send-email 2.51.0.rc1.167.g924127e9c0-goog Message-ID: <20250819215156.2494305-26-smostafa@google.com> Subject: [PATCH v4 25/28] iommu/arm-smmu-v3-kvm: Emulate GBPA From: Mostafa Saleh To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, jgg@ziepe.ca, mark.rutland@arm.com, praan@google.com, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The last bit of emulation is GBPA. it must be always set to ABORT, as when the SMMU is disabled it=E2=80=99s not allowed for the host to bypass the SMMU. That =E2=80=98s is done by setting the GBPA to ABORT at init time, when the= host: - Writes, we ignore the write and save the value without the UPDATE bit. - Reads, return the saved value. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 21 ++++++++++++++++--- .../iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h | 2 ++ 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index 0f890a7d8db3..db9d9caaca2c 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -100,6 +100,13 @@ static int smmu_unshare_pages(phys_addr_t addr, size_t= size) return 0; } =20 +static int smmu_abort_gbpa(struct hyp_arm_smmu_v3_device *smmu) +{ + writel_relaxed(GBPA_UPDATE | GBPA_ABORT, smmu->base + ARM_SMMU_GBPA); + /* Wait till UPDATE is cleared. */ + return smmu_wait(readl_relaxed(smmu->base + ARM_SMMU_GBPA) =3D=3D GBPA_AB= ORT); +} + static bool smmu_cmdq_full(struct arm_smmu_queue *cmdq) { struct arm_smmu_ll_queue *llq =3D &cmdq->llq; @@ -416,6 +423,10 @@ static int smmu_init_device(struct hyp_arm_smmu_v3_dev= ice *smmu) if (ret) goto out_ret; =20 + ret =3D smmu_abort_gbpa(smmu); + if (ret) + goto out_ret; + return 0; =20 out_ret: @@ -663,10 +674,14 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_d= evice *smmu, smmu->host_ste_cfg =3D val; } goto out_ret; - /* Passthrough the register access for bisectiblity, handled later */ case ARM_SMMU_GBPA: - mask =3D read_write; - break; + if (is_write) + smmu->gbpa =3D val & ~GBPA_UPDATE; + else + regs->regs[rd] =3D smmu->gbpa; + + WARN_ON(len !=3D sizeof(u32)); + goto out_ret; case ARM_SMMU_CR0: if (is_write) { bool last_cmdq_en =3D is_cmdq_enabled(smmu); diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h index cf85e5efdd9e..aab585dd9fd8 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm_smmu_v3.h @@ -31,6 +31,7 @@ * @host_ste_cfg Host stream table config * @host_ste_base Host stream table base * @strtab_cfg Stream table as seen by HW + * @gbpa Last value of GBPA from the host */ struct hyp_arm_smmu_v3_device { phys_addr_t mmio_addr; @@ -54,6 +55,7 @@ struct hyp_arm_smmu_v3_device { u64 host_ste_cfg; u64 host_ste_base; struct arm_smmu_strtab_cfg strtab_cfg; + u32 gbpa; }; =20 extern size_t kvm_nvhe_sym(kvm_hyp_arm_smmu_v3_count); --=20 2.51.0.rc1.167.g924127e9c0-goog