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Tue, 19 Aug 2025 14:52:45 -0700 (PDT) Date: Tue, 19 Aug 2025 21:51:50 +0000 In-Reply-To: <20250819215156.2494305-1-smostafa@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250819215156.2494305-1-smostafa@google.com> X-Mailer: git-send-email 2.51.0.rc1.167.g924127e9c0-goog Message-ID: <20250819215156.2494305-23-smostafa@google.com> Subject: [PATCH v4 22/28] iommu/arm-smmu-v3-kvm: Emulate CMDQ for host From: Mostafa Saleh To: linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Cc: maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, robin.murphy@arm.com, jean-philippe@linaro.org, qperret@google.com, tabba@google.com, jgg@ziepe.ca, mark.rutland@arm.com, praan@google.com, Mostafa Saleh Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Don=E2=80=99t allow access to the command queue from the host: - ARM_SMMU_CMDQ_BASE: Only allowed to be written when CMDQ is disabled, we use it to keep track of the host command queue base. Reads return the saved value. - ARM_SMMU_CMDQ_PROD: Writes trigger command queue emulation which sanitises and filters the whole range. Reads returns the host copy. - ARM_SMMU_CMDQ_CONS: Writes move the sw copy of the cons, but the host can= =E2=80=99t skip commands once submitted. Reads return the emulated value and the err= or bits in the actual cons. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 108 +++++++++++++++++- 1 file changed, 105 insertions(+), 3 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iom= mu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index 554229e466f3..10c6461bbf12 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -325,6 +325,88 @@ static bool is_cmdq_enabled(struct hyp_arm_smmu_v3_dev= ice *smmu) return FIELD_GET(CR0_CMDQEN, smmu->cr0); } =20 +static bool smmu_filter_command(struct hyp_arm_smmu_v3_device *smmu, u64 *= command) +{ + u64 type =3D FIELD_GET(CMDQ_0_OP, command[0]); + + switch (type) { + case CMDQ_OP_CFGI_STE: + /* TBD: SHADOW_STE*/ + break; + case CMDQ_OP_CFGI_ALL: + { + /* + * Linux doesn't use range STE invalidation, and only use this + * for CFGI_ALL, which is done on reset and not on an new STE + * being used. + * Although, this is not architectural we rely on the current Linux + * implementation. + */ + WARN_ON((FIELD_GET(CMDQ_CFGI_1_RANGE, command[1]) !=3D 31)); + break; + } + case CMDQ_OP_TLBI_NH_ASID: + case CMDQ_OP_TLBI_NH_VA: + case 0x13: /* CMD_TLBI_NH_VAA: Not used by Linux */ + { + /* Only allow VMID =3D 0*/ + if (FIELD_GET(CMDQ_TLBI_0_VMID, command[0]) =3D=3D 0) + break; + break; + } + case 0x10: /* CMD_TLBI_NH_ALL: Not used by Linux */ + case CMDQ_OP_TLBI_EL2_ALL: + case CMDQ_OP_TLBI_EL2_VA: + case CMDQ_OP_TLBI_EL2_ASID: + case CMDQ_OP_TLBI_S12_VMALL: + case 0x23: /* CMD_TLBI_EL2_VAA: Not used by Linux */ + /* Malicous host */ + return WARN_ON(true); + case CMDQ_OP_CMD_SYNC: + if (FIELD_GET(CMDQ_SYNC_0_CS, command[0]) =3D=3D CMDQ_SYNC_0_CS_IRQ) { + /* Allow it, but let the host timeout, as this should never happen. */ + command[0] &=3D ~CMDQ_SYNC_0_CS; + command[0] |=3D FIELD_PREP(CMDQ_SYNC_0_CS, CMDQ_SYNC_0_CS_SEV); + command[1] &=3D ~CMDQ_SYNC_1_MSIADDR_MASK; + } + break; + } + + return false; +} + +static void smmu_emulate_cmdq_insert(struct hyp_arm_smmu_v3_device *smmu) +{ + u64 *host_cmdq =3D hyp_phys_to_virt(smmu->cmdq_host.q_base & Q_BASE_ADDR_= MASK); + int idx; + u64 cmd[CMDQ_ENT_DWORDS]; + bool skip; + + if (!is_cmdq_enabled(smmu)) + return; + + while (!queue_empty(&smmu->cmdq_host.llq)) { + /* Wait for the command queue to have some space. */ + WARN_ON(smmu_wait_event(smmu, !smmu_cmdq_full(&smmu->cmdq))); + + idx =3D Q_IDX(&smmu->cmdq_host.llq, smmu->cmdq_host.llq.cons); + /* Avoid TOCTOU */ + memcpy(cmd, &host_cmdq[idx * CMDQ_ENT_DWORDS], CMDQ_ENT_DWORDS << 3); + skip =3D smmu_filter_command(smmu, cmd); + if (!skip) + smmu_add_cmd_raw(smmu, cmd); + queue_inc_cons(&smmu->cmdq_host.llq); + } + + /* + * Wait till consumed, this can be improved a bit by returning to the host + * while flagging the current offset in the command queue with the host, + * this would be maintained from the hyp entering command or when the + * host issuing another read to cons. + */ + WARN_ON(smmu_wait_event(smmu, smmu_cmdq_empty(&smmu->cmdq))); +} + static void smmu_emulate_cmdq_enable(struct hyp_arm_smmu_v3_device *smmu) { size_t cmdq_size; @@ -360,17 +442,37 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_d= evice *smmu, mask =3D read_only & ~(IDR0_S2P | IDR0_VMID16 | IDR0_MSI | IDR0_HYP); WARN_ON(len !=3D sizeof(u32)); break; - /* Passthrough the register access for bisectiblity, handled later */ case ARM_SMMU_CMDQ_BASE: =20 /* Not allowed by the architecture */ WARN_ON(is_cmdq_enabled(smmu)); if (is_write) smmu->cmdq_host.q_base =3D val; - mask =3D read_write; - break; + else + regs->regs[rd] =3D smmu->cmdq_host.q_base; + goto out_ret; case ARM_SMMU_CMDQ_PROD: + if (is_write) { + smmu->cmdq_host.llq.prod =3D val; + smmu_emulate_cmdq_insert(smmu); + } else { + regs->regs[rd] =3D smmu->cmdq_host.llq.prod; + } + goto out_ret; case ARM_SMMU_CMDQ_CONS: + if (is_write) { + /* Not allowed by the architecture */ + WARN_ON(is_cmdq_enabled(smmu)); + smmu->cmdq_host.llq.cons =3D val; + } else { + /* Propagate errors back to the host.*/ + u32 cons =3D readl_relaxed(smmu->base + ARM_SMMU_CMDQ_CONS); + u32 err =3D CMDQ_CONS_ERR & cons; + + regs->regs[rd] =3D smmu->cmdq_host.llq.cons | err; + } + goto out_ret; + /* Passthrough the register access for bisectiblity, handled later */ case ARM_SMMU_STRTAB_BASE: case ARM_SMMU_STRTAB_BASE_CFG: case ARM_SMMU_GBPA: --=20 2.51.0.rc1.167.g924127e9c0-goog