From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 29D7D2C11D8 for ; Tue, 19 Aug 2025 16:55:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622528; cv=none; b=QxHbVBb8EDudbh6tBc2/GbAY4A4FsBJKmVFYSebSuw4SI+NoSQx1QyQcWyg88m3JRspSOzKVM3EQQeLRfWjyZpeLjgKuPUR9M5uTfulzQCtQ3pVSzcapkdujdBEbHBqIA35fvbK+Xv/xJA0kwshxMEoGUnNem5/GiihsJ35XuRc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622528; c=relaxed/simple; bh=/AflHXTFVOH16SOW2V+0meYRbIqCERPZj2WZC7Vo8H8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=euC0vbMgXhjTF0+cCmDA7UYRSGu9GQ7aRxQv4/jOB2oNOuTYL+5tbaouVyVDW8Qo4YK2wYprV05G4g7fxaIDkyK4WoFw8fYptt4IlWTeQtwF4nNYm4S3HvEC1z3PzeTf38Zi53oKGJ3nH7jIHedYOJVq29mE3ccgwbSpTkhmAJg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=cXRdml3m; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="cXRdml3m" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90awC008391 for ; Tue, 19 Aug 2025 16:55:26 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=pXVD6URM8iG tLYeJuDTnL3ZNXgs+m9zGa8usL8h3epI=; b=cXRdml3mbCs2lHhaZJZzWvieN84 kUS2hI4UYd+t00HXPun/dT3q0wvOzh+VJZq5Sz4z68oWu6692DeoM6iHmvklrRvk 3kO1lhs7ViWgxA7Tc/8A06DVdWK60h+dHVuL4iS4EVmLd7n7orD79MAnQhiq9Vea x8mZItrgJUcJNZo06G0lcAL8rfbWcfRdZwY4kzuyGkAAMKVwMehXWpGYZMQfcL8c 983esjVm9Rovo/ji4enBKuQseE70aQHRkDTwV2jGVxXPg3QtFeb8XiXiB3pkMrAK rdh2t6kW9+ewtdHjPflu6mtlmLLbkbFSZzRHSfsZ+kIrBBC/BRbbPRx342A== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48jk99s96b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:26 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2445806eab4so58151955ad.1 for ; Tue, 19 Aug 2025 09:55:26 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622525; x=1756227325; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pXVD6URM8iGtLYeJuDTnL3ZNXgs+m9zGa8usL8h3epI=; b=acUr5YWrl1vCEe44chJNYlRp8bMlvE6xUsqUi0/5Fm0/2q76Lj2p1jhPGj+DG5ajY9 4XycXrZ4abdXHXLCHRWbtNL1glzYerVZ3FEKioWXhHjwEverl2pZWuq72RSEfmLj2QXm FikFtjP9kDsEAh5cWi1inV46mQiijF1IchprHmyqvVSAIvytY41JxSEdROPKlib+1LVO fE+IHxc/jFl2iZxGTzoPRV+V6RVUqBuT5mtIIC4EmSHCU0ZKagh4SvQx3tFmF8LDvePN 4yY+Toi1/PBk3K+3grmigavZa6DNooIsRlCJGQu8nO+7sXBWHVYvtG1L1bUVHMGXzAoq FCEw== X-Forwarded-Encrypted: i=1; AJvYcCWP8vI7KVcoh47XK7Feed1YwsPUV9th+Mpq6U+dgzRtLQQ30No9Bl1wD1cVxftFFWmMe0m0Fu/09hMIZ5Q=@vger.kernel.org X-Gm-Message-State: AOJu0YzGAfBeNKvcdO8KdbIB86Bf64iXuHHEC5uutPIhK1m7ZijBl52t pUtga/e+gWH2M1d9inBtHyJQ3yoFbstdBl1Zd31qsh2t8Xtqnh0fIdMPA0CaF1yvY8wrt5RuMqK sCxUuLD6TF5Gk3AfnF1T8Tuv40sWKEmS68gMbFMaFRGv2wykZRBclx4FQIqXQOoNllEM= X-Gm-Gg: ASbGncsII9VmI29B8Wo9DGhW5yvty+ttYCA+zuVY1aFUU5qedXrs+AMC3hCSPqmzIWX G3PSMfJ7Ap0Rb9ebkoFsnpf1hArvX/OON57q3aE7dgrQpS87QyVt9o7HprX0kJrsb6V+I8xWHHP CBBYrag2Zq4mULIO5GaEayI4Fta6siLromqyXz7Jzm+Zpu62btleqbcE0q2Q/N3+51P7IYvN53H SuAeKADrFhmvRi+l+HnZ63AhJXEDKNjcYgy3sgm3m2hvilFk3TtESgZOz99Q4CnjVxNroDUvnwO vY3qocNlPnRG+vQ59ANhfbDXSk1MAMatxlJzd3AGI4gi+ZKBGdcUposakEma7E8izyQ= X-Received: by 2002:a17:903:198e:b0:240:967a:fec3 with SMTP id d9443c01a7336-245e0484a9amr41225435ad.29.1755622525327; Tue, 19 Aug 2025 09:55:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH+lNYppywDdTFFexVwLhEK+BRHzaI9WsoHo0SSwLAnNl6dT+h/o5sN/sHh1+Wi0XAryEA6Lg== X-Received: by 2002:a17:903:198e:b0:240:967a:fec3 with SMTP id d9443c01a7336-245e0484a9amr41225205ad.29.1755622524920; Tue, 19 Aug 2025 09:55:24 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:24 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 01/11] firmware: qcom_scm: Introduce PAS context initialization helper Date: Tue, 19 Aug 2025 22:24:36 +0530 Message-ID: <20250819165447.4149674-2-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 1Gnd9fsFXMDee2ItiqGS1b2-UwJtgYxO X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDA0NSBTYWx0ZWRfX/Mqbkl6uQ+qy BO/XzZXPF3ri6VMi3Y/HLeTqbCIR0y4+i68sZ/MgzyBp5SuhosCYUJQCWGhOcUSxie+uv+ethkz +z0mNox87Lnoqg2G+OXg6ptM1YFz5e6neMAhtzLK2jQNrlYxwMkDE1HV57MHBgFmoldhc0h4Njs Wj5GQsyxs0Oq+jDaZPP+IyoiZs2dD0R4n2Yy5C7iSvn/6JV4UzzrgZoTR2GHaNryKDghSL0DGLC w7ZscT4WdH/8OgwqcI9cRd6bNU6gJXdZ/8OY7QHZZKbOGT9Mvk3vRilfeD6JmaiJ2PvKpui+kCd 8Ai4yWcpVPQH1JES/JD5v16n8d85KM07CdylzTaF1ItMNb5oUsCUqmCXL8FwGcQReU9HPUlfYEU acMEbAJp X-Authority-Analysis: v=2.4 cv=IIMCChvG c=1 sm=1 tr=0 ts=68a4ac7e cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=3w5JJ7MTCOpz5QvkTaEA:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: 1Gnd9fsFXMDee2ItiqGS1b2-UwJtgYxO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160045 Content-Type: text/plain; charset="utf-8" Currently, remoteproc and non-remoteproc subsystems use different variants of the MDT loader helper API, primarily due to the handling of the metadata context. Remoteproc subsystems retain this context until authentication and reset, while non-remoteproc subsystems (e.g., video, graphics) do not require it. Unify the metadata loading process for both remoteproc and non-remoteproc subsystems by introducing a dedicated PAS context initialization function. By introducing qcom_scm_pas_ctx_init(), we can standardize the API usage across subsystems and reduce the number of parameters passed to MDT loader functions, improving code clarity and maintainability. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 26 ++++++++++++++++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 11 +++++++++++ 2 files changed, 37 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 96d5cf40a74c..33187d4f4aef 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -558,6 +558,32 @@ static void qcom_scm_set_download_mode(u32 dload_mode) dev_err(__scm->dev, "failed to set download mode: %d\n", ret); } =20 +void *qcom_scm_pas_ctx_init(struct device *dev, u32 peripheral, phys_addr_= t mem_phys, + size_t mem_size, bool save_mdt_ctx) +{ + struct qcom_scm_pas_ctx *ctx; + + ctx =3D devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return NULL; + + ctx->dev =3D dev; + ctx->peripheral =3D peripheral; + ctx->mem_phys =3D mem_phys; + ctx->mem_size =3D mem_size; + ctx->save_mdt_ctx =3D save_mdt_ctx; + ctx->metadata =3D NULL; + + if (save_mdt_ctx) { + ctx->metadata =3D devm_kzalloc(dev, sizeof(*ctx->metadata), GFP_KERNEL); + if (!ctx->metadata) + return NULL; + } + + return ctx; +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_ctx_init); + /** * qcom_scm_pas_init_image() - Initialize peripheral authentication service * state machine for a given peripheral, using the diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index a55ca771286b..b7eb206561a9 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -72,6 +72,17 @@ struct qcom_scm_pas_metadata { ssize_t size; }; =20 +struct qcom_scm_pas_ctx { + struct device *dev; + u32 peripheral; + phys_addr_t mem_phys; + size_t mem_size; + struct qcom_scm_pas_metadata *metadata; + bool save_mdt_ctx; +}; + +void *qcom_scm_pas_ctx_init(struct device *dev, u32 peripheral, phys_addr_= t mem_phys, + size_t mem_size, bool save_mdt_ctx); int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t s= ize, struct qcom_scm_pas_metadata *ctx); void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5EA942D2494 for ; Tue, 19 Aug 2025 16:55:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622533; cv=none; b=qoOBt7RlbZ6VNxkRST4UblvkfVOkpW6bWqEifgb5EukUTjrP9ULdbLhxRxXr6MI0hvd1/uGjQJ/arEoYOr31JzVw/l9T5OBmiDWbSklEIaOIGcCSGCiKJMv7gvKV/+TSMnhBMdIWf7jUFMMrRxZy9om/zuOd4dVARCXQ+YkrQJc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622533; c=relaxed/simple; bh=EAfpvsi6NVKNbNSOJcBUSNNG3c+NvpwLp5OAM0V/v7k=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Z2C86g9yOpVHk+FQeN4Rm7SJnr7mC1vu5FVJWqyIUtByABV7W0QsGoHFjFb18X76ze0pOaoqCCIzBoJDexqOIx9i6W+IXamofRd+VPa4qBGUy7/dh/G5GE1ueV3yE9OsNJT1bjsKFPYLFchQ4HBWCv4io8Ib0oTJcfigM3ZeeYM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=OuPXFo4U; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="OuPXFo4U" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90a0w029813 for ; Tue, 19 Aug 2025 16:55:30 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=op1TPLxV5Hz dPsGSHZreogRDWYSb1zFoqqgwkfe5+WM=; b=OuPXFo4Uo6QHDTGKLvzb+mL/fGO bUpCnsxthb1nNEBHICaXsn4RI1LRicmjjJZOVM5nfIwnvkE8X2dR6pt8cBSOG6Lw jPak5rpI8stp2gOyiotVZP3ua4e5f+LXUn9RXyG+GjZeF8oxxR/2UDCm4Ezmiof6 7EDPovFg0AtyN6gsxLoujMGTfQ370gt1ySLeN3ekFRPrw1Xs53EFFN2E273m6mN5 7OWIzTwh4ub31E0bqrZIYw6jH2HmXVvolhoeoA1DclLWvns4jsrHCt+Jvovy+/Mn cJH8c2GkF5rrNztwIO4Mzo7+rFxkJaDnHpNcxEXNfpaBnOe57ubDCOKvBcw== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48jk5mh68w-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:30 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-2445805d386so60174535ad.1 for ; Tue, 19 Aug 2025 09:55:30 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622530; x=1756227330; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=op1TPLxV5HzdPsGSHZreogRDWYSb1zFoqqgwkfe5+WM=; b=egV61T8vdXjiQlRylqekXld/2+nsNcyijmP6M/KhJ/4MZJr2cV6omW8loNq9Nu6vfR avww6NXT9Q4dWxWE22KAE2Ly05HN4W7nAmb/shrz3dqIIvZ+D+xMDw6o/nNe+ZVyyPVR QgC0FoXalcXYQcKCKzAJyjDeNmAx09KGaaq/qiBf0/5+uURmbEgFO5dTXs6Ht+IXs5P3 50DK77SE5lEub4GRypwaWyzS8Uv4ER2ofkO2AA7/AlPwt4iAc59tzrEDGGQF0KxcNgju RKehzokWmmGcwc+BffnxZobyawBbGoPaxk0eXsfpHszur3uBU4IMXGqqjZIFSyD6lAaD 3PhA== X-Forwarded-Encrypted: i=1; AJvYcCV7ndRCgslaQ9NyP5qYmRXyc+nA2hcHumcaraePqEkAkLT5IiHyq/7jwoZr7E5Naniv0bSRPg+OJG18eiA=@vger.kernel.org X-Gm-Message-State: AOJu0Yy8WFQDMJmQIhyE08r8gkRKKiurkDvcCNb7aPOMIno3+8GboJvA j6Txcmwvyex+u+0mBMGyMJiHHEnJGqlOk1lOo8PQvCh81J0gegBAC4rtkBDKXYYa7WuXhxOzpg1 T7uDm9+mci+oAJp/YX8paY9zr4e+0qbsCWa/pfqiNKYTwPjbpfKy1XGtpkNzae1BXfC4= X-Gm-Gg: ASbGnctZ6MHORePh9QsIdjqg8GuQ6bjYWw+BwXNFoQfcCDz61tfZci/fiNLVSYIKwZN pCyYKZpiCm96s6Zeq8MPFkW7ZXiNPukOVaH+yrHNpFmC0hlXPe6qsGUPMSH59qhFaLkWifiDEee v0LLOCT/4OTnWTZga77vgCCGNGqxZr90Dbqsgk2hAw8ZFQ4JdMH+eZWFTLVeVZq9+/KCmjZ6vre XaL++92Vba7iciOfrPFLOYPfpmiueMmy5tw79EZZiy2xXnIr2CF5/9Xjgm30dGiApJii+AA+APl j3CfH/2dor2ggKTJZTeIGLgCuAr49eLTXdLjjbJWUZwF0bpzrOjKZDohagOYyW39dWw= X-Received: by 2002:a17:902:d50f:b0:240:25f3:211b with SMTP id d9443c01a7336-245e04c7029mr45132885ad.51.1755622529546; Tue, 19 Aug 2025 09:55:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHP1fg8V0NTh0vtb8DSC8js3l86SxwQ5bNSKBheoxb2Ujnh1eu6S8wkXVP3Kxz1CvGgBsp/lQ== X-Received: by 2002:a17:902:d50f:b0:240:25f3:211b with SMTP id d9443c01a7336-245e04c7029mr45132485ad.51.1755622529018; Tue, 19 Aug 2025 09:55:29 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:28 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 02/11] soc: qcom: mdtloader: Add context aware qcom_mdt_pas_load() helper Date: Tue, 19 Aug 2025 22:24:37 +0530 Message-ID: <20250819165447.4149674-3-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Sdn3duRu c=1 sm=1 tr=0 ts=68a4ac82 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=DsNTrw4wbpnc9IaBGIUA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-ORIG-GUID: vBjjASCHMi5PiAn8UvGND3Xg40PfJd5W X-Proofpoint-GUID: vBjjASCHMi5PiAn8UvGND3Xg40PfJd5W X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDA0MiBTYWx0ZWRfXwzMf7kRsCxZV Yt4gu3zY8s3UIHisO6AkvUJ3DSqYHnx6NQ71WWmF8pRMpMQK8AYyrE+C7ZEO/OgF1edI2UaJCYZ qO8rq1Iojuf1/GOVtgdvEsyj/mszRpx0iE2vD394w3w1dYN0FQKfdzbUrtVB2sxhZ+EQtVnzy+o OEQgUl+meMpBgad7tcoXrxcGVYTjBbbuNWo+aDtPZWt0C9kikmuAMX9RoCvtPVKQMrM1OpoF65i FGyvCOS1RAlD+/1OD9mjB0fYXiuAQAZMpjVTQ5/7ZDZVJoIZQnjiSPFrKA7ZW4IGzpg+su2laWL bplB+Xz8qHj+0LvbHTe8ZRw17u8D5dISNDv22HX+LJFa8R0mZyPtdx2FJq5otvkZjWVMoKDIzOK zZfwdaur X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160042 Content-Type: text/plain; charset="utf-8" Currently, remoteproc and non-remoteproc subsystems use different variants of the MDT loader helper API, primarily due to the handling of the metadata context. Remoteproc subsystems retain this context until authentication and reset, while non-remoteproc subsystems (e.g., video, graphics) do not require it. Add context aware qcom_mdt_pas_load() function which uses context returned from qcom_scm_pas_ctx_init() and use it till subsystems is out of set. This will also help in unifying the API used by remoteproc and non-remoteproc subsystems drivers. Signed-off-by: Mukesh Ojha --- If this approach is preferred, will convert all subsystem drivers to use the same set of API's using context and completely get away with qcom_mdt_load() -Mukesh drivers/remoteproc/qcom_q6v5_pas.c | 53 ++++++++++++++--------------- drivers/soc/qcom/mdt_loader.c | 26 ++++++++++---- include/linux/soc/qcom/mdt_loader.h | 22 ++++++------ 3 files changed, 56 insertions(+), 45 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index 55a7da801183..e376c0338576 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -115,8 +115,8 @@ struct qcom_pas { struct qcom_rproc_ssr ssr_subdev; struct qcom_sysmon *sysmon; =20 - struct qcom_scm_pas_metadata pas_metadata; - struct qcom_scm_pas_metadata dtb_pas_metadata; + struct qcom_scm_pas_ctx *pas_ctx; + struct qcom_scm_pas_ctx *dtb_pas_ctx; }; =20 static void qcom_pas_segment_dump(struct rproc *rproc, @@ -209,9 +209,9 @@ static int qcom_pas_unprepare(struct rproc *rproc) * auth_and_reset() was successful, but in other cases clean it up * here. */ - qcom_scm_pas_metadata_release(&pas->pas_metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx->metadata); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx->metadata); =20 return 0; } @@ -235,15 +235,8 @@ static int qcom_pas_load(struct rproc *rproc, const st= ruct firmware *fw) return ret; } =20 - ret =3D qcom_mdt_pas_init(pas->dev, pas->dtb_firmware, pas->dtb_firmware= _name, - pas->dtb_pas_id, pas->dtb_mem_phys, - &pas->dtb_pas_metadata); - if (ret) - goto release_dtb_firmware; - - ret =3D qcom_mdt_load_no_init(pas->dev, pas->dtb_firmware, pas->dtb_firm= ware_name, - pas->dtb_mem_region, pas->dtb_mem_phys, - pas->dtb_mem_size, &pas->dtb_mem_reloc); + ret =3D qcom_mdt_pas_load(pas->dtb_pas_ctx, pas->dtb_firmware, pas->dtb_= firmware_name, + pas->dtb_mem_region, &pas->dtb_mem_reloc); if (ret) goto release_dtb_metadata; } @@ -251,9 +244,7 @@ static int qcom_pas_load(struct rproc *rproc, const str= uct firmware *fw) return 0; =20 release_dtb_metadata: - qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata); - -release_dtb_firmware: + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx->metadata); release_firmware(pas->dtb_firmware); =20 return ret; @@ -301,14 +292,8 @@ static int qcom_pas_start(struct rproc *rproc) } } =20 - ret =3D qcom_mdt_pas_init(pas->dev, pas->firmware, rproc->firmware, pas->= pas_id, - pas->mem_phys, &pas->pas_metadata); - if (ret) - goto disable_px_supply; - - ret =3D qcom_mdt_load_no_init(pas->dev, pas->firmware, rproc->firmware, - pas->mem_region, pas->mem_phys, pas->mem_size, - &pas->mem_reloc); + ret =3D qcom_mdt_pas_load(pas->pas_ctx, pas->firmware, rproc->firmware, + pas->mem_region, &pas->dtb_mem_reloc); if (ret) goto release_pas_metadata; =20 @@ -328,9 +313,9 @@ static int qcom_pas_start(struct rproc *rproc) goto release_pas_metadata; } =20 - qcom_scm_pas_metadata_release(&pas->pas_metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx->metadata); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx->metadata); =20 /* firmware is used to pass reference from qcom_pas_start(), drop it now = */ pas->firmware =3D NULL; @@ -338,9 +323,9 @@ static int qcom_pas_start(struct rproc *rproc) return 0; =20 release_pas_metadata: - qcom_scm_pas_metadata_release(&pas->pas_metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx->metadata); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(&pas->dtb_pas_metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx->metadata); disable_px_supply: if (pas->px_supply) regulator_disable(pas->px_supply); @@ -774,6 +759,18 @@ static int qcom_pas_probe(struct platform_device *pdev) } =20 qcom_add_ssr_subdev(rproc, &pas->ssr_subdev, desc->ssr_name); + + pas->pas_ctx =3D qcom_scm_pas_ctx_init(pas->dev, pas->pas_id, pas->mem_ph= ys, + pas->mem_size, true); + if (!pas->pas_ctx) + goto remove_ssr_sysmon; + + pas->dtb_pas_ctx =3D qcom_scm_pas_ctx_init(pas->dev, pas->dtb_pas_id, + pas->dtb_mem_phys, pas->dtb_mem_size, + true); + if (!pas->dtb_pas_ctx) + goto remove_ssr_sysmon; + ret =3D rproc_add(rproc); if (ret) goto remove_ssr_sysmon; diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index a5c80d4fcc36..509ff85d9bf6 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -228,7 +228,7 @@ void *qcom_mdt_read_metadata(const struct firmware *fw,= size_t *data_len, EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata); =20 /** - * qcom_mdt_pas_init() - initialize PAS region for firmware loading + * __qcom_mdt_pas_init() - initialize PAS region for firmware loading * @dev: device handle to associate resources with * @fw: firmware object for the mdt file * @fw_name: name of the firmware, for construction of segment file names @@ -238,9 +238,9 @@ EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata); * * Returns 0 on success, negative errno otherwise. */ -int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, - const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_metadata *ctx) +static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *= fw, + const char *fw_name, int pas_id, phys_addr_t mem_phys, + struct qcom_scm_pas_metadata *ctx) { const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; @@ -302,7 +302,6 @@ int qcom_mdt_pas_init(struct device *dev, const struct = firmware *fw, out: return ret; } -EXPORT_SYMBOL_GPL(qcom_mdt_pas_init); =20 static bool qcom_mdt_bins_are_split(const struct firmware *fw) { @@ -456,7 +455,7 @@ int qcom_mdt_load(struct device *dev, const struct firm= ware *fw, { int ret; =20 - ret =3D qcom_mdt_pas_init(dev, fw, firmware, pas_id, mem_phys, NULL); + ret =3D __qcom_mdt_pas_init(dev, fw, firmware, pas_id, mem_phys, NULL); if (ret) return ret; =20 @@ -486,5 +485,20 @@ int qcom_mdt_load_no_init(struct device *dev, const st= ruct firmware *fw, } EXPORT_SYMBOL_GPL(qcom_mdt_load_no_init); =20 +int qcom_mdt_pas_load(struct qcom_scm_pas_ctx *ctx, const struct firmware = *fw, + const char *firmware, void *mem_region, phys_addr_t *reloc_base) +{ + int ret; + + ret =3D __qcom_mdt_pas_init(ctx->dev, fw, firmware, ctx->peripheral, + ctx->mem_phys, ctx->metadata); + if (ret) + return ret; + + return __qcom_mdt_load(ctx->dev, fw, firmware, mem_region, ctx->mem_phys, + ctx->mem_size, reloc_base); +} +EXPORT_SYMBOL_GPL(qcom_mdt_pas_load); + MODULE_DESCRIPTION("Firmware parser for Qualcomm MDT format"); MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/m= dt_loader.h index 8ea8230579a2..450fa0be2af0 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -10,19 +10,20 @@ =20 struct device; struct firmware; -struct qcom_scm_pas_metadata; +struct qcom_scm_pas_ctx; =20 #if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) =20 ssize_t qcom_mdt_get_size(const struct firmware *fw); -int qcom_mdt_pas_init(struct device *dev, const struct firmware *fw, - const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_metadata *pas_metadata_ctx); + int qcom_mdt_load(struct device *dev, const struct firmware *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, size_t mem_size, phys_addr_t *reloc_base); =20 +int qcom_mdt_pas_load(struct qcom_scm_pas_ctx *ctx, const struct firmware = *fw, + const char *firmware, void *mem_region, phys_addr_t *reloc_base); + int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, const char *fw_name, void *mem_region, phys_addr_t mem_phys, size_t mem_size, @@ -37,13 +38,6 @@ static inline ssize_t qcom_mdt_get_size(const struct fir= mware *fw) return -ENODEV; } =20 -static inline int qcom_mdt_pas_init(struct device *dev, const struct firmw= are *fw, - const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_metadata *pas_metadata_ctx) -{ - return -ENODEV; -} - static inline int qcom_mdt_load(struct device *dev, const struct firmware = *fw, const char *fw_name, int pas_id, void *mem_region, phys_addr_t mem_phys, @@ -52,6 +46,12 @@ static inline int qcom_mdt_load(struct device *dev, cons= t struct firmware *fw, return -ENODEV; } =20 +int qcom_mdt_pas_load(struct qcom_scm_pas_ctx *ctx, const struct firmware = *fw, + const char *firmware, void *mem_region, phys_addr_t *reloc_base) +{ + return -ENODEV; +} + static inline int qcom_mdt_load_no_init(struct device *dev, const struct firmware *fw, const char *fw_name, void *mem_region, --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E4732C2343 for ; Tue, 19 Aug 2025 16:55:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622537; cv=none; b=Iyb+4l4iGceshpWHR75qYAgoG9TpfS+eHJ7R10vDqbJQXb+ogOBS6ASf9tts62nJY26ojUjML5GYDUpIwV5dVEZCZF+8bKyc8dSDYm5mHerl9+HtS9Wjt+0HEn9s7ZaKITQCqfeLg9SH1Z/3gLLzxk8WH7ZGRjwmqZwdVdUgqdI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622537; c=relaxed/simple; bh=dmKcJUIVtmS50+BiHAPFjw7rQIQKfyNOMW7Ww7Lx9J0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=R8VGe/0z9yvIYLMNl/bx5PiPVHsLvPOA6+QxxNrfJUTGpFFnRpcaLm/wzDTi6taAffQZ6YQawiJVIE1659NVDporNDCy/dE24MpyhQvYlGAlDnxt+ChLyp/GVM/heAkJAvn+Iombe77dFJtBaGkAIP4ZD5zFCuJNzqQ9R1i/A90= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=JxSHwHqc; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="JxSHwHqc" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90ap6021803 for ; Tue, 19 Aug 2025 16:55:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= enByMTUq/WcM7Q767ZJgoe5KkDWAYvRUW6oJgwm1WBA=; b=JxSHwHqc4+2efYoc EHIXuGESYOwsOo/Jl1TlifpGh9z1Iw3sIS7onknR4rF3tPh4LaSQeAUBRXQ4WPh/ XFavQP3SpykoCKEeFEUCPWOUgq9qF9SH+5LfPr1nyHLvTS1D3IwnTJXnDByz+N3w FChJ8grlQqtxNtkf1/tgmBZr0oBk3ISsFt2sKAUpErPnfKlOiInwkFAhe23dTPn2 JV+vqzJ1H9umJ6ACs5TKMzF+gU0oHL3vNS4CYxaUPbe09OdpntwJTR5C0rKy4y6N oyLaXmNRzTcSpy0yaWCaw0E+lxRWkanym4dnQm+ePdtSHxwt3dj/6H4+RfvQ6A2T R1YNww== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48m71cm20s-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:34 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-24458345f5dso59672095ad.3 for ; Tue, 19 Aug 2025 09:55:34 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622534; x=1756227334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=enByMTUq/WcM7Q767ZJgoe5KkDWAYvRUW6oJgwm1WBA=; b=YeH3VjGj4PgjsOD82ialsX+q+CXQ+tHTxZqHl9GeX+NRsZEgoE3n8mrOmlrVFohujO cLhDfa1Sz5X0v5hJxDNhH2qFhZE+OHc4aKoIO3OzzaCiU66VxWxaJG7s1ig4OLkIzuDb 3uQREbJCa/6F5YaQ7TzDAWEKLQcsQfXOZFrS3Qd/wOj9WZiM5NGHQuq3wLB3F6rg/Pes Zf96rw3/FTsKG5dnKjMO6jjiDTYRoHgDCyRJQVtmJrjdYeO9153TgtGA4fsMPrrvbez/ e2xhN0VfSiXAZVtR0qnHKQD3qPxd87O/AGAk3LVhoDgnV/y9Qc5EVPRZ1UYKku6D7JPj wFEA== X-Forwarded-Encrypted: i=1; AJvYcCUaxinEFtsv2Ja8lJjQnN2sP9Ha/KPh/LF+x0Y/whaShqz/lCShQTJhA/Cr4BFrQLyAJwLq0O2NDBg3+V4=@vger.kernel.org X-Gm-Message-State: AOJu0YwUPeItnsdbQdXJH1+W2yQgfXpwsvcAHUnk48Mv0f/+QTjeBtnJ sPxYIej/i6o7VxIhI8ILSjs+0klmB0hBVnO5VvgEv6XcsbIgYG3DOZQffRyIyBRMP47p37/mXyF u0J2RkBgzqiKEtmbEGm0//NymU2EX/0m28lRSO0Me4Fw36qALODfIgdJEQcFWGYrADhQ= X-Gm-Gg: ASbGncuVY0Hswcb0C7/+YUUuJD9kl+FXMQeQzHAxoX0D+1rfpagj+Po28CLWHSBDjDI USnRxxKxVr+ZEbCbzMTxdh1EXW3gK4KYigQwoAqLqHao1U/5XzDFgHew/LxByZezil9H8SG3hwZ 7eHNs3VKH9Znv1iFiT86/Vk+Dud63uxk+W057P15FjGY/4v/6YQB00DMLAmQet0JUuGlrgv29hO EKwTlSOnpcOmA5UFRjBIY8J0lzAxEDZKD8CpLwaxk/m53+GCxbj/i+/1MyhdynRvMREWMQZZrCL Vp10vwpz6m/QoK0Y8MPqxGFwn4TZX593pSgeAsVREZiBtkZfP0a9UZnjOyk8yigbeCM= X-Received: by 2002:a17:902:eccf:b0:240:934f:27ac with SMTP id d9443c01a7336-245e049d32fmr46953795ad.33.1755622533636; Tue, 19 Aug 2025 09:55:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHv9NKBhQZBU4DFDEN9fRVd2gjaOBSnMVLUa3PreZFrVrpWEGvKQExqyoAlrfKKQpanX5N+Og== X-Received: by 2002:a17:902:eccf:b0:240:934f:27ac with SMTP id d9443c01a7336-245e049d32fmr46953325ad.33.1755622533162; Tue, 19 Aug 2025 09:55:33 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:32 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 03/11] firmware: qcom_scm: Add a prep version of auth_and_reset function Date: Tue, 19 Aug 2025 22:24:38 +0530 Message-ID: <20250819165447.4149674-4-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: uJpd3bwospKt-_gFBMyuB5DZEwXVjWCy X-Proofpoint-GUID: uJpd3bwospKt-_gFBMyuB5DZEwXVjWCy X-Authority-Analysis: v=2.4 cv=IvQecK/g c=1 sm=1 tr=0 ts=68a4ac86 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=xhUff6YxzY9YBBblk4UA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE4MDE0NyBTYWx0ZWRfX/mwZAjLE8HVd m36x6wODrnSgBVRAyT90xOHDWeCnpEzq3OUXGFCSH0jzt7qQHEjEILPrBYS7rPUOqa6aiqNko4w iI/jFjzQMeXL71J/PIF4n8INn9pi9YaEVlEEp7tiqx0obD/Ctc60cm+hEXAcx/VTURJ13qxw5uY V1ee64mcunzhlfrMdP0kaPXOoGwKfOR5jcmDA2UrE93Xtt6Sq5pmoCsC7MIspel75imo/oET/mr aVT705LRiXFmwl8MyULY+0FU9zrrb42BOh4EBG0M5BWsjrhsFRBK772FYaD9Kr1dbS2Vc3nf8rm LSfURfSGMis5gR6a88LBKlWDkb8FX/REyONV6J3ARbChn8L6PR2Ijs2p34Na0QLM2gPQ6X/mzpp ovSAfhQ0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 phishscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508180147 Qualcomm SoCs running with QHEE (Qualcomm Hypervisor Execution Environment=E2=80=94a library present in the Gunyah hypervisor) utilize the Peripheral Authentication Service (PAS) from TrustZone (TZ) firmware to securely authenticate and reset remote processors via a sequence of SMC calls such as qcom_scm_pas_init_image(), qcom_scm_pas_mem_setup(), and qcom_scm_pas_auth_and_reset(). For memory passed to Qualcomm TrustZone, it must either be part of a pool registered with TZ or be directly registered via SHMbridge SMC calls. When QHEE is present, PAS SMC calls from Linux running at EL1 are trapped by QHEE (running at EL2), which then creates or retrieves memory from the SHMbridge for both metadata and remoteproc carveout memory before passing them to TZ. However, when the SoC runs with a non-QHEE-based hypervisor, Linux must create the SHM bridge for both metadata (before it is passed to TZ in qcom_scm_pas_init_image()) and for remoteproc memory (before the call is made to TZ in qcom_scm_pas_auth_and_reset()). For auth_and_reset() call, first it need to register remoteproc carveout memory with TZ via SHMbridge SMC call and then it can trigger auth_and_reset SMC call and once the call returns, remoteproc carveout memory can be deregisterd with TZ. Add qcom_scm_pas_prepare_and_auth_reset() function which does prepare the SHMbridge over carveout memory and call auth_and_reset SMC call. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 46 ++++++++++++++++++++++++++ include/linux/firmware/qcom/qcom_scm.h | 2 ++ 2 files changed, 48 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 33187d4f4aef..9a5b34f5bacb 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -759,6 +759,52 @@ int qcom_scm_pas_auth_and_reset(u32 peripheral) } EXPORT_SYMBOL_GPL(qcom_scm_pas_auth_and_reset); =20 +/** + * qcom_scm_pas_prepare_and_auth_reset() - Prepare, authenticate, and rese= t the remote processor + * + * @ctx: Context saved during call to qcom_scm_pas_ctx_init() + * + * This function performs the necessary steps to prepare a PAS subsystem, + * authenticate it using the provided metadata, and initiate a reset seque= nce. + * + * It is typically used when Linux is in control setting up the IOMMU hard= ware + * for remote subsystem during secure firmware loading processes. The prep= aration + * step sets up shmbridge over the firmware memory before TrustZone access= the + * firmware memory region for authentication. The authentication step veri= fies + * the integrity and authenticity of the firmware or configuration using s= ecure + * metadata. Finally, the reset step ensures the subsystem starts in a cle= an and + * sane state. + * + * Return: 0 on success, negative errno on failure. + */ +int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_ctx *ctx) +{ + u64 handle; + int ret; + + if (!ctx->has_iommu) + return qcom_scm_pas_auth_and_reset(ctx->peripheral); + + /* + * When Linux running at EL1, Gunyah(EL2) traps auth_and_reset call and c= reates + * shmbridge on subsystem memory region before it passes the call to Trus= tZone + * to authenticate it while when Linux runs at EL2, it needs to create sh= mbridge + * before this call goes to TrustZone. + */ + ret =3D qcom_tzmem_shm_bridge_create(ctx->mem_phys, ctx->mem_size, &handl= e); + if (ret) { + dev_err(__scm->dev, "Failed to create shmbridge ret=3D%d %u\n", + ret, ctx->peripheral); + return ret; + } + + ret =3D qcom_scm_pas_auth_and_reset(ctx->peripheral); + qcom_tzmem_shm_bridge_delete(handle); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_prepare_and_auth_reset); + /** * qcom_scm_pas_shutdown() - Shut down the remote processor * @peripheral: peripheral id diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index b7eb206561a9..a31006fe49a9 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -79,6 +79,7 @@ struct qcom_scm_pas_ctx { size_t mem_size; struct qcom_scm_pas_metadata *metadata; bool save_mdt_ctx; + bool has_iommu; }; =20 void *qcom_scm_pas_ctx_init(struct device *dev, u32 peripheral, phys_addr_= t mem_phys, @@ -87,6 +88,7 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *m= etadata, size_t size, struct qcom_scm_pas_metadata *ctx); void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t s= ize); +int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_ctx *ctx); int qcom_scm_pas_auth_and_reset(u32 peripheral); int qcom_scm_pas_shutdown(u32 peripheral); bool qcom_scm_pas_supported(u32 peripheral); --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C1FB82E22B9 for ; Tue, 19 Aug 2025 16:55:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622541; cv=none; b=M284XxISLBNMYah4gc9w8DNkbicX9qUKmleZZyHepNcbuumPpfZku9DVTQzHvjJvXPmLcvSVXpbm7W1IuWjJ3ryuIDFxGXyrRQQ5CDcJ+lL5krRb4nh0CgO5ngVmjh0Mwo6FyNPKmlxAneZyxOdFsmU8DvUCkPSdpb2c1d7cOcg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622541; c=relaxed/simple; bh=Jz5i0hb8iPyBN4hHz1WzlmNjotDeNcwA9V2rf5gcWrE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=mG9E4JRKMV0JJefznBkhn9HBwtlQMiyghntL2FsqvGvMlpDYlOfj/2DXDk3nxm8O+D8GlEOMHuQvNC0Twh13gnfAuK+3ESj7fMheHPaYwtt4urOaLJmBb/2zcVH8jVTP9tDBKKrWO/8ojTIN1x4XCFT8Dkw4y0adsMsE1AU6YZg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=NUr/u2nm; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="NUr/u2nm" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90Ysv023100 for ; Tue, 19 Aug 2025 16:55:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=MHzX4m9djdY BrCYq6RUgrrQ8tJswsBpsxDwBSp7qf/U=; b=NUr/u2nmxmdVRpXNIpi6Bv/ZqJF QaF80JGuChksMqQWy5NghH2UKhmKs/DyGXhWImn0feeIlofLOqVX9jY3q7mo38IX kepnbVDMivsFl9nwsC/IjIL7rxMI3voD2/CDVL1tpyduMjPWpoHpKCPFKVF9X/Fv mRdjtAy50pwfxZ0vbwX+bcDaB5Kndt//uW241ypCIczKc+CNUDtrxzJVgx7Zb/bf 0WlLgwbdIcFtn+ZxqhfgyMWY0+/oeElA2farCiWXCtqbt3PABUtQNVApONhHFl77 2eTn+FS2HFIdzSZXtEigG6kCG9XsWmyGl3HBNFyaDF3JgJJkOoLON48PEfQ== Received: from mail-pl1-f198.google.com (mail-pl1-f198.google.com [209.85.214.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48mca5k1ju-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:39 +0000 (GMT) Received: by mail-pl1-f198.google.com with SMTP id d9443c01a7336-2445823bc21so137729755ad.3 for ; Tue, 19 Aug 2025 09:55:39 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622538; x=1756227338; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MHzX4m9djdYBrCYq6RUgrrQ8tJswsBpsxDwBSp7qf/U=; b=G3XfFKjpwnRm67YGM1bDjTVGAkw0jFTFIKrcPxASBzfypyQfJ1xxXmNJZD9gpfZ62d 1I9PB91a+cKeygvv8RHQTuIu0/qanbAJPjPHem81NLJFjkGJ3h4gf7gnV3+Sk8/sGeEJ VLp851QdGnsqad3T1ChTcsBKa9IPROWpDPN7F0ECcm6uqsJS0EdqMdCdqL2ZOzfarxxR zOFZ3g+STqAz2/LjKM0XjmPTeZvVD9jW3OyG/R6KWqq5U4GaG2ahSrKm5jkKHCmJy/et mehxi3kU4moVgjliSSD3ARYxEFW+cycGQhwMEx+2k6RKr+At8EqAJktlYDxR7VJa2875 UVCg== X-Forwarded-Encrypted: i=1; AJvYcCVeYiNss5rj0hnT+I0gnQF2i46tSShj1XexWnZg0Hj25Lo+fVjFLMWYAD23aXKVi5Cm/DPEvJ+JektqttE=@vger.kernel.org X-Gm-Message-State: AOJu0YxcE0AdQjXapkUuLusG+k4nFpRM9zSi1hLAtgzHFpr+Mf+ecdRI aQga3L4+moGAhTDhdQiYMsdbsRwO6AarNNPX8X9vorbZMAvJzBpalkROOhuVDNizDDvrTW/NZnU ym3fm1JOP4DMOcxyvHN6GkCf56Xflk5qReZbk1zmTlxgvkEwPQXqxRPmXDijbHVbzwvA= X-Gm-Gg: ASbGnctMm5mDt/intyFBjsjYDLCcQ3dNdsqerInR72HMj6JFP15rLM/v5ZXyV629Lhs A1konOrHdk2yN05E4pIy+PWcXDulAS3IUzSfci0+/DBjJNQGKEGpWAZl+Ej2L4TjIbNAqhMu5Rq mw1nyueJQk8S/oeOaDtHNdpIb9oS+ud6O80AyDzFcXUA34boqS3YFfB85ZnUnRJBiuxy9iLUy21 JfZuoryXjztiYFzAvCn6TWsAIB3XDUJmuvZJvMhZAchBzHBREaoPAxHm+chQSz8sfJ4tojUTQ4G 4P2Ice3Uvnb4cSnRfcwCieDxzxl5/+ajGjfdDA/dyJ+TJuaMr7yPx9C11FU83R9BSlw= X-Received: by 2002:a17:902:ea0b:b0:243:597:a2d6 with SMTP id d9443c01a7336-245e02a52ecmr56407085ad.1.1755622538302; Tue, 19 Aug 2025 09:55:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHdZh+CflCKOL+J9L55ubWiuqFife6t4XkwShQjJuGcwmfkYC9b9mA7fxGUIeUJ/HsPN4t1Pw== X-Received: by 2002:a17:902:ea0b:b0:243:597:a2d6 with SMTP id d9443c01a7336-245e02a52ecmr56406285ad.1.1755622537275; Tue, 19 Aug 2025 09:55:37 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:36 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 04/11] firmware: qcom_scm: Simplify qcom_scm_pas_init_image() Date: Tue, 19 Aug 2025 22:24:39 +0530 Message-ID: <20250819165447.4149674-5-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=FdU3xI+6 c=1 sm=1 tr=0 ts=68a4ac8b cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=7vI4Mn6wnVF6ixtUiuoA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: hqiK4IeEU8hOEKJHYOw2wCoSDTIW6nId X-Proofpoint-GUID: hqiK4IeEU8hOEKJHYOw2wCoSDTIW6nId X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE4MDIwMiBTYWx0ZWRfX1bCls0mUq0BC VQQ0H+BDigIQ8Efr3uWCttT913z9mde6sSdkNKN4lQ+AjJa/UlWG2aMVOsVHvoTp/2MVbFhQYUF hguNDCEy96kQmijnrDcmBDgJDsx/yjJ/1mI7X6ATbtugYa0fsClCvYthg3EABieijMJZ/zWi+8i NKCFgYZz3BXcPRWERTNe8e6GnReFcV0LyWK2duSJpMe3lKEcHmzjKahmZeEm8iFwn/xno6gejxr bybwJun1teA7q0pFMp2YK5K7m0CVMn/N2j8eWmMhJxaWi8KOvIHlThGGJX+U36HIwXhTBOZzoHN 5WK1LA9kxJpn6gCtAG9YO6DTmCxHIz7q/e7Q8ofhHmwGm3ze2nSs9GnsROJ7GnIYJR9ZmqgWzh9 IyCWU8+O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 phishscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508180202 Content-Type: text/plain; charset="utf-8" Simplify qcom_scm_pas_init_image() by making the memory allocation, copy and free work in a separate function then the actual SMC call. Signed-off-by: Mukesh Ojha Reviewed-by: Bryan O'Donoghue --- drivers/firmware/qcom/qcom_scm.c | 59 ++++++++++++++++++-------------- 1 file changed, 34 insertions(+), 25 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 9a5b34f5bacb..7827699e277c 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -584,6 +584,38 @@ void *qcom_scm_pas_ctx_init(struct device *dev, u32 pe= ripheral, phys_addr_t mem_ } EXPORT_SYMBOL_GPL(qcom_scm_pas_ctx_init); =20 +static int __qcom_scm_pas_init_image(u32 peripheral, dma_addr_t mdata_phys, + void *metadata, size_t size, + struct qcom_scm_res *res) +{ + int ret; + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_PIL, + .cmd =3D QCOM_SCM_PIL_PAS_INIT_IMAGE, + .arginfo =3D QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), + .args[0] =3D peripheral, + .owner =3D ARM_SMCCC_OWNER_SIP, + }; + + ret =3D qcom_scm_clk_enable(); + if (ret) + return ret; + + ret =3D qcom_scm_bw_enable(); + if (ret) + goto disable_clk; + + desc.args[1] =3D mdata_phys; + + ret =3D qcom_scm_call(__scm->dev, &desc, res); + qcom_scm_bw_disable(); + +disable_clk: + qcom_scm_clk_disable(); + + return ret; +} + /** * qcom_scm_pas_init_image() - Initialize peripheral authentication service * state machine for a given peripheral, using the @@ -604,17 +636,10 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_ctx_init); int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t s= ize, struct qcom_scm_pas_metadata *ctx) { + struct qcom_scm_res res; dma_addr_t mdata_phys; void *mdata_buf; int ret; - struct qcom_scm_desc desc =3D { - .svc =3D QCOM_SCM_SVC_PIL, - .cmd =3D QCOM_SCM_PIL_PAS_INIT_IMAGE, - .arginfo =3D QCOM_SCM_ARGS(2, QCOM_SCM_VAL, QCOM_SCM_RW), - .args[0] =3D peripheral, - .owner =3D ARM_SMCCC_OWNER_SIP, - }; - struct qcom_scm_res res; =20 /* * During the scm call memory protection will be enabled for the meta @@ -635,23 +660,7 @@ int qcom_scm_pas_init_image(u32 peripheral, const void= *metadata, size_t size, =20 memcpy(mdata_buf, metadata, size); =20 - ret =3D qcom_scm_clk_enable(); - if (ret) - goto out; - - ret =3D qcom_scm_bw_enable(); - if (ret) - goto disable_clk; - - desc.args[1] =3D mdata_phys; - - ret =3D qcom_scm_call(__scm->dev, &desc, &res); - qcom_scm_bw_disable(); - -disable_clk: - qcom_scm_clk_disable(); - -out: + ret =3D __qcom_scm_pas_init_image(peripheral, mdata_phys, mdata_buf, size= , &res); if (ret < 0 || !ctx) { dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); } else if (ctx) { --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24CA22FA0FF for ; Tue, 19 Aug 2025 16:55:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622545; cv=none; b=ORXm9CYkVz+kql5SpfJN1ufOi8v7y6ADWk3rziy+MNhPzR0wR8gkVynRcEsWU+vxdA75G0T4uTJWD6ykZ8jFNVz5tjaV1/H1FeKxTHRVFdPgkif6TpTKLJ7KQAuDUOCXp45m+ZCnUJi7J1EUCZ9FkNsOTn66R+dHSafXnE9Jwnc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622545; c=relaxed/simple; bh=igmWXGDfZJgGqYLQsdWmweoZviV0aJv6y/WleauHOUM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=U4vF3W3Cl7kxuWFV2YKRBeS/+BoLCKh88/U8G8EfQWnkzN2czUmwDYslTHoYsklgAF70cIXoeAGudZO0vh0WKwaqTjw9v5d7jnG1jdOpPo65WyEnJZU9FUa9R1c5cJalP6e9+pvOasEviMESJtjTbAttcc7e1Fih9Hx7WfeXRjE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=M9OmXDBT; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="M9OmXDBT" Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57JFL7oi006540 for ; Tue, 19 Aug 2025 16:55:43 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= CjgXp1Y64nh4dU4S4gqNWdoW+21OmjzNlNKNUULzdWM=; b=M9OmXDBTor4vXzNP SWxLZqdfIT/rEVeIWXeBSmknm4ZO4RWErkAyRq/NlbxsQU/iTfO9sB21RtZFtCBY auODGNEKS4OSAqrU3GymlyIFPXFJK1CNmLStwlvwQvXdJxxj1zaReP2D2EUbU11x CcrHN+3KMjQTQC8K1b5mKaNvn9ShdO1nkgriak4Mb4E0MRR1S4XuSWndKCUdr7R6 zapUdDjC974G23Xrjf3a/H+iFX2Oy2LPCvTuno/qMXaMvuHnyNP2RCvFyUB/TNEH /nqHoA3XxveEof1iqxcGy7CwbBmYazDbdJ7K6I/iWvYbNocW2akYNmEmdvWl8c53 muIV3g== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48muu0ga2d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:43 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-2445806b18aso61128295ad.1 for ; Tue, 19 Aug 2025 09:55:42 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622542; x=1756227342; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CjgXp1Y64nh4dU4S4gqNWdoW+21OmjzNlNKNUULzdWM=; b=RuyBqPTqcRL/mVnUGrw6N0MDeQ2cosQvCRe1NL29Gxj7qhhjbzqp8kFtsCusVLoMPn VREgqoi1j/s6Gk51GgDLUqW4DOL5f7NdOJ3UslmvKY/9R2od4xWn2rujRoT+Jj8pZgAE Kkqvu1Wrf0PJD5Zy50ya5xjig4BcR8eBkQphmxQPI38Gj1dSooiwmFJHKIZCBOX9/EyM bcbHWXXD8eIJkeqepyJZNR0qx3OG/dLJCjJ8LNuZ3CA4hAvYqD8ICKK0fxuW0stmI/u0 t177FiziVYY8qgCafo2QOkykUvZo6KYRizAWD3PZ/eiCk1iAkayNwunVJd8Dbc+ftSP0 p5eg== X-Forwarded-Encrypted: i=1; AJvYcCXak5sWckwfvASWfR8llaQ7eUcbcrKkUDZ41OIpATxbXmeLP3H60ZSuDTGqxZ4lZHtzePonic98kw+C+fw=@vger.kernel.org X-Gm-Message-State: AOJu0YxQVNhCFiVMy1gIBVwht/o+ZblCAdPsMJ/wUmS8Ct5owMtWfnZi 0wOwpP/KS5HIDydejRRZuLDPRDjX6pYHW9NHroJrSOfMZTn7JYWytw5FRsEIHGEyCyGiu6zYYVZ qdyMT0ovFLdIfvz019a/F93TP7TTp00IHBBplhG/I49xayTOq6EFz0JXnNn1zhvJzCeo= X-Gm-Gg: ASbGncuiws+uQWi45MeNx9WjVyWjlA8Y2cK45gDPds/B10mQycTSngE1sF6MFjUl0Vh U2XE+vWcJyfcNtAI4wjIP67ch6pC+aRHY5kH7sxAwdOnSRZBf734C/JPUMYcQSExvRZyrW/NC+/ yMIHBg1zcVpgxx6kURk3nwcVeXKFcri6WQpiu3Den2xzHIUzONYsRLpuwi3gytHevcxjisB0mgS dNJM6TTjnqNn9VeKikMLCMLP8qZQ0Co4+NgoAF1HfSNq1eIdiS29Q/BKeb0i5ZYJQ4QaO6ewgJV Hm9IXkqO8grMt00397hp9tHPzyU65G5euTyZUuewng9XQBp+/gnqQ359x1Yalyu0q0c= X-Received: by 2002:a17:903:90d:b0:240:a222:230c with SMTP id d9443c01a7336-245e04347d4mr44873675ad.12.1755622541963; Tue, 19 Aug 2025 09:55:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEjSbx6hP0IXrtwYPwayQaEdPlolnmEHoQI6x7PsME5hqHanrSk6OjmUJzYGCOGXay3PmcQCg== X-Received: by 2002:a17:903:90d:b0:240:a222:230c with SMTP id d9443c01a7336-245e04347d4mr44873265ad.12.1755622541415; Tue, 19 Aug 2025 09:55:41 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:41 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 05/11] firmware: qcom_scm: Add shmbridge support to pas_init/release function Date: Tue, 19 Aug 2025 22:24:40 +0530 Message-ID: <20250819165447.4149674-6-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: _ZTU_jwe9b5tV3Az4zrsQyd-N6PbSJT- X-Authority-Analysis: v=2.4 cv=YtYPR5YX c=1 sm=1 tr=0 ts=68a4ac8f cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=ztJyIkpEuA6XkPtyt7wA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE5MDE0MyBTYWx0ZWRfX6+m0/kPvQemv 5gursR0yfUC+t1/gAdhfirqVOwdbn6HBd1S2BrzReADePB5Laog5CD6b12U3qlxik876Wke4QiD AJE8iSIjuU65WPP63MNy37LBOfXKJaEU1xxu5qZQzsUg0cnuy8Pidm0WNgFaNrljRT42KNcZPGz Mp6jgfuCfTgPTLMkY51uWK+WL/KHdZGrnRmdJ5LsksoKE507gQx81FgZn6SmC28qa1TjzndGqgQ +Hv0fDYd4e1CMU0ybPv1YcRSL5rgC+JRzCpLE6KVifcyTHFYlbvuh0a3+LzHJEaR3GC/RZudHoy W6kD4NBaihTNHTYh9z0T75dKpZzERg89fKlatRp8X+6u8u6Emr1Y+O82YYUfKZ07RD+3jKW+ujN e2eC9v7B X-Proofpoint-ORIG-GUID: _ZTU_jwe9b5tV3Az4zrsQyd-N6PbSJT- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 spamscore=0 priorityscore=1501 clxscore=1015 suspectscore=0 bulkscore=0 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508190143 Qualcomm SoCs running with QHEE (Qualcomm Hypervisor Execution Environment=E2=80=94a library present in the Gunyah hypervisor) utilize the Peripheral Authentication Service (PAS) from Qualcomm TrustZone (TZ) also called QTEE(Qualcomm Trusted Execution Environment firmware) to securely authenticate and reset remote processors via a sequence of SMC calls such as qcom_scm_pas_init_image(), qcom_scm_pas_mem_setup(), and qcom_scm_pas_auth_and_reset(). For memory passed to Qualcomm TrustZone, it must either be part of a pool registered with TZ or be directly registered via SHMbridge SMC calls. When QHEE is present, PAS SMC calls from Linux running at EL1 are trapped by QHEE (running at EL2), which then creates or retrieves memory from the SHM bridge for both metadata and remoteproc carveout memory before passing them to TZ. However, when the SoC runs with a non-QHEE-based hypervisor, Linux must create the SHM bridge for both metadata (before it is passed to TZ in qcom_scm_pas_init_image()) and for remoteproc memory (before the call is made to TZ in qcom_scm_pas_auth_and_reset()). For the qcom_scm_pas_init_image() call, metadata content must be copied to a buffer allocated from the SHM bridge before making the SMC call. This buffer should be freed either immediately after the call or during the qcom_scm_pas_metadata_release() function, depending on the context parameter passed to qcom_scm_pas_init_image(). Convert the metadata context parameter to use PAS context data structure so that it will also be possible to decide whether to get memory from SHMbridge pool or not. When QHEE is present, it manages the IOMMU translation context so, in absence of it device driver will be aware through device tree that its translation context is managed by Linux and it need to create SHMbridge before passing any buffer to TZ, So, remote processor driver should appropriately set ctx->has_iommu to let PAS SMC function to take care of everything ready for the call to work. Lets convert qcom_scm_pas_init_image() and qcom_scm_pas_metadata_release() to have these awareness. Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 71 +++++++++++++++++++++----- drivers/remoteproc/qcom_q6v5_pas.c | 14 ++--- drivers/soc/qcom/mdt_loader.c | 4 +- include/linux/firmware/qcom/qcom_scm.h | 9 ++-- 4 files changed, 73 insertions(+), 25 deletions(-) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 7827699e277c..301d440f62f3 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -616,6 +616,35 @@ static int __qcom_scm_pas_init_image(u32 peripheral, d= ma_addr_t mdata_phys, return ret; } =20 +static int qcom_scm_pas_prep_and_init_image(struct qcom_scm_pas_ctx *ctx, + const void *metadata, size_t size) +{ + struct qcom_scm_pas_metadata *mdt_ctx; + struct qcom_scm_res res; + phys_addr_t mdata_phys; + void *mdata_buf; + int ret; + + mdt_ctx =3D ctx->metadata; + mdata_buf =3D qcom_tzmem_alloc(__scm->mempool, size, GFP_KERNEL); + if (!mdata_buf) + return -ENOMEM; + + memcpy(mdata_buf, metadata, size); + mdata_phys =3D qcom_tzmem_to_phys(mdata_buf); + + ret =3D __qcom_scm_pas_init_image(ctx->peripheral, mdata_phys, mdata_buf,= size, &res); + if (ret < 0 || !mdt_ctx) { + qcom_tzmem_free(mdata_buf); + } else if (mdt_ctx) { + mdt_ctx->ptr =3D mdata_buf; + mdt_ctx->addr.phys_addr =3D mdata_phys; + mdt_ctx->size =3D size; + } + + return ret ? : res.result[0]; +} + /** * qcom_scm_pas_init_image() - Initialize peripheral authentication service * state machine for a given peripheral, using the @@ -625,7 +654,7 @@ static int __qcom_scm_pas_init_image(u32 peripheral, dm= a_addr_t mdata_phys, * and optional blob of data used for authenticating the metadata * and the rest of the firmware * @size: size of the metadata - * @ctx: optional metadata context + * @ctx: optional pas context * * Return: 0 on success. * @@ -634,13 +663,19 @@ static int __qcom_scm_pas_init_image(u32 peripheral, = dma_addr_t mdata_phys, * qcom_scm_pas_metadata_release() by the caller. */ int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t s= ize, - struct qcom_scm_pas_metadata *ctx) + struct qcom_scm_pas_ctx *ctx) { + struct qcom_scm_pas_metadata *mdt_ctx; struct qcom_scm_res res; dma_addr_t mdata_phys; void *mdata_buf; int ret; =20 + if (ctx && ctx->has_iommu) { + ret =3D qcom_scm_pas_prep_and_init_image(ctx, metadata, size); + return ret; + } + /* * During the scm call memory protection will be enabled for the meta * data blob, so make sure it's physically contiguous, 4K aligned and @@ -663,10 +698,11 @@ int qcom_scm_pas_init_image(u32 peripheral, const voi= d *metadata, size_t size, ret =3D __qcom_scm_pas_init_image(peripheral, mdata_phys, mdata_buf, size= , &res); if (ret < 0 || !ctx) { dma_free_coherent(__scm->dev, size, mdata_buf, mdata_phys); - } else if (ctx) { - ctx->ptr =3D mdata_buf; - ctx->phys =3D mdata_phys; - ctx->size =3D size; + } else if (ctx->metadata) { + mdt_ctx =3D ctx->metadata; + mdt_ctx->ptr =3D mdata_buf; + mdt_ctx->addr.dma_addr =3D mdata_phys; + mdt_ctx->size =3D size; } =20 return ret ? : res.result[0]; @@ -675,18 +711,27 @@ EXPORT_SYMBOL_GPL(qcom_scm_pas_init_image); =20 /** * qcom_scm_pas_metadata_release() - release metadata context - * @ctx: metadata context + * @ctx: pas context */ -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx) +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_ctx *ctx) { - if (!ctx->ptr) + struct qcom_scm_pas_metadata *mdt_ctx; + + mdt_ctx =3D ctx->metadata; + if (!mdt_ctx->ptr) return; =20 - dma_free_coherent(__scm->dev, ctx->size, ctx->ptr, ctx->phys); + if (ctx->has_iommu) { + qcom_tzmem_free(mdt_ctx->ptr); + mdt_ctx->addr.phys_addr =3D 0; + } else { + dma_free_coherent(__scm->dev, mdt_ctx->size, mdt_ctx->ptr, + mdt_ctx->addr.dma_addr); + mdt_ctx->addr.dma_addr =3D 0; + } =20 - ctx->ptr =3D NULL; - ctx->phys =3D 0; - ctx->size =3D 0; + mdt_ctx->ptr =3D NULL; + mdt_ctx->size =3D 0; } EXPORT_SYMBOL_GPL(qcom_scm_pas_metadata_release); =20 diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index e376c0338576..09cada92dfd5 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -209,9 +209,9 @@ static int qcom_pas_unprepare(struct rproc *rproc) * auth_and_reset() was successful, but in other cases clean it up * here. */ - qcom_scm_pas_metadata_release(pas->pas_ctx->metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx->metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); =20 return 0; } @@ -244,7 +244,7 @@ static int qcom_pas_load(struct rproc *rproc, const str= uct firmware *fw) return 0; =20 release_dtb_metadata: - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx->metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); release_firmware(pas->dtb_firmware); =20 return ret; @@ -313,9 +313,9 @@ static int qcom_pas_start(struct rproc *rproc) goto release_pas_metadata; } =20 - qcom_scm_pas_metadata_release(pas->pas_ctx->metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx->metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); =20 /* firmware is used to pass reference from qcom_pas_start(), drop it now = */ pas->firmware =3D NULL; @@ -323,9 +323,9 @@ static int qcom_pas_start(struct rproc *rproc) return 0; =20 release_pas_metadata: - qcom_scm_pas_metadata_release(pas->pas_ctx->metadata); + qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) - qcom_scm_pas_metadata_release(pas->dtb_pas_ctx->metadata); + qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); disable_px_supply: if (pas->px_supply) regulator_disable(pas->px_supply); diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index 509ff85d9bf6..a1718db91b3e 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -240,7 +240,7 @@ EXPORT_SYMBOL_GPL(qcom_mdt_read_metadata); */ static int __qcom_mdt_pas_init(struct device *dev, const struct firmware *= fw, const char *fw_name, int pas_id, phys_addr_t mem_phys, - struct qcom_scm_pas_metadata *ctx) + struct qcom_scm_pas_ctx *ctx) { const struct elf32_phdr *phdrs; const struct elf32_phdr *phdr; @@ -491,7 +491,7 @@ int qcom_mdt_pas_load(struct qcom_scm_pas_ctx *ctx, con= st struct firmware *fw, int ret; =20 ret =3D __qcom_mdt_pas_init(ctx->dev, fw, firmware, ctx->peripheral, - ctx->mem_phys, ctx->metadata); + ctx->mem_phys, ctx); if (ret) return ret; =20 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index a31006fe49a9..bd3417d9c3f9 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -68,7 +68,10 @@ int qcom_scm_set_remote_state(u32 state, u32 id); =20 struct qcom_scm_pas_metadata { void *ptr; - dma_addr_t phys; + union { + dma_addr_t dma_addr; + phys_addr_t phys_addr; + } addr; ssize_t size; }; =20 @@ -85,8 +88,8 @@ struct qcom_scm_pas_ctx { void *qcom_scm_pas_ctx_init(struct device *dev, u32 peripheral, phys_addr_= t mem_phys, size_t mem_size, bool save_mdt_ctx); int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t s= ize, - struct qcom_scm_pas_metadata *ctx); -void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx); + struct qcom_scm_pas_ctx *ctx); +void qcom_scm_pas_metadata_release(struct qcom_scm_pas_ctx *ctx); int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t s= ize); int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_ctx *ctx); int qcom_scm_pas_auth_and_reset(u32 peripheral); --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB16B2FE04A for ; Tue, 19 Aug 2025 16:55:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622551; cv=none; b=dKpGANsYothLJvhk0ji694Ua06vi37CqenT0EUKqpzfaiE1hG/z9Vq+eAJ+R1IWrb7mC4xfyUuXCGdkJDGjUrUrff57EA4RcuGQiyphE2UVSHgiZpouojGKSOhdI0golb693m4eyAEHaqVbf4YSZ7yH/R5MWpd2CqAXsYPW8ebQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622551; c=relaxed/simple; bh=6uARc0vcWDCi81bBukzSSmsTavWRG+fZaiu9oKnZQEE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=XcP9eEwKADx/HKf9EdCYpBDAoaHl8xGxeu/kkRNoUofOdkIdh87K29zrdGFddSJhkgvfUciCL6Zo1QBGLSLoc7mXr6M84mHJmTePe15S/C7H0h1HWYG67wA0Dg0nYd4g9/jn2kwTq4n2q6BGuU+fDr6A2bapE6UbIvh9RpOF2ns= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=CpV5vJSb; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="CpV5vJSb" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90XZ6008279 for ; Tue, 19 Aug 2025 16:55:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= OIdi5u8DuhRCI3eqLELOEnZhKOfN2ulzVRZrP+89AOE=; b=CpV5vJSb8pZnEcTD DQxK3GsFUCweaDj2sPH0e0aUB7NBV/eHVRccy2FVGZmTe8OIX2fRM4UKik5eaVhg oJKc6vez1oT/ImOW0DCtyfceTVCmnG2E7YTpmvIUYOTlOoWBwVpDPK3BrRn0ozPo S1HgcnDjBeHhzwX9q+dbrv7hGy5QrRvsvLlQczkx2FGbFgGbIYealfese1uOO1JW Aw+ZyOBoAR3QngCyj7Taj5ho3+9+uHE34aNQ2D9WfYhl0GRBY4Y2TJsZABTEvgJl pSXKkcenNmhgN9hmb50fYUDToEmgVOtApUtt9bRROhCxe2DNyLL6tvDP82I1iEyD Apw46w== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48jk99s984-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:47 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-24457f42254so132451825ad.0 for ; Tue, 19 Aug 2025 09:55:47 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622547; x=1756227347; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OIdi5u8DuhRCI3eqLELOEnZhKOfN2ulzVRZrP+89AOE=; b=G2dTuPt9xOPpKp95CDQbDTXk2rFly1imTG+dvJIOtO5Rohhse6zh1XP28aZ1utJyUI MFAdgORinjajTc//PrRPgN5yMVspwvcU1VCwd+IMjN64RpmBNigrLcVyNLhZiox3AgFE xxRMO0dL7fCaIKDU5l8iE1H04EKjlbAt4W4wx1TBjredAzRL5R1KYvzq2wx+gvUs36mT l02l2WLNoeYHt/bkAAjHI3A4RVHrUaVEPQNoD9o0K7WAlFlYkNAJ1ROym6jOfxOhdhGT 1b/Z34rVzmXpur8rzD6S3m21mdSEQOxIwrAQF1ZsCiDI/sukjyZcbe+3u7DQ3D8l6VGe +/wg== X-Forwarded-Encrypted: i=1; AJvYcCVDaYuYnlEiXAvrPMCplC201+XoVvC7J53KCrWoNSFPfHTGvW2BFphuobyYWRHSDppWtCF+NttNBhxA6JM=@vger.kernel.org X-Gm-Message-State: AOJu0YwIT4wTWYkmW/skFz9cOG2owBJNYMaVx6z/mp6z8kO7E8JoTMjg L3pNguiEQFCemt/SKJhqrpTDYgy3pVqZX3AOJAuWEleHutexmIdp0keGNPuJIrGuw1UDplkSk0m q/fkZSum69oscdwD9GnXk4sKA/gHzZpUNo272Rv7lz4msHbRgkdOvKrMqh8lMC7X84MQ= X-Gm-Gg: ASbGnctmVdb12GOHYXNl5gv1eO0CjfIG8u3nS/PDvqND7kjFz22ZUWEEoBGsPmUYXUF yStrCVrDZxkBpX1h6qpIlik8+U1wdTcopmdRwxv3IKV6Ysgyyb3I4Tq4rNh9X0PQO5XQFvu1P31 8WPt8cOnCvj9Nb9WIhH+MrrWkM+7Lhjwc2ty8CfgXGR5TxarQEJvlOp8tfX3wvLINAbHIS6IdV6 BQx3ZGkdcWbaJQ57hdMftTdg/YaHS9Gy1YGV2781h5DmpaTTvaG2k+KbImTX0hluap6SSmeiQtS mWADMXBkluNDeR79B9uBFwnmJH2AUMkp+MhHdqCnoFvtVir0G7kffX24pzVStYIDPPk= X-Received: by 2002:a17:903:f86:b0:234:b123:b4ff with SMTP id d9443c01a7336-245e030dcc5mr37283665ad.21.1755622546397; Tue, 19 Aug 2025 09:55:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGlv3/HxdpCBT3YNIgL40FoV62d5oil2G8WGXtNSzI2tuHRffr1GEdKFOqkN74PCrIbi8L2Aw== X-Received: by 2002:a17:903:f86:b0:234:b123:b4ff with SMTP id d9443c01a7336-245e030dcc5mr37283365ad.21.1755622545643; Tue, 19 Aug 2025 09:55:45 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:45 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 06/11] remoteproc: Move resource table data structure to its own header Date: Tue, 19 Aug 2025 22:24:41 +0530 Message-ID: <20250819165447.4149674-7-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 5pDbFp_0cSfYF_R7YkmG8ULlllZfiQxG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDA0NSBTYWx0ZWRfX+6ljIAh/4gRk afu65sTJR1PYVoUcdj92DdB8KDpHFRoHrAsF5qxYK4vXDUoUymC7iwbNxIkGTPH0iKqkYxTIXAD posckGIGa0BKjkqLO4Fshb9GR1HvzrYCgUQn4dQZbmUlPBfdJC/B/C5bUl4WqC/snCHAocnYxKP fUlLqy3wPCo7hN8/l/ZkgtTkMywjSe9PVP4k4hyR2Lq4ehH9Ng7/Byov9z8om27x3EtaOSQa9J6 QITuntDDdUdEDVk4NG+miu5tEKwRb++MdlCBKRAnEfn26Ay0wo/VdzcwnlQVsyt/ocNfO8txvo9 RW86+FlvNtZnrcYSavGH7BMWap9tYmnHhMfy053TOz4w530OkiseUeMAWRs/bekhPC5k4ygoMIB Hm1dDRt+ X-Authority-Analysis: v=2.4 cv=IIMCChvG c=1 sm=1 tr=0 ts=68a4ac94 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=hqicfOp3TDPPg1m-M2YA:9 a=Y6HKh-LrsuiIPCo2:21 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: 5pDbFp_0cSfYF_R7YkmG8ULlllZfiQxG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 clxscore=1015 impostorscore=0 phishscore=0 adultscore=0 malwarescore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160045 The resource table data structure has traditionally been associated with the remoteproc framework, where the resource table is included as a section within the remote processor firmware binary. However, it is also possible to obtain the resource table through other means=E2=80=94such as f= rom a reserved memory region populated by the boot firmware, statically maintained driver data, or via a secure SMC call=E2=80=94when it is not emb= edded in the firmware. There are multiple Qualcomm remote processors (e.g., Venus, Iris, GPU, etc.) in the upstream kernel that do not use the remoteproc framework to manage their lifecycle for various reasons. When Linux is running at EL2, similar to the Qualcomm PAS driver (qcom_q6v5_pas.c), client drivers for subsystems like video and GPU may also want to use the resource table SMC call to retrieve and map resources before they are used by the remote processor. In such cases, the resource table data structure is no longer tightly coupled with the remoteproc headers. Client drivers that do not use the remoteproc framework should still be able to parse the resource table obtained through alternative means. Therefore, there is a need to decouple the resource table definitions from the remoteproc headers. Signed-off-by: Mukesh Ojha --- include/linux/remoteproc.h | 269 +------------------------------- include/linux/rsc_table.h | 306 +++++++++++++++++++++++++++++++++++++ 2 files changed, 307 insertions(+), 268 deletions(-) create mode 100644 include/linux/rsc_table.h diff --git a/include/linux/remoteproc.h b/include/linux/remoteproc.h index b4795698d8c2..7c1546d48008 100644 --- a/include/linux/remoteproc.h +++ b/include/linux/remoteproc.h @@ -42,274 +42,7 @@ #include #include #include - -/** - * struct resource_table - firmware resource table header - * @ver: version number - * @num: number of resource entries - * @reserved: reserved (must be zero) - * @offset: array of offsets pointing at the various resource entries - * - * A resource table is essentially a list of system resources required - * by the remote processor. It may also include configuration entries. - * If needed, the remote processor firmware should contain this table - * as a dedicated ".resource_table" ELF section. - * - * Some resources entries are mere announcements, where the host is inform= ed - * of specific remoteproc configuration. Other entries require the host to - * do something (e.g. allocate a system resource). Sometimes a negotiation - * is expected, where the firmware requests a resource, and once allocated, - * the host should provide back its details (e.g. address of an allocated - * memory region). - * - * The header of the resource table, as expressed by this structure, - * contains a version number (should we need to change this format in the - * future), the number of available resource entries, and their offsets - * in the table. - * - * Immediately following this header are the resource entries themselves, - * each of which begins with a resource entry header (as described below). - */ -struct resource_table { - u32 ver; - u32 num; - u32 reserved[2]; - u32 offset[]; -} __packed; - -/** - * struct fw_rsc_hdr - firmware resource entry header - * @type: resource type - * @data: resource data - * - * Every resource entry begins with a 'struct fw_rsc_hdr' header providing - * its @type. The content of the entry itself will immediately follow - * this header, and it should be parsed according to the resource type. - */ -struct fw_rsc_hdr { - u32 type; - u8 data[]; -} __packed; - -/** - * enum fw_resource_type - types of resource entries - * - * @RSC_CARVEOUT: request for allocation of a physically contiguous - * memory region. - * @RSC_DEVMEM: request to iommu_map a memory-based peripheral. - * @RSC_TRACE: announces the availability of a trace buffer into which - * the remote processor will be writing logs. - * @RSC_VDEV: declare support for a virtio device, and serve as its - * virtio header. - * @RSC_LAST: just keep this one at the end of standard resources - * @RSC_VENDOR_START: start of the vendor specific resource types range - * @RSC_VENDOR_END: end of the vendor specific resource types range - * - * For more details regarding a specific resource type, please see its - * dedicated structure below. - * - * Please note that these values are used as indices to the rproc_handle_r= sc - * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to - * check the validity of an index before the lookup table is accessed, so - * please update it as needed. - */ -enum fw_resource_type { - RSC_CARVEOUT =3D 0, - RSC_DEVMEM =3D 1, - RSC_TRACE =3D 2, - RSC_VDEV =3D 3, - RSC_LAST =3D 4, - RSC_VENDOR_START =3D 128, - RSC_VENDOR_END =3D 512, -}; - -#define FW_RSC_ADDR_ANY (-1) - -/** - * struct fw_rsc_carveout - physically contiguous memory request - * @da: device address - * @pa: physical address - * @len: length (in bytes) - * @flags: iommu protection flags - * @reserved: reserved (must be zero) - * @name: human-readable name of the requested memory region - * - * This resource entry requests the host to allocate a physically contiguo= us - * memory region. - * - * These request entries should precede other firmware resource entries, - * as other entries might request placing other data objects inside - * these memory regions (e.g. data/code segments, trace resource entries, = ...). - * - * Allocating memory this way helps utilizing the reserved physical memory - * (e.g. CMA) more efficiently, and also minimizes the number of TLB entri= es - * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB - * pressure is important; it may have a substantial impact on performance. - * - * If the firmware is compiled with static addresses, then @da should spec= ify - * the expected device address of this memory region. If @da is set to - * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then - * overwrite @da with the dynamically allocated address. - * - * We will always use @da to negotiate the device addresses, even if it - * isn't using an iommu. In that case, though, it will obviously contain - * physical addresses. - * - * Some remote processors needs to know the allocated physical address - * even if they do use an iommu. This is needed, e.g., if they control - * hardware accelerators which access the physical memory directly (this - * is the case with OMAP4 for instance). In that case, the host will - * overwrite @pa with the dynamically allocated physical address. - * Generally we don't want to expose physical addresses if we don't have to - * (remote processors are generally _not_ trusted), so we might want to - * change this to happen _only_ when explicitly required by the hardware. - * - * @flags is used to provide IOMMU protection flags, and @name should - * (optionally) contain a human readable name of this carveout region - * (mainly for debugging purposes). - */ -struct fw_rsc_carveout { - u32 da; - u32 pa; - u32 len; - u32 flags; - u32 reserved; - u8 name[32]; -} __packed; - -/** - * struct fw_rsc_devmem - iommu mapping request - * @da: device address - * @pa: physical address - * @len: length (in bytes) - * @flags: iommu protection flags - * @reserved: reserved (must be zero) - * @name: human-readable name of the requested region to be mapped - * - * This resource entry requests the host to iommu map a physically contigu= ous - * memory region. This is needed in case the remote processor requires - * access to certain memory-based peripherals; _never_ use it to access - * regular memory. - * - * This is obviously only needed if the remote processor is accessing memo= ry - * via an iommu. - * - * @da should specify the required device address, @pa should specify - * the physical address we want to map, @len should specify the size of - * the mapping and @flags is the IOMMU protection flags. As always, @name = may - * (optionally) contain a human readable name of this mapping (mainly for - * debugging purposes). - * - * Note: at this point we just "trust" those devmem entries to contain val= id - * physical addresses, but this isn't safe and will be changed: eventually= we - * want remoteproc implementations to provide us ranges of physical addres= ses - * the firmware is allowed to request, and not allow firmwares to request - * access to physical addresses that are outside those ranges. - */ -struct fw_rsc_devmem { - u32 da; - u32 pa; - u32 len; - u32 flags; - u32 reserved; - u8 name[32]; -} __packed; - -/** - * struct fw_rsc_trace - trace buffer declaration - * @da: device address - * @len: length (in bytes) - * @reserved: reserved (must be zero) - * @name: human-readable name of the trace buffer - * - * This resource entry provides the host information about a trace buffer - * into which the remote processor will write log messages. - * - * @da specifies the device address of the buffer, @len specifies - * its size, and @name may contain a human readable name of the trace buff= er. - * - * After booting the remote processor, the trace buffers are exposed to the - * user via debugfs entries (called trace0, trace1, etc..). - */ -struct fw_rsc_trace { - u32 da; - u32 len; - u32 reserved; - u8 name[32]; -} __packed; - -/** - * struct fw_rsc_vdev_vring - vring descriptor entry - * @da: device address - * @align: the alignment between the consumer and producer parts of the vr= ing - * @num: num of buffers supported by this vring (must be power of two) - * @notifyid: a unique rproc-wide notify index for this vring. This notify - * index is used when kicking a remote processor, to let it know that this - * vring is triggered. - * @pa: physical address - * - * This descriptor is not a resource entry by itself; it is part of the - * vdev resource type (see below). - * - * Note that @da should either contain the device address where - * the remote processor is expecting the vring, or indicate that - * dynamically allocation of the vring's device address is supported. - */ -struct fw_rsc_vdev_vring { - u32 da; - u32 align; - u32 num; - u32 notifyid; - u32 pa; -} __packed; - -/** - * struct fw_rsc_vdev - virtio device header - * @id: virtio device id (as in virtio_ids.h) - * @notifyid: a unique rproc-wide notify index for this vdev. This notify - * index is used when kicking a remote processor, to let it know that the - * status/features of this vdev have changes. - * @dfeatures: specifies the virtio device features supported by the firmw= are - * @gfeatures: a place holder used by the host to write back the - * negotiated features that are supported by both sides. - * @config_len: the size of the virtio config space of this vdev. The conf= ig - * space lies in the resource table immediate after this vdev header. - * @status: a place holder where the host will indicate its virtio progres= s. - * @num_of_vrings: indicates how many vrings are described in this vdev he= ader - * @reserved: reserved (must be zero) - * @vring: an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring= '. - * - * This resource is a virtio device header: it provides information about - * the vdev, and is then used by the host and its peer remote processors - * to negotiate and share certain virtio properties. - * - * By providing this resource entry, the firmware essentially asks remotep= roc - * to statically allocate a vdev upon registration of the rproc (dynamic v= dev - * allocation is not yet supported). - * - * Note: - * 1. unlike virtualization systems, the term 'host' here means - * the Linux side which is running remoteproc to control the remote - * processors. We use the name 'gfeatures' to comply with virtio's term= s, - * though there isn't really any virtualized guest OS here: it's the ho= st - * which is responsible for negotiating the final features. - * Yeah, it's a bit confusing. - * - * 2. immediately following this structure is the virtio config space for - * this vdev (which is specific to the vdev; for more info, read the vi= rtio - * spec). The size of the config space is specified by @config_len. - */ -struct fw_rsc_vdev { - u32 id; - u32 notifyid; - u32 dfeatures; - u32 gfeatures; - u32 config_len; - u8 status; - u8 num_of_vrings; - u8 reserved[2]; - struct fw_rsc_vdev_vring vring[]; -} __packed; +#include =20 struct rproc; =20 diff --git a/include/linux/rsc_table.h b/include/linux/rsc_table.h new file mode 100644 index 000000000000..c32c8b6cd2a7 --- /dev/null +++ b/include/linux/rsc_table.h @@ -0,0 +1,306 @@ +/* + * Resource table and its types data structure + * + * Copyright(c) 2011 Texas Instruments, Inc. + * Copyright(c) 2011 Google, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * * Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * * Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * * Neither the name Texas Instruments nor the names of its + * contributors may be used to endorse or promote products derived + * from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef RSC_TABLE_H +#define RSC_TABLE_H + +/** + * struct resource_table - firmware resource table header + * @ver: version number + * @num: number of resource entries + * @reserved: reserved (must be zero) + * @offset: array of offsets pointing at the various resource entries + * + * A resource table is essentially a list of system resources required + * by the remote processor. It may also include configuration entries. + * If needed, the remote processor firmware should contain this table + * as a dedicated ".resource_table" ELF section. + * + * Some resources entries are mere announcements, where the host is inform= ed + * of specific remoteproc configuration. Other entries require the host to + * do something (e.g. allocate a system resource). Sometimes a negotiation + * is expected, where the firmware requests a resource, and once allocated, + * the host should provide back its details (e.g. address of an allocated + * memory region). + * + * The header of the resource table, as expressed by this structure, + * contains a version number (should we need to change this format in the + * future), the number of available resource entries, and their offsets + * in the table. + * + * Immediately following this header are the resource entries themselves, + * each of which begins with a resource entry header (as described below). + */ +struct resource_table { + u32 ver; + u32 num; + u32 reserved[2]; + u32 offset[]; +} __packed; + +/** + * struct fw_rsc_hdr - firmware resource entry header + * @type: resource type + * @data: resource data + * + * Every resource entry begins with a 'struct fw_rsc_hdr' header providing + * its @type. The content of the entry itself will immediately follow + * this header, and it should be parsed according to the resource type. + */ +struct fw_rsc_hdr { + u32 type; + u8 data[]; +} __packed; + +/** + * enum fw_resource_type - types of resource entries + * + * @RSC_CARVEOUT: request for allocation of a physically contiguous + * memory region. + * @RSC_DEVMEM: request to iommu_map a memory-based peripheral. + * @RSC_TRACE: announces the availability of a trace buffer into which + * the remote processor will be writing logs. + * @RSC_VDEV: declare support for a virtio device, and serve as its + * virtio header. + * @RSC_LAST: just keep this one at the end of standard resources + * @RSC_VENDOR_START: start of the vendor specific resource types range + * @RSC_VENDOR_END: end of the vendor specific resource types range + * + * For more details regarding a specific resource type, please see its + * dedicated structure below. + * + * Please note that these values are used as indices to the rproc_handle_r= sc + * lookup table, so please keep them sane. Moreover, @RSC_LAST is used to + * check the validity of an index before the lookup table is accessed, so + * please update it as needed. + */ +enum fw_resource_type { + RSC_CARVEOUT =3D 0, + RSC_DEVMEM =3D 1, + RSC_TRACE =3D 2, + RSC_VDEV =3D 3, + RSC_LAST =3D 4, + RSC_VENDOR_START =3D 128, + RSC_VENDOR_END =3D 512, +}; + +#define FW_RSC_ADDR_ANY (-1) + +/** + * struct fw_rsc_carveout - physically contiguous memory request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested memory region + * + * This resource entry requests the host to allocate a physically contiguo= us + * memory region. + * + * These request entries should precede other firmware resource entries, + * as other entries might request placing other data objects inside + * these memory regions (e.g. data/code segments, trace resource entries, = ...). + * + * Allocating memory this way helps utilizing the reserved physical memory + * (e.g. CMA) more efficiently, and also minimizes the number of TLB entri= es + * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB + * pressure is important; it may have a substantial impact on performance. + * + * If the firmware is compiled with static addresses, then @da should spec= ify + * the expected device address of this memory region. If @da is set to + * FW_RSC_ADDR_ANY, then the host will dynamically allocate it, and then + * overwrite @da with the dynamically allocated address. + * + * We will always use @da to negotiate the device addresses, even if it + * isn't using an iommu. In that case, though, it will obviously contain + * physical addresses. + * + * Some remote processors needs to know the allocated physical address + * even if they do use an iommu. This is needed, e.g., if they control + * hardware accelerators which access the physical memory directly (this + * is the case with OMAP4 for instance). In that case, the host will + * overwrite @pa with the dynamically allocated physical address. + * Generally we don't want to expose physical addresses if we don't have to + * (remote processors are generally _not_ trusted), so we might want to + * change this to happen _only_ when explicitly required by the hardware. + * + * @flags is used to provide IOMMU protection flags, and @name should + * (optionally) contain a human readable name of this carveout region + * (mainly for debugging purposes). + */ +struct fw_rsc_carveout { + u32 da; + u32 pa; + u32 len; + u32 flags; + u32 reserved; + u8 name[32]; +} __packed; + +/** + * struct fw_rsc_devmem - iommu mapping request + * @da: device address + * @pa: physical address + * @len: length (in bytes) + * @flags: iommu protection flags + * @reserved: reserved (must be zero) + * @name: human-readable name of the requested region to be mapped + * + * This resource entry requests the host to iommu map a physically contigu= ous + * memory region. This is needed in case the remote processor requires + * access to certain memory-based peripherals; _never_ use it to access + * regular memory. + * + * This is obviously only needed if the remote processor is accessing memo= ry + * via an iommu. + * + * @da should specify the required device address, @pa should specify + * the physical address we want to map, @len should specify the size of + * the mapping and @flags is the IOMMU protection flags. As always, @name = may + * (optionally) contain a human readable name of this mapping (mainly for + * debugging purposes). + * + * Note: at this point we just "trust" those devmem entries to contain val= id + * physical addresses, but this isn't safe and will be changed: eventually= we + * want remoteproc implementations to provide us ranges of physical addres= ses + * the firmware is allowed to request, and not allow firmwares to request + * access to physical addresses that are outside those ranges. + */ +struct fw_rsc_devmem { + u32 da; + u32 pa; + u32 len; + u32 flags; + u32 reserved; + u8 name[32]; +} __packed; + +/** + * struct fw_rsc_trace - trace buffer declaration + * @da: device address + * @len: length (in bytes) + * @reserved: reserved (must be zero) + * @name: human-readable name of the trace buffer + * + * This resource entry provides the host information about a trace buffer + * into which the remote processor will write log messages. + * + * @da specifies the device address of the buffer, @len specifies + * its size, and @name may contain a human readable name of the trace buff= er. + * + * After booting the remote processor, the trace buffers are exposed to the + * user via debugfs entries (called trace0, trace1, etc..). + */ +struct fw_rsc_trace { + u32 da; + u32 len; + u32 reserved; + u8 name[32]; +} __packed; + +/** + * struct fw_rsc_vdev_vring - vring descriptor entry + * @da: device address + * @align: the alignment between the consumer and producer parts of the vr= ing + * @num: num of buffers supported by this vring (must be power of two) + * @notifyid: a unique rproc-wide notify index for this vring. This notify + * index is used when kicking a remote processor, to let it know that this + * vring is triggered. + * @pa: physical address + * + * This descriptor is not a resource entry by itself; it is part of the + * vdev resource type (see below). + * + * Note that @da should either contain the device address where + * the remote processor is expecting the vring, or indicate that + * dynamically allocation of the vring's device address is supported. + */ +struct fw_rsc_vdev_vring { + u32 da; + u32 align; + u32 num; + u32 notifyid; + u32 pa; +} __packed; + +/** + * struct fw_rsc_vdev - virtio device header + * @id: virtio device id (as in virtio_ids.h) + * @notifyid: a unique rproc-wide notify index for this vdev. This notify + * index is used when kicking a remote processor, to let it know that the + * status/features of this vdev have changes. + * @dfeatures: specifies the virtio device features supported by the firmw= are + * @gfeatures: a place holder used by the host to write back the + * negotiated features that are supported by both sides. + * @config_len: the size of the virtio config space of this vdev. The conf= ig + * space lies in the resource table immediate after this vdev header. + * @status: a place holder where the host will indicate its virtio progres= s. + * @num_of_vrings: indicates how many vrings are described in this vdev he= ader + * @reserved: reserved (must be zero) + * @vring: an array of @num_of_vrings entries of 'struct fw_rsc_vdev_vring= '. + * + * This resource is a virtio device header: it provides information about + * the vdev, and is then used by the host and its peer remote processors + * to negotiate and share certain virtio properties. + * + * By providing this resource entry, the firmware essentially asks remotep= roc + * to statically allocate a vdev upon registration of the rproc (dynamic v= dev + * allocation is not yet supported). + * + * Note: + * 1. unlike virtualization systems, the term 'host' here means + * the Linux side which is running remoteproc to control the remote + * processors. We use the name 'gfeatures' to comply with virtio's term= s, + * though there isn't really any virtualized guest OS here: it's the ho= st + * which is responsible for negotiating the final features. + * Yeah, it's a bit confusing. + * + * 2. immediately following this structure is the virtio config space for + * this vdev (which is specific to the vdev; for more info, read the vi= rtio + * spec). The size of the config space is specified by @config_len. + */ +struct fw_rsc_vdev { + u32 id; + u32 notifyid; + u32 dfeatures; + u32 gfeatures; + u32 config_len; + u8 status; + u8 num_of_vrings; + u8 reserved[2]; + struct fw_rsc_vdev_vring vring[]; +} __packed; + +#endif /* RSC_TABLE_H */ --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 420E22D2482 for ; Tue, 19 Aug 2025 16:55:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622553; cv=none; b=n89tffPfzoFCMzSdBtExLZtn9B8qZHdjt0rO3vPCJb1CrmFvHMGUw+6Mx9zGrMukqEW3yimvInjSnNqHU/5CmBnxu8/grWmMaBXtrsMb3cSURN9MVFlvuOvi5MI4MVmOTGbgpDmf+0y5p4HjtMBTKvtrpajS3u1jKAIj+eC+kpc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622553; c=relaxed/simple; bh=aH2ItPDzQjNcbMleRAVtTqLHHkrwA+xhSJpEApaXmmY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jrAS0wBZn8JCKY73CKvoxkeMp3kwHuqcDbCgPL0+Pn1SqVWdcwKSfTBrA96SL9wh599yHZ3d0IcI7771mI4wlrgZ5uP7OoTpT3IiwPHG52mlUoqtR7gKhlGVH0eZVToExSBiDbmO8wWU/XH1mlDZySvGXKePCEBAOB2o+xkVj5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=YdfZk5vy; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="YdfZk5vy" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90Z5m029804 for ; Tue, 19 Aug 2025 16:55:51 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=fwQg7CGB53q clpnRXzplcKXl+FhijNK1WRddU0YzXbs=; b=YdfZk5vyRD/5RT0fGOI+DZvnDcO abe3W8ro/+/fYfMpu9GD4DS9f5vExsaagwhxOqBNTQ7FsSRdsZ7c9IA9Ex2PHIHr b22EKfqZnBAs89w462r6u6Nn6BxlIpbbK5oFvfBccxgZHdtW9EkIpA84sNIHEC77 +zRpigjTbQLgnc7CBNXobSH2SyNtJgaHwTotmqHytYDWUccUqxxMW/b4fIowE2/h DFsEt9/X5cAcfcDJDf7CKakIlJIj+w5DbHkJHGrRHJ8DSIxHM0upFB16yeqF1GIP 7TIPYZj16QtVn4vRFEp6CpDlp6FqY84HHxFCeR16j+5ciDEfpHam8vsBnBA== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48jk5mh6ae-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:51 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2445803f0cfso58759135ad.1 for ; Tue, 19 Aug 2025 09:55:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622550; x=1756227350; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fwQg7CGB53qclpnRXzplcKXl+FhijNK1WRddU0YzXbs=; b=b+YRfWitcP6EHZjV8Y5CVbIlHp7btTusFJGvYTN/i4XnU39S1I7KrhGkH6Eijfv+7J CtsfMUZbaBLAyD54droiT3/gGOTbCTDNgVacQxGPljs5n1MPEXmJuek/Z/Ox0OdW5Hbf 4EoVKkXgfT8mqZD4lxaXf5wIW6vCS/PKjjuZkPdJMSL0rQFymSbTBxrqknxz9zI8o1eQ YLizC3L5PdOLLch2ZfaRVdq8qevjBNv6CXoN34IsYG1xr9f0g2RNj+j/mrv9lk8vMbNE mmYHHrCTMlq1iFH6spCxSg7+HBerm54jp6P0ZJKEE2BH6uQ2i23mysgHIkvVvmqvWXOw mirA== X-Forwarded-Encrypted: i=1; AJvYcCUpVzkA5YFlEwCwIY+nfalmNEqkjEAp+NuPZ+iDCfsap2Kh6gZZZA/tHfW5aWvLlG7tyBfhd13xwfLDQ6E=@vger.kernel.org X-Gm-Message-State: AOJu0YwfhCrhudjII/Te1PNsHd/cDrr3Q8OPPUmTGihXTtcpNT/9VnGG 8L5MWLCFf3K40loOiXsUUk8RGBWo84q++r5A9JAx09nIyCTl/iZnhbWM8Vsl1e/16B45HFA27Pw IrzBuw8MSxiP37EVAg/cqQ/XCljmWDpeFQ7vg8EejBcSGxHOUn+buUdd8SjH+mZ9bKno= X-Gm-Gg: ASbGnctbMjUt++8wp1IjzdgjNEgGwoz7maF5P87QMFT6ONxpEjfa5uPT/LGSrfI2LSn KsPd3Lv6vQ/Z1yVuMANAFZb8BlsvDYvxSRbcVIaBC9up+hmT+BplQ6NLrk3vTuAAGcQjhupK5Lf lvR7HEwMhOIeWZgY3ttXYJwzIsSM1HvQw8QljTtuF7EAy4T88W60Y8ieDLyiJ8dS8B0HZjpOdm8 idVHg7zgDddNZz2Y2J3AOLXj8i/OYOUN+fqWYuSRRLcjAqUPZrG16bRJwRm1mmyD39Fu5Re5T3o tmThc9h2OVkjzmS/nl999TRNG2nK7Oy5/Qvu3clcd7p8X9j223arh/uRz5LJ1rbnc4A= X-Received: by 2002:a17:902:cccf:b0:23f:cf96:3072 with SMTP id d9443c01a7336-245e0541d78mr41647755ad.26.1755622550244; Tue, 19 Aug 2025 09:55:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFHOfhh4kDIVCqOF/lgln17dW403C80shSMtreRS1SuNs3fddXQMYCMEL7XlPlGTIovsfgYyA== X-Received: by 2002:a17:902:cccf:b0:23f:cf96:3072 with SMTP id d9443c01a7336-245e0541d78mr41647415ad.26.1755622549726; Tue, 19 Aug 2025 09:55:49 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:49 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 07/11] firmware: qcom_scm: Add qcom_scm_pas_get_rsc_table() to get resource table Date: Tue, 19 Aug 2025 22:24:42 +0530 Message-ID: <20250819165447.4149674-8-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Sdn3duRu c=1 sm=1 tr=0 ts=68a4ac97 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=NnWisg9ZSMKnuRCoed8A:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: WB4tRtyNmd5KZHlW6OQj3J3gPUYn_a94 X-Proofpoint-GUID: WB4tRtyNmd5KZHlW6OQj3J3gPUYn_a94 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDA0MiBTYWx0ZWRfX138czUPRA5dN +wSq5P2VAm3c7lTVq1xAF62KudB1kMq4QwkhBw6Qj+kcP44dJ7ObHV13PYsn1qiyT2VAbTL6rpu iyrp8f+fmn23dN/6nDOq15BqHGRW/Jnpd/A9L1pxaEbA+20FimV5Q2MgGJTH2E0DUcxkB8axey7 rmLy3W6blwW6xAfuT5DB+ULVxVwHEto0NnEZhmMP+k7FmE1QhNFtG6L3Z6OOoHA1gi6Sc1tnj/r PeMPbUHLbvZnqX+0e+5n4wEy8EF9QQG63r9bXopAPbWAC1gtKDFReZpRo+MQvMkqSgQnENeOnS/ BA4y0TB1jWSWNsqQlb2x/5ZvjOEQ8C68CIVon9Irg1PZh1ffzYIzsi7MwaK09Hz9/yB1BSl70uf aL78tjQG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160042 Content-Type: text/plain; charset="utf-8" Qualcomm remote processor may rely on both static and dynamic resources for its functionality. Static resources typically refer to memory-mapped addresses required by the subsystem and are often embedded within the firmware binary and dynamic resources, such as shared memory in DDR etc., are determined at runtime during the boot process. On Qualcomm Technologies devices, it's possible that static resources are not embedded in the firmware binary and instead are provided by TrustZone However, dynamic resources are always expected to come from TrustZone. This indicates that for Qualcomm devices, all resources (static and dynamic) will be provided by TrustZone via the SMC call. Add qcom_scm_pas_get_rsc_table() SMC call which will return resource table including static and dynamic resource for a given PAS id in passed output buffer of output size. If the remote processor firmware binary does not include a resource table, the caller of this function should set input_rt as NULL and input_rt_size as zero respectively. If the firmware binary does contain static resources, they should be passed in input_rt. These will be forwarded to TrustZone for authentication. TrustZone will then append the dynamic resources and return the complete resource table in output_rt. More about documentation on resource table format can be found in include/linux/rsc_table.h Signed-off-by: Mukesh Ojha --- drivers/firmware/qcom/qcom_scm.c | 158 +++++++++++++++++++++++++ drivers/firmware/qcom/qcom_scm.h | 1 + include/linux/firmware/qcom/qcom_scm.h | 5 + 3 files changed, 164 insertions(+) diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_= scm.c index 301d440f62f3..1b45aafd6c05 100644 --- a/drivers/firmware/qcom/qcom_scm.c +++ b/drivers/firmware/qcom/qcom_scm.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include =20 @@ -111,6 +112,10 @@ enum qcom_scm_qseecom_tz_cmd_info { QSEECOM_TZ_CMD_INFO_VERSION =3D 3, }; =20 +enum qcom_scm_rsctable_resp_type { + RSCTABLE_BUFFER_NOT_SUFFICIENT =3D 20, +}; + #define QSEECOM_MAX_APP_NAME_SIZE 64 #define SHMBRIDGE_RESULT_NOTSUPP 4 =20 @@ -776,6 +781,159 @@ int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_= t addr, phys_addr_t size) } EXPORT_SYMBOL_GPL(qcom_scm_pas_mem_setup); =20 +static int __qcom_scm_pas_get_rsc_table(u32 peripheral, void *input_rt, + size_t input_rt_size, void **output_rt, + size_t *output_rt_size) +{ + struct qcom_scm_desc desc =3D { + .svc =3D QCOM_SCM_SVC_PIL, + .cmd =3D QCOM_SCM_PIL_PAS_GET_RSCTABLE, + .arginfo =3D QCOM_SCM_ARGS(5, QCOM_SCM_VAL, QCOM_SCM_RO, QCOM_SCM_VAL, + QCOM_SCM_RW, QCOM_SCM_VAL), + .args[0] =3D peripheral, + .owner =3D ARM_SMCCC_OWNER_SIP, + }; + void *input_rt_buf, *output_rt_buf; + struct resource_table *rsc; + struct qcom_scm_res res; + int ret; + + ret =3D qcom_scm_clk_enable(); + if (ret) + return ret; + + ret =3D qcom_scm_bw_enable(); + if (ret) + goto disable_clk; + + /* + * TrustZone can not accept buffer as NULL value as argument Hence, + * we need to pass a input buffer indicating that subsystem firmware + * does not have resource table by filling resource table structure. + */ + if (!input_rt) + input_rt_size =3D sizeof(*rsc); + + input_rt_buf =3D qcom_tzmem_alloc(__scm->mempool, input_rt_size, GFP_KERN= EL); + if (!input_rt_buf) { + ret =3D -ENOMEM; + goto disable_scm_bw; + } + + if (!input_rt) { + rsc =3D input_rt_buf; + rsc->num =3D 0; + } else { + memcpy(input_rt_buf, input_rt, input_rt_size); + } + + output_rt_buf =3D qcom_tzmem_alloc(__scm->mempool, *output_rt_size, GFP_K= ERNEL); + if (!output_rt_buf) { + ret =3D -ENOMEM; + goto free_input_rt_buf; + } + + desc.args[1] =3D qcom_tzmem_to_phys(input_rt_buf); + desc.args[2] =3D input_rt_size; + desc.args[3] =3D qcom_tzmem_to_phys(output_rt_buf); + desc.args[4] =3D *output_rt_size; + + /* + * Whether SMC fail or pass, res.result[2] will hold actual resource table + * size. + * + * if passed 'output_rt_size' buffer size is not sufficient to hold the + * resource table TrustZone sends, response code in res.result[1] as + * RSCTABLE_BUFFER_NOT_SUFFICIENT so that caller can retry this SMC call = with + * output_rt buffer with res.result[2] size. + */ + ret =3D qcom_scm_call(__scm->dev, &desc, &res); + *output_rt_size =3D res.result[2]; + if (!ret) + memcpy(*output_rt, output_rt_buf, *output_rt_size); + + if (ret && res.result[1] =3D=3D RSCTABLE_BUFFER_NOT_SUFFICIENT) + ret =3D -EAGAIN; + + qcom_tzmem_free(output_rt_buf); + +free_input_rt_buf: + qcom_tzmem_free(input_rt_buf); + +disable_scm_bw: + qcom_scm_bw_disable(); + +disable_clk: + qcom_scm_clk_disable(); + + return ret ? : res.result[0]; +} + +/** + * qcom_scm_pas_get_rsc_table() - Retrieve the resource table in passed ou= tput buffer + * for a given peripheral. + * + * Qualcomm remote processor may rely on both static and dynamic resources= for + * its functionality. Static resources typically refer to memory-mapped ad= dresses + * required by the subsystem and are often embedded within the firmware bi= nary + * and dynamic resources, such as shared memory in DDR etc., are determine= d at + * runtime during the boot process. + * + * On Qualcomm Technologies devices, it's possible that static resources a= re not + * embedded in the firmware binary and instead are provided by TrustZone H= owever, + * dynamic resources are always expected to come from TrustZone. This indi= cates + * that for Qualcomm devices, all resources (static and dynamic) will be p= rovided + * by TrustZone via the SMC call. + * + * If the remote processor firmware binary does contain static resources, = they + * should be passed in input_rt. These will be forwarded to TrustZone for + * authentication. TrustZone will then append the dynamic resources and re= turn + * the complete resource table in output_rt. + * + * If the remote processor firmware binary does not include a resource tab= le, + * the caller of this function should set input_rt as NULL and input_rt_si= ze + * as zero respectively. + * + * More about documentation on resource table data structures can be found= in + * include/linux/rsc_table.h + * + * @ctx: PAS context + * @peripheral: peripheral id + * @input_rt: resource table buffer which is present in firmware bin= ary + * @input_rt_size: size of the resource table present in firmware binary + * @output_rt: buffer to which the both static and dynamic resources w= ill + * be returned. + * @output_rt_size: TrustZone expects caller should pass worst case size f= or + * the output_rt. + * + * Return: 0 on success and nonzero on failure. + * + * Upon successful return, output_rt will have the resource table and outp= ut_rt_size + * will have actual resource table size, + */ +int qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_ctx *ctx, void *input_r= t, + size_t input_rt_size, void **output_rt, + size_t *output_rt_size) +{ + int ret; + + do { + *output_rt =3D devm_kzalloc(ctx->dev, *output_rt_size, GFP_KERNEL); + if (!*output_rt) + return -ENOMEM; + + ret =3D __qcom_scm_pas_get_rsc_table(ctx->peripheral, input_rt, + input_rt_size, output_rt, + output_rt_size); + if (ret) + devm_kfree(ctx->dev, *output_rt); + + } while (ret =3D=3D -EAGAIN); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_scm_pas_get_rsc_table); + /** * qcom_scm_pas_auth_and_reset() - Authenticate the given peripheral firmw= are * and reset the remote processor diff --git a/drivers/firmware/qcom/qcom_scm.h b/drivers/firmware/qcom/qcom_= scm.h index a56c8212cc0c..50d87c628d78 100644 --- a/drivers/firmware/qcom/qcom_scm.h +++ b/drivers/firmware/qcom/qcom_scm.h @@ -105,6 +105,7 @@ int qcom_scm_shm_bridge_enable(struct device *scm_dev); #define QCOM_SCM_PIL_PAS_SHUTDOWN 0x06 #define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07 #define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a +#define QCOM_SCM_PIL_PAS_GET_RSCTABLE 0x21 =20 #define QCOM_SCM_SVC_IO 0x05 #define QCOM_SCM_IO_READ 0x01 diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmwar= e/qcom/qcom_scm.h index bd3417d9c3f9..4fd13661ecdb 100644 --- a/include/linux/firmware/qcom/qcom_scm.h +++ b/include/linux/firmware/qcom/qcom_scm.h @@ -91,6 +91,11 @@ int qcom_scm_pas_init_image(u32 peripheral, const void *= metadata, size_t size, struct qcom_scm_pas_ctx *ctx); void qcom_scm_pas_metadata_release(struct qcom_scm_pas_ctx *ctx); int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t s= ize); + +int qcom_scm_pas_get_rsc_table(struct qcom_scm_pas_ctx *ctx, void *input_r= t, + size_t input_rt_size, void **output_rt, + size_t *output_rt_size); + int qcom_scm_pas_prepare_and_auth_reset(struct qcom_scm_pas_ctx *ctx); int qcom_scm_pas_auth_and_reset(u32 peripheral); int qcom_scm_pas_shutdown(u32 peripheral); --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2AB483009CE for ; Tue, 19 Aug 2025 16:55:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622557; cv=none; b=uYttrt8i4eqU3rHilL5Tl7yflKGJ0GlEAg5CUbcPBt31HPaSz/hpIifisveSPEb/mcMdjzAcy10SDt3cWeOEmYjK/O/VuNwQ1mnOArXw5rbgOVGW4GQ4qUGoDBiNl64QBTq1izGZog4X8O18/QN9635O/5uY+5sHqas3oOCFHuU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622557; c=relaxed/simple; bh=J8uls0Dvy/CcmQSkUDekOAYLdJXikPhNFgv4fD+sHnw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=SykFBDiqtb8TvdvHaOigdnG+mnxZ3ZevT1MdCUiNy0x0pGIggPZH/jy4wSpJoSSTRUmdtdLp+9eaNRMjF+kwbBADnwYFaIJILxDE5OY8tS0LokrQ5eo2ZViZbx5e1BMUPvLGXSPI6gB3pqIeCbJFlHU2MvpMvZKKYrZsh9+YD/w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=n/3ETA+U; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="n/3ETA+U" Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90a10029813 for ; Tue, 19 Aug 2025 16:55:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=BGxWt6ZCodU TWAKtq3VJEkSSPZxr5kmK9vduWMkjzjA=; b=n/3ETA+UJOA5Jtc/ZdghtEic/tG 6VZdktZyWtILDCepz4p1VsH3DQ8U6cvnTMpnhDRZR3N83b9+HlnLbdRF4pforI3H D5ugv8NoTnDiPLrwWUGp+wjOCEQxptGaVJDTiylifCKEyp7ERoQ+d1WzOMdZaVLC xCeHf92MXXFf2eiBVtSKg3rWzy2fyklv/+eCDCnMe1xAnZeOiQFmUM5OsJf24+Oc Xfrow6FUU/5ZmySYAlg4q9mnrDCZLCj373laV1kYUnI1LmUvVZgONrUqcJlppryq SUAOIdUKR9fY1C/D+Wc6SCQOCTo/bcRcFCbPC/7TsLG3tnI+Pl6rU90Wc6A== Received: from mail-pg1-f199.google.com (mail-pg1-f199.google.com [209.85.215.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48jk5mh6ap-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:55 +0000 (GMT) Received: by mail-pg1-f199.google.com with SMTP id 41be03b00d2f7-b47538030bfso1097697a12.1 for ; Tue, 19 Aug 2025 09:55:55 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622554; x=1756227354; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BGxWt6ZCodUTWAKtq3VJEkSSPZxr5kmK9vduWMkjzjA=; b=n5j+czlJeJxsWAkHQWw8lzDXGjDXDwk34WBDCBraivexl+pdbJsGbSEk0ovPF7j6ON lHyGIPqo8H4F6+UO3fyVs3GoyJQeEfwsayHTY6CKnOiJOvm4OqFIsZE09nXoIsBdmnbS 31AG+dQ2bCWrQBgjyke5mta+v8HjMrYwAp+/y4FUteLZQftKbKam3jrZmiEsMVlQNybB CY24T8R/T73WLasxyoeeHme/243EP+1aF4zWJXbVRiBMjt6JNGs5Kpv9OYiHo6lo3LBR b8Dpl5pRtrn1YrBEO16+sN0Bwl+qkhSPnsn5hqYchNCeECbRkyIIroOQkwknaoneKnGV hNag== X-Forwarded-Encrypted: i=1; AJvYcCVOtYfT084IEZHMos0Btw/HgJ6cHZHY1+CFmd7siBVjpoRC2NAqV8+B+JM/BjBVqVnfWPDYZBUbzArwrZg=@vger.kernel.org X-Gm-Message-State: AOJu0YzyQpgxdWXuTgmZmm9HSUeWfs6q7y2J1n/z7wXvn9uz5FKvOXcN 50euDLYlUHUao7zg69UCnYitE0oK2rn7gP6QPslK1O5FckFKRDWkhZE8O1MketJ8sJzJrIqsIaR aJOyL8Xkseytkjg+Y369xo4bHrqOYhei50gTzuBwefLdL7K5GxON4tTahl4bMGPPVdqw= X-Gm-Gg: ASbGncu9sA7MR269Wd6kJBK85/mOK9wTgz8peDFnNkCkrUbUCFS35ATxcA2mn5672W6 MpslMg4AJtyhWeP4lWGbqRZ/d1gFVTO17ItNTTPjQREnbIJH9EFA9ZaEpZINorxxdEMZ6T8BfSV zsXqVF+XhH+b679ecSYQkXf0aFWhywazEUpnIEqf+y1IgK/rX8tIWi240mfQEjQmZ39/GEXEVDw 9AbKvKEf8B9YYCwlz1wOBsii9tE433HaIUrZGQzDWSqC6vyg3kJdMipe1vtOyzxG1a207h36bLa 4966XLTGqY/xbuowgjVgs4Fog3HXEmOQ2RV5dJ1Bn53aEg6UJynPBrLHCOfRDYq8+v4= X-Received: by 2002:a17:903:4b4b:b0:243:43a:fa2b with SMTP id d9443c01a7336-245e05979d3mr45162985ad.56.1755622554394; Tue, 19 Aug 2025 09:55:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHCJvSyWdYCUdwdFkeuPmuHg/oB5uZt1WNslleqZHji6H0GkE4HG2Ih5XUKxUI8BqkFwEGWGQ== X-Received: by 2002:a17:903:4b4b:b0:243:43a:fa2b with SMTP id d9443c01a7336-245e05979d3mr45162595ad.56.1755622553832; Tue, 19 Aug 2025 09:55:53 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:53 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 08/11] soc: qcom: mdt_loader: Add helper functions to map and unmap resources Date: Tue, 19 Aug 2025 22:24:43 +0530 Message-ID: <20250819165447.4149674-9-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=Sdn3duRu c=1 sm=1 tr=0 ts=68a4ac9b cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=uXk6sN4QHJxknyAWzbwA:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-ORIG-GUID: ZbO-Ws2b6Wkq8Ii67PnB6uqyQ5aDU22Q X-Proofpoint-GUID: ZbO-Ws2b6Wkq8Ii67PnB6uqyQ5aDU22Q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDA0MiBTYWx0ZWRfX7k+gIszrU9+f xvZCLCYfWb6UQ+W9WBTn0kp4RKhinFsds4026ZtYixNnelW3tIAqWcBbJ9VoCSPXw8Qr2wl3rh0 gxSKyF+7xWcQsYppRdJV41756nfKZ1j5QrvGFaqS/fOpN5Thif1Q6I6CIyy0qimFW9FizLE9xQg eITI+LyXaDiG0bNTA6cAn9cZ82iJUI9NVgeBueIUQqD1IGM7mg98fc9T0YPzxNWpxNmVNkKWPIl da5/+TQEZeYZmpcwvH/vuWEa57fgroJeYowzofKkqy86bfYJtovafFGv6jP/v7tfG5aD/rZK9Lo ocrYOpouFwrmGsv01PybKm2OlxDfNUZLZ9XO9XTsuMdJo+xxwigkFqhJSFzt1SB+TwibaebQGex GUhiXZm+ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 spamscore=0 adultscore=0 malwarescore=0 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160042 Content-Type: text/plain; charset="utf-8" Most Qualcomm platforms feature a proprietary hypervisor (Gunyah, QHEE), which normally takes care of the IOMMU configuration for remote processors by intercepting qcom_scm_pas_auth_and_reset() calls. When the aforementioned hypervisor is absent, the OS must perform the configuration instead. To do so, it must first retrieve a resource table from the secure world, to ensure the settings are in sync with TZ's expectations and then it should map the resources before it calls qcom_scm_pas_auth_and_reset(). Add helper function to IOMMU map and unmap devmem resources for a given remote processor. Signed-off-by: Mukesh Ojha --- drivers/soc/qcom/mdt_loader.c | 174 ++++++++++++++++++++++++++++ include/linux/soc/qcom/mdt_loader.h | 17 +++ 2 files changed, 191 insertions(+) diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index a1718db91b3e..ea7034c4b996 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -11,13 +11,34 @@ #include #include #include +#include #include +#include +#include #include #include +#include #include #include #include =20 +#define MAX_RSCTABLE_SIZE SZ_16K +#define RSC_TABLE_HASH_BITS 5 // 32 buckets + +DEFINE_HASHTABLE(qcom_pas_rsc_table_map, RSC_TABLE_HASH_BITS); + +struct qcom_pas_devmem_rsc { + struct fw_rsc_devmem *devmem; + struct list_head node; +}; + +struct qcom_pas_rsc_table_info { + struct resource_table *rsc_table; + struct list_head devmem_list; + struct hlist_node hnode; + int pas_id; +}; + static bool mdt_header_valid(const struct firmware *fw) { const struct elf32_hdr *ehdr; @@ -500,5 +521,158 @@ int qcom_mdt_pas_load(struct qcom_scm_pas_ctx *ctx, c= onst struct firmware *fw, } EXPORT_SYMBOL_GPL(qcom_mdt_pas_load); =20 +static void __qcom_mdt_unmap_devmem_rscs(struct qcom_pas_rsc_table_info *i= nfo, + struct iommu_domain *domain) +{ + struct qcom_pas_devmem_rsc *entry, *tmp; + + list_for_each_entry_safe(entry, tmp, &info->devmem_list, node) { + iommu_unmap(domain, entry->devmem->da, entry->devmem->len); + list_del(&entry->node); + kfree(entry); + } +} + +void qcom_mdt_pas_unmap_devmem_rscs(struct qcom_scm_pas_ctx *ctx, struct i= ommu_domain *domain) +{ + struct qcom_pas_rsc_table_info *info; + + if (!ctx || !domain) + return; + + if (!ctx->has_iommu) + return; + + hash_for_each_possible(qcom_pas_rsc_table_map, info, hnode, ctx->peripher= al) { + if (info->pas_id =3D=3D ctx->peripheral) + __qcom_mdt_unmap_devmem_rscs(info, domain); + + hash_del(&info->hnode); + kfree(info->rsc_table); + } + + return; +} +EXPORT_SYMBOL_GPL(qcom_mdt_pas_unmap_devmem_rscs); + +static int __qcom_mdt_map_devmem_rscs(struct device *dev, void *ptr, int a= vail, + struct iommu_domain *domain, + struct qcom_pas_rsc_table_info *info) +{ + struct qcom_pas_devmem_rsc *devmem_info; + struct fw_rsc_devmem *rsc =3D ptr; + int ret; + + if (sizeof(*rsc) > avail) { + dev_err(dev, "devmem rsc is truncated\n"); + return -EINVAL; + } + + if (rsc->reserved) { + dev_err(dev, "devmem rsc has non zero reserved bytes\n"); + return -EINVAL; + } + + devmem_info =3D kzalloc(sizeof(*devmem_info), GFP_KERNEL); + if (!devmem_info) + return -ENOMEM; + + ret =3D iommu_map(domain, rsc->da, rsc->pa, rsc->len, rsc->flags, GFP_KER= NEL); + if (ret) { + dev_err(dev, "failed to map devmem: %d\n", ret); + kfree(devmem_info); + return ret; + } + + devmem_info->devmem =3D rsc; + list_add_tail(&devmem_info->node, &info->devmem_list); + + dev_dbg(dev, "mapped devmem pa 0x%x, da 0x%x, len 0x%x\n", + rsc->pa, rsc->da, rsc->len); + + return ret; +} + +/** + * qcom_mdt_pas_map_devmem_rscs() - IOMMU map device memory resources for + * a given Peripheral + * + * This routine should be called when it is known that the SoC is running + * with Linux as hypervisor at EL2 where it is in control of the IOMMU map + * of the resources for the remote processors. + * + * @ctx: pas context data structure + * @domain: IOMMU domain + * @input_rt: input resource table buffer when resource table is part = of firmware + * binary, if not, pass NULL + * @input_rt_size: input resource table size, if input_rt is NULL, then p= ass zero. + * + * Returns 0 on success, negative errno otherwise. + * + */ +int qcom_mdt_pas_map_devmem_rscs(struct qcom_scm_pas_ctx *ctx, struct iomm= u_domain *domain, + void *input_rt, size_t input_rt_size) +{ + size_t output_rt_size =3D MAX_RSCTABLE_SIZE; + struct resource_table *rsc_table; + struct qcom_pas_rsc_table_info *info; + void *output_rt; + int ret; + int i; + + if (!ctx || !domain) + return -EINVAL; + + if (!ctx->has_iommu) + return 0; + + ret =3D qcom_scm_pas_get_rsc_table(ctx, input_rt, input_rt_size, &output_= rt, + &output_rt_size); + if (ret) { + dev_err(ctx->dev, "error %d getting resource_table\n", ret); + return ret; + } + + rsc_table =3D output_rt; + info =3D devm_kzalloc(ctx->dev, sizeof(*info), GFP_KERNEL); + if (!info) + goto free_output_rt; + + info->pas_id =3D ctx->peripheral; + info->rsc_table =3D output_rt; + INIT_LIST_HEAD(&info->devmem_list); + for (i =3D 0; i < rsc_table->num; i++) { + int offset =3D rsc_table->offset[i]; + struct fw_rsc_hdr *hdr =3D (void *)rsc_table + offset; + int avail =3D output_rt_size - offset - sizeof(*hdr); + void *ptr =3D (void *)hdr + sizeof(*hdr); + + if (avail < 0) { + dev_err(ctx->dev, "rsc table is truncated\n"); + ret =3D -EINVAL; + goto undo_mapping; + } + + if (hdr->type =3D=3D RSC_DEVMEM) { + ret =3D __qcom_mdt_map_devmem_rscs(ctx->dev, ptr, avail, domain, info); + if (ret) + goto undo_mapping; + } + } + + hash_add(qcom_pas_rsc_table_map, &info->hnode, ctx->peripheral); + + return 0; + +undo_mapping: + __qcom_mdt_unmap_devmem_rscs(info, domain); + +free_output_rt: + devm_kfree(ctx->dev, info->rsc_table); + + return ret; +} +EXPORT_SYMBOL_GPL(qcom_mdt_pas_map_devmem_rscs); + MODULE_DESCRIPTION("Firmware parser for Qualcomm MDT format"); MODULE_LICENSE("GPL v2"); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/m= dt_loader.h index 450fa0be2af0..62f239f64dfb 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -11,6 +11,8 @@ struct device; struct firmware; struct qcom_scm_pas_ctx; +struct resource_table; +struct iommu_domain; =20 #if IS_ENABLED(CONFIG_QCOM_MDT_LOADER) =20 @@ -31,6 +33,11 @@ int qcom_mdt_load_no_init(struct device *dev, const stru= ct firmware *fw, void *qcom_mdt_read_metadata(const struct firmware *fw, size_t *data_len, const char *fw_name, struct device *dev); =20 +int qcom_mdt_pas_map_devmem_rscs(struct qcom_scm_pas_ctx *ctx, struct iomm= u_domain *domain, + void *rsc_table, size_t rsc_size); + +void qcom_mdt_pas_unmap_devmem_rscs(struct qcom_scm_pas_ctx *ctx, struct i= ommu_domain *domain); + #else /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ =20 static inline ssize_t qcom_mdt_get_size(const struct firmware *fw) @@ -68,6 +75,16 @@ static inline void *qcom_mdt_read_metadata(const struct = firmware *fw, return ERR_PTR(-ENODEV); } =20 +static inline int qcom_mdt_pas_map_devmem_rscs(struct device *dev, bool ha= s_iommu, + struct iommu_domain *domain, int pas_id, + phys_addr_t rsc_table, size_t rsc_size) +{ + return -ENODEV; +} + +void qcom_mdt_pas_unmap_devmem_rscs(bool has_iommu, int pas_id, struct iom= mu_domain *domain) +{ +} #endif /* !IS_ENABLED(CONFIG_QCOM_MDT_LOADER) */ =20 #endif --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24CF33043BF for ; Tue, 19 Aug 2025 16:55:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622561; cv=none; b=Vn7kSgTXzqB5BGZG+E7kY9v1CBvABqT4N6eMjnAvhrUx83BSr0xgEVY4XrRhwRfkCIG0T60fvHYWP1CFXBeb0ePW+loRXTSouotgD0F+Er4g2XIkOWNSiHQdjYETeYgB/R9hzEo9DE/nbtnxaaygMzxg8E3Nkgacv4e/vjBCw4A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622561; c=relaxed/simple; bh=B3HXZFYsID/A0xupa0b1H+gHN5gYfsep6vwGMULf79o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jTA7SjsdE45uENW1BeWti/ffzTobXv7rD2Vxj6WJlGDJ9+XOi2nG78EVyEFi+Cu1PZlYyoJ6PXZ3uIgLYqjTNhn8YYnnFiwSpUi3l7b+5qoL8yVmNXMPh1juBr5GNKx1kX0pHXJi4HWu5Zsw4j10o2uGI6CBJeKvoak1pc1UG18= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=VE1Qs8+X; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="VE1Qs8+X" Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90i4L007348 for ; Tue, 19 Aug 2025 16:55:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=dxpDpl+fh+T OdTRIITvI5AH6/tTOz6Po0lG2zRNlW+U=; b=VE1Qs8+X6VdZ602twN1edfphoHF haA+PyWGPORACpVbxXU69rFil2mZ8MNpl7UIBhNviKgm5zu8oM9LSoj0hBH2ioPS 9C68ox/fJMQY8biIEzbGF3SW3QCF5hVNMW2DumjIHXG/OcSoNiR6ZxNRTdSyLvXh GCAciD1l90t4Cjsvl9YlVX8AkqOzr2XVb63KodVa/Aebca//MVoqUenalu43P1Sa Bu2TWgNz+AN7ciiDNUWJm0h1d1YFokgGUlpk4Vhob03NO4EQEcPrx3BNhvex+dK8 c2ySD1NX8QSwZNpS4/gIdVnrVtPTo9Yotb8eeXVTL4aQmse7KLz3hZXWxdQ== Received: from mail-pl1-f200.google.com (mail-pl1-f200.google.com [209.85.214.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48jj749cyu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:55:59 +0000 (GMT) Received: by mail-pl1-f200.google.com with SMTP id d9443c01a7336-24458264c5aso58486665ad.3 for ; Tue, 19 Aug 2025 09:55:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622558; x=1756227358; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dxpDpl+fh+TOdTRIITvI5AH6/tTOz6Po0lG2zRNlW+U=; b=GWs+tv0Hezxu3NsOADcn7n74KFoHOYbY0jv5nIcToAyAJO0Az+v/Pdo86gXcIN0NrD +XB46ChA6D/MECDqJ3CKrmAHjXfKvDMArncmNyjOBiQyAWJm5HmglZOmg8jcNvEz79uI X3M4O/dHvi8ocwamClVe1jodojNBJDO8IZSlwZPAC9EGnLd9gBp7AOsdBwm+GLu4B6zA 3HedC511IwrzXlzM5+Kjyu4PhMPMxsJs8rmgM6lBErM4qKh8+HXBFvH4utJ59Ey4Evqs 5qd/WuUSdzqJ1fw4mzjOi6UfbBdFZbcm4wPZGmt3cYCvhzrA2TS2wfPDGh1usnADUk95 ounw== X-Forwarded-Encrypted: i=1; AJvYcCUQRd3a6zcQk5/BPrFO3oqmfuMtwUhcqdc0Vi1KV9NIO3Fm8Sp6S6NVTwsewT725AWTFRE6L4JiiFkMNI4=@vger.kernel.org X-Gm-Message-State: AOJu0YycJHykDcIDu4ZV45HMJlF68SwEmYvVxxYdHTUr+yo/sbw71r5o mLr6OVSt5L2NDHJt9naCgIM6o+Me3qwBMnVoMfIv3Zvu/E9gKuOU7TDn5n8989FKmp8W1OJX89Q vG1cha+GxrtZtu+ERah/DVJPIuEWO4T3jNeFwiZAvuhrrn9bWX1wky/y9lGe5JN0VbtU= X-Gm-Gg: ASbGnct01h/uV5G8D4H+xeeX7ZWpHzuxSuFtF/ONUjhz9n1IHgc/WdV1DufGfDnigjH Q7iqJ9T6e7Cyq1f8pM/Muywt+Rnj2hAWxdc+niPItaDgAbDH1Evhhv1/v+DxJPG33juHQ/z0iR9 GQj9gVQaX/sx7bHEq9fYRmveV6lghEOheroIPMZtTLd5KymBqgCMOEzRkb+jqhupxv9mbGL5kRt r9jZ3RyQ1YqfX1247RR6Oa2gkpmTY7jiSMO8majZLig1/xY4e7RmZ0MX5piqrejEBAA8OpvL56y GKfHnefnB6/b6Jc+PHgJbMpds30hD8VDrM7ZEchTpOa7Od/WBfU7pVF99BVRuaMXi94= X-Received: by 2002:a17:903:298d:b0:23f:f065:f2be with SMTP id d9443c01a7336-245e0484ab0mr38524255ad.26.1755622558378; Tue, 19 Aug 2025 09:55:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEeiSCkw7ouQ0AQ0r5FwfI9TjfvBzcDTXckjTR+IZ8Q5OuI924lLyvlvwXZh5sjHkfU7/illQ== X-Received: by 2002:a17:903:298d:b0:23f:f065:f2be with SMTP id d9443c01a7336-245e0484ab0mr38523985ad.26.1755622557923; Tue, 19 Aug 2025 09:55:57 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:55:57 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 09/11] remoteproc: pas: Extend parse_fw callback to parse resource table Date: Tue, 19 Aug 2025 22:24:44 +0530 Message-ID: <20250819165447.4149674-10-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: joz9dZxAKd3MK8V7OeLyOmQigDFwh1XS X-Proofpoint-ORIG-GUID: joz9dZxAKd3MK8V7OeLyOmQigDFwh1XS X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE2MDAzMyBTYWx0ZWRfX2jiuTMNEhfGs JQhXQ/7P0FJ3h5/6FfK/3Oubx+kf8Kgoc2NZt+N2oOPr31TkIzY9n2Ny/O+VOuhvrQF6Xuyi4zJ EOvJCUmez9tn3OlaqkmBBPD5kNEZdEWEIy1RaXdEryI/ywR4qQENys+MGgqmv1gqzQAzeJG97ot tKtUzs2uF18BbuRUTIfFZwA9WR8zwWsjo8Zi5AsTLuwbbyZjNixwFNB1y1OTebIHPYeMXJhSsCy 0ow4E9pZXQqhH4a9uebWLqGQNxXqCMbs/PzftIGPNR3oKOHEOmu1GwC6CNHt2eRZxD1zxkYOYDc 6sM2C9n7v1VZX5H1eIPWufax3saCBf9M6MGggwuHkGHGNt4AZH7UX1Y5qJWQYymNrHE+SJanx5y e0IPz/JY X-Authority-Analysis: v=2.4 cv=MJtgmNZl c=1 sm=1 tr=0 ts=68a4ac9f cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=PrD8l-S5Z6VY88wQs4gA:9 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 bulkscore=0 adultscore=0 suspectscore=0 phishscore=0 clxscore=1015 impostorscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508160033 Content-Type: text/plain; charset="utf-8" Extend parse_fw callback to include SMC call to get resource table from TrustZone to leverage resource table parse and mapping and unmapping code reuse from the framework. Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 33 +++++++++++++++++++++++++++-- drivers/soc/qcom/mdt_loader.c | 1 - include/linux/soc/qcom/mdt_loader.h | 2 ++ 3 files changed, 33 insertions(+), 3 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index 09cada92dfd5..1e0f09bf1ef2 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -408,6 +408,35 @@ static void *qcom_pas_da_to_va(struct rproc *rproc, u6= 4 da, size_t len, bool *is return pas->mem_region + offset; } =20 +static int qcom_pas_parse_firmware(struct rproc *rproc, const struct firmw= are *fw) +{ + struct qcom_pas *pas =3D rproc->priv; + size_t output_rt_size =3D MAX_RSCTABLE_SIZE; + void *output_rt; + int ret; + + ret =3D qcom_register_dump_segments(rproc, fw); + if (ret) { + dev_err(pas->dev, "Error in registering dump segments\n"); + return ret; + } + + if (!rproc->has_iommu) + return ret; + + ret =3D qcom_scm_pas_get_rsc_table(pas->pas_id, NULL, 0, &output_rt, &out= put_rt_size); + if (ret) { + dev_err(pas->dev, "error %d getting resource_table\n", ret); + return ret; + } + + rproc->cached_table =3D output_rt; + rproc->table_ptr =3D rproc->cached_table; + rproc->table_sz =3D output_rt_size; + + return ret; +} + static unsigned long qcom_pas_panic(struct rproc *rproc) { struct qcom_pas *pas =3D rproc->priv; @@ -420,7 +449,7 @@ static const struct rproc_ops qcom_pas_ops =3D { .start =3D qcom_pas_start, .stop =3D qcom_pas_stop, .da_to_va =3D qcom_pas_da_to_va, - .parse_fw =3D qcom_register_dump_segments, + .parse_fw =3D qcom_pas_parse_firmware, .load =3D qcom_pas_load, .panic =3D qcom_pas_panic, }; @@ -430,7 +459,7 @@ static const struct rproc_ops qcom_pas_minidump_ops =3D= { .start =3D qcom_pas_start, .stop =3D qcom_pas_stop, .da_to_va =3D qcom_pas_da_to_va, - .parse_fw =3D qcom_register_dump_segments, + .parse_fw =3D qcom_pas_parse_firmware, .load =3D qcom_pas_load, .panic =3D qcom_pas_panic, .coredump =3D qcom_pas_minidump, diff --git a/drivers/soc/qcom/mdt_loader.c b/drivers/soc/qcom/mdt_loader.c index ea7034c4b996..8456cca3f3e0 100644 --- a/drivers/soc/qcom/mdt_loader.c +++ b/drivers/soc/qcom/mdt_loader.c @@ -22,7 +22,6 @@ #include #include =20 -#define MAX_RSCTABLE_SIZE SZ_16K; #define RSC_TABLE_HASH_BITS 5 // 32 buckets =20 DEFINE_HASHTABLE(qcom_pas_rsc_table_map, RSC_TABLE_HASH_BITS); diff --git a/include/linux/soc/qcom/mdt_loader.h b/include/linux/soc/qcom/m= dt_loader.h index 62f239f64dfb..92ad862e733e 100644 --- a/include/linux/soc/qcom/mdt_loader.h +++ b/include/linux/soc/qcom/mdt_loader.h @@ -8,6 +8,8 @@ #define QCOM_MDT_TYPE_HASH (2 << 24) #define QCOM_MDT_RELOCATABLE BIT(27) =20 +#define MAX_RSCTABLE_SIZE SZ_16K + struct device; struct firmware; struct qcom_scm_pas_ctx; --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A4102D24BB for ; Tue, 19 Aug 2025 16:56:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622565; cv=none; b=NQpfyB4n8dCpEw1A8encu3b9OGhVlCj0V02ZMLedeRsu5ibDhcvCKoPtMwPzFneUnb2VdMgZKWdejNOeuqGNsy0PblyjrLk//tXCyj0C8pLYpfmXVif5pG3ggtHF63CB4WzRe2/iHDDvkIfu5qmlgLnUx2wg3al/Cv98nKV3MfU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622565; c=relaxed/simple; bh=Zc7+4/Z4XXaktbT2Lj7+7GuvFjOCS7TRGcWb2kd9DCE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qBcmh+Pq3ZJkF7RvrnHSoXfMP0Ch4BJus2BNxTPGUEbiQt3g+QVx5LB5g8mbhTZMrUpxvwONby+Gge/9EKSQ4pf8PxTY5BmlL/sypG5BhNs4vkghMcLITQbie5FQwdK95UTtjl2kTn2AxQK19XFEULknAYpxo4TtQjyrsJomHag= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=PtN7QPdF; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="PtN7QPdF" Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57JGiFP1023047 for ; Tue, 19 Aug 2025 16:56:03 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=7TQCNmijRE9 VS3dO0cEngmYEHlTvYCRhw6o+g4o3fCo=; b=PtN7QPdFvYCJJ9iXRc5gaT+8PwE DC6REKCdsle28yGZSmwt3oHX/3BAOaUzgJfSlzvoSHeM5fuK/xEqDM65Ae/ysP7P bMzwzTPs5KHRYxCwkOtDL7Ep/Yrej+rTnrRH1jkz9AoqT6v1itykSljuOI267Bmw s7y4GUuYzdwJKv2fXXeYfs1X0nSdnUOhXE7LsedmvAv6NNwqFvQv6E6MzhTVpjDw CDifGgtNof5w4bod+bKyldy4notNfLZtAqbf9K/nUwME8vTjB9Mp8UPGNW7RMWo6 G3VUyN3GvMK7mG+eoM5jsox6GAqkB0BR2tQCWrC9debMTa+hhOALNQKFV5A== Received: from mail-pl1-f199.google.com (mail-pl1-f199.google.com [209.85.214.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48mca5k1m9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:56:03 +0000 (GMT) Received: by mail-pl1-f199.google.com with SMTP id d9443c01a7336-24457f59889so58911865ad.0 for ; Tue, 19 Aug 2025 09:56:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622562; x=1756227362; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7TQCNmijRE9VS3dO0cEngmYEHlTvYCRhw6o+g4o3fCo=; b=vX2q9xQwSydM+fK0+eZJbn4vW87jAg6HAnDIEER2ymOkyr3cJKOk3v5yzeiV0cDWpI PNiRtbQ1xShffU1njoyd4oI+grHALRpwH9IV+SfiDh3akFAU/OQuSl7Qowm4dpT6xPs1 PJtCoq56GIXEd/QfYpjGRQkcXAu0rbUKb7dIGV43zj3pcPzxqMCBhOTrgQOV4jO3S45H KSuQ2x8Al6qCU2RYhV0JT2/obyMPp7f9rxsRr43Y9fLU8DXtBZ8QWX9rjcEOmRgcpsJH OMMkqawZEXPdtqJiH/L+hl6PTR07X+5CB4Yy1iDxb+KtGHQ5WZU+WZgC1zHcQydU3ahj HuTA== X-Forwarded-Encrypted: i=1; AJvYcCW9WcSQMfOWzLmvRddiCpPetY+3gCZdbEWiTZ89rAtAlHFhGQyDp3t9iEIW/YeeTUVFVkXweyBkfeyzjxM=@vger.kernel.org X-Gm-Message-State: AOJu0YyzZ2+VkyUZeIf4vPNlYOTa6fuqX7hNgVhRuD1jBkfo0zW15wSR +wYTylZcrWJKyyPsCDEZJ+0ga5DDhusGRuQrmpnVQDV04E7V8CvwinXgSZqlsdSo7+EgBNNKRTZ U7hUfV1NKLjUaFehbdn10qGerIywNzGz8h3q48DpdK2oZFX6+R1mt++sva7UxvQZ7iRs= X-Gm-Gg: ASbGncvNwb7TwN+6/2JUyvh7FmFud4wsqHisJcOXkEFay04ka9Gn6W3xDRKkoX0e5HC cS6psvkZosB9ndr3mCS6XI4nkXuEpH13Ny3/cm7oQ2ksuVUTpbWbvfRRWqOEjVHqKus1Ox2y8EZ W3fTP0//t7e259Z6xHEtnOBg+B3HFvhgybroLKakcF/MoAwDMi0wEY7itA3uQcbXKWCtIOU51ID KxV3xIsaUO1XXGmkw6KjVat5xZRy5ZEmA4VwsitINp5ipBzvIJ9CMeGLBKmYZ/a1FPA/vRaLE78 eU0EODVzc23O3e3Q2DlpZGWAHseMzRipn2su4Wtdpb20F/mwb66f1lAMuCU+A29Kz3k= X-Received: by 2002:a17:902:e80a:b0:242:2cad:2f8 with SMTP id d9443c01a7336-245e030786dmr50925085ad.22.1755622562527; Tue, 19 Aug 2025 09:56:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGZhIm1RfeHftaTXr4FFqQ6mdKSfUgMY7hKB3MMlwRM9W570Zfi/DtPRME7Cf9owHlZ1VkQyg== X-Received: by 2002:a17:902:e80a:b0:242:2cad:2f8 with SMTP id d9443c01a7336-245e030786dmr50924715ad.22.1755622562030; Tue, 19 Aug 2025 09:56:02 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.55.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:56:01 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 10/11] remoteproc: qcom: pas: Enable Secure PAS support with IOMMU managed by Linux Date: Tue, 19 Aug 2025 22:24:45 +0530 Message-ID: <20250819165447.4149674-11-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=FdU3xI+6 c=1 sm=1 tr=0 ts=68a4aca3 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=aSAcVJyT6VmtggMVTjAA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: 0Tuv5Jbs9eV7kdJQOoiRAzDx5ncIsf-H X-Proofpoint-GUID: 0Tuv5Jbs9eV7kdJQOoiRAzDx5ncIsf-H X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE4MDIwMiBTYWx0ZWRfXyKY7Z69Ti+Sc z5o7BbGSoj22rnw5SpgCmy3FVY3O8IdB+xErfXPFClNeL6K115SIyl77T8DZC8QyyWijBsUjYKE GVYevpSJNsmjAhJi7U3xRmKZit65n7Y76KrAuvDk4GEgNZ4abWb41OvEyHXHgtQ296FX2D+quXW XZDrfk9s/vwG/isMUbho9KegYrqxHDlRQwkmo8zjKJAeYzfkouXW/fQ4gYAsnF9sp5oPUxwZZ+1 LDLlqRES9Hg0ZzDqUvUo/3u+FqRjn3Ra4HcgCLnR1KmB1hqv7abA+F+z9ugXxU0plQJQv5lzV7f 3icGb+gYuyQ+WU8rqxqHuiu8Egv7WJVklBWGuxAgSkw+v7t2CMKcATo06JYyw91kr3+txiwTcii G0ujCMLO X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 phishscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508180202 Content-Type: text/plain; charset="utf-8" Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah or QHEE), which typically handles IOMMU configuration. This includes mapping memory regions and device memory resources for remote processors by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are later removed during teardown. Additionally, SHM bridge setup is required to enable memory protection for both remoteproc metadata and its memory regions. When the aforementioned hypervisor is absent, the operating system must perform these configurations instead. When Linux runs as the hypervisor (at EL2) on a SoC, it will have its own device tree overlay file that specifies the firmware stream ID now managed by Linux for a particular remote processor. If the iommus property is specified in the remoteproc device tree node, it indicates that IOMMU configuration must be handled by Linux. In this case, the has_iommu flag is set for the remote processor, which ensures that the resource table, carveouts, and SHM bridge are properly configured before memory is passed to TrustZone for authentication. Otherwise, the has_iommu flag remains unset, which is the default behavior. Enables Secure PAS support for remote processors when IOMMU configuration is managed by Linux. Signed-off-by: Mukesh Ojha --- drivers/remoteproc/qcom_q6v5_pas.c | 63 +++++++++++++++++++++++++++--- 1 file changed, 57 insertions(+), 6 deletions(-) diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q= 6v5_pas.c index 1e0f09bf1ef2..180528bcd57c 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -250,6 +251,22 @@ static int qcom_pas_load(struct rproc *rproc, const st= ruct firmware *fw) return ret; } =20 +static void qcom_pas_unmap_carveout(struct rproc *rproc, phys_addr_t mem_p= hys, size_t size) +{ + if (rproc->has_iommu) + iommu_unmap(rproc->domain, mem_phys, size); +} + +static int qcom_pas_map_carveout(struct rproc *rproc, phys_addr_t mem_phys= , size_t size) +{ + int ret =3D 0; + + if (rproc->has_iommu) + ret =3D iommu_map(rproc->domain, mem_phys, mem_phys, size, + IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); + return ret; +} + static int qcom_pas_start(struct rproc *rproc) { struct qcom_pas *pas =3D rproc->priv; @@ -284,11 +301,15 @@ static int qcom_pas_start(struct rproc *rproc) } =20 if (pas->dtb_pas_id) { - ret =3D qcom_scm_pas_auth_and_reset(pas->dtb_pas_id); + ret =3D qcom_pas_map_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_siz= e); + if (ret) + goto disable_px_supply; + + ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->dtb_pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate dtb image and release reset\n"); - goto disable_px_supply; + goto unmap_dtb_carveout; } } =20 @@ -299,18 +320,22 @@ static int qcom_pas_start(struct rproc *rproc) =20 qcom_pil_info_store(pas->info_name, pas->mem_phys, pas->mem_size); =20 - ret =3D qcom_scm_pas_auth_and_reset(pas->pas_id); + ret =3D qcom_pas_map_carveout(rproc, pas->mem_phys, pas->mem_size); + if (ret) + goto release_pas_metadata; + + ret =3D qcom_scm_pas_prepare_and_auth_reset(pas->pas_ctx); if (ret) { dev_err(pas->dev, "failed to authenticate image and release reset\n"); - goto release_pas_metadata; + goto unmap_carveout; } =20 ret =3D qcom_q6v5_wait_for_start(&pas->q6v5, msecs_to_jiffies(5000)); if (ret =3D=3D -ETIMEDOUT) { dev_err(pas->dev, "start timed out\n"); qcom_scm_pas_shutdown(pas->pas_id); - goto release_pas_metadata; + goto unmap_carveout; } =20 qcom_scm_pas_metadata_release(pas->pas_ctx); @@ -322,10 +347,16 @@ static int qcom_pas_start(struct rproc *rproc) =20 return 0; =20 +unmap_carveout: + qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); release_pas_metadata: qcom_scm_pas_metadata_release(pas->pas_ctx); if (pas->dtb_pas_id) qcom_scm_pas_metadata_release(pas->dtb_pas_ctx); + +unmap_dtb_carveout: + if (pas->dtb_pas_id) + qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size); disable_px_supply: if (pas->px_supply) regulator_disable(pas->px_supply); @@ -381,8 +412,12 @@ static int qcom_pas_stop(struct rproc *rproc) ret =3D qcom_scm_pas_shutdown(pas->dtb_pas_id); if (ret) dev_err(pas->dev, "failed to shutdown dtb: %d\n", ret); + + qcom_pas_unmap_carveout(rproc, pas->dtb_mem_phys, pas->dtb_mem_size); } =20 + qcom_pas_unmap_carveout(rproc, pas->mem_phys, pas->mem_size); + handover =3D qcom_q6v5_unprepare(&pas->q6v5); if (handover) qcom_pas_handover(&pas->q6v5); @@ -424,7 +459,8 @@ static int qcom_pas_parse_firmware(struct rproc *rproc,= const struct firmware *f if (!rproc->has_iommu) return ret; =20 - ret =3D qcom_scm_pas_get_rsc_table(pas->pas_id, NULL, 0, &output_rt, &out= put_rt_size); + ret =3D qcom_scm_pas_get_rsc_table(pas->pas_ctx, NULL, 0, + &output_rt, &output_rt_size); if (ret) { dev_err(pas->dev, "error %d getting resource_table\n", ret); return ret; @@ -726,6 +762,20 @@ static int qcom_pas_probe(struct platform_device *pdev) return -ENOMEM; } =20 + if (of_property_present(pdev->dev.of_node, "iommus")) { + struct of_phandle_args args; + + ret =3D of_parse_phandle_with_args(pdev->dev.of_node, "iommus", + "#iommu-cells", 0, &args); + if (ret < 0) + return ret; + + rproc->has_iommu =3D true; + of_node_put(args.np); + } else { + rproc->has_iommu =3D false; + } + rproc->auto_boot =3D desc->auto_boot; rproc_coredump_set_elf_info(rproc, ELFCLASS32, EM_NONE); =20 @@ -800,6 +850,7 @@ static int qcom_pas_probe(struct platform_device *pdev) if (!pas->dtb_pas_ctx) goto remove_ssr_sysmon; =20 + pas->pas_ctx->has_iommu =3D pas->dtb_pas_ctx->has_iommu =3D rproc->has_io= mmu; ret =3D rproc_add(rproc); if (ret) goto remove_ssr_sysmon; --=20 2.50.1 From nobody Sat Oct 4 06:37:08 2025 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 453F7305E24 for ; Tue, 19 Aug 2025 16:56:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622569; cv=none; b=Ng5UM/vs3Fd9ywF/b1Axnbto8vuyJ85b3D2NaP1xfn//8vpSIgRcfN8Bj9aJkKAC3jV0pLr+i9oyNGsswxVnHSO9aPueAihIZzz/flsLTgEzANKFn9cBxnA1B8E+q/21uQjgMlwG0HaTNvd3jwabVN0uNLFXggAUCCEtUOtIWN8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755622569; c=relaxed/simple; bh=4ddIxvA0hH2mxKgfv6MJY3eyB2GVx5N6CjAeCWH79KI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ga5C30aSozi9gaVDiQJEdqBIwTYq3w+NxrQJCcwUDulO1X30oHp1TH3Jhw5ch70LBFpR1eJFQBO4lbMnv/2BjxhetO6QHrAy8dAKFfFp6351jKCyq6QvEjSArGdWmluXpFvo4IcIxHwiDVYTsb5hR0EEoUlIGQQITMdHa/0Nf1M= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=SobHllPW; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="SobHllPW" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J90YSm021768 for ; Tue, 19 Aug 2025 16:56:07 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=fwtoFh3kbTj shFkNb7Zh2kYEycwDTbRcgDbn16CiXI0=; b=SobHllPW2sSiKrpl/VQRv+jiiRS kZROaXacbWCM1uLOgoRb4YoqbVCHOdSUkXTGHppfrX2FvG4g25dFUM+AoKILMRAD xBxGVwXMlhtF8s4PVvLM3wqD2D1wiEX8YPXapJiDtrfrIT+FLBVRRhksUiyM5VJM DpEQrMm2iuuwkI3K9n9e2nToInUH/Ap2hKiQenhh+7hhv+1AARmmnPsTjzFd7+3W asRmqiVANYvdNpEtNEdAZC0QPvEpOnj0o3MflbCiuEccJK6CdegHpVJyTSLLNnSc AXIW6Z4S1HOlzWmxX45mmD0hcQbacVNxO1CJEP06LtBKps4p1RD3inQQzJw== Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48m71cm23p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 19 Aug 2025 16:56:07 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-2445806b2beso136932765ad.1 for ; Tue, 19 Aug 2025 09:56:07 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755622567; x=1756227367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fwtoFh3kbTjshFkNb7Zh2kYEycwDTbRcgDbn16CiXI0=; b=Qlj0BsMhGXqg+cwDAQT9ysQHN5fyeF6T3BBEk3Hc+ZKqhNOdOY8Xjak/OG6U38vFvV 4emvxI4WVHVfnwjIKgfyIxveYWwKNEZf8Gg52IqDu289NR5PfluHCMwoIn7Hv4/buY4W jxZQc63wJRupt0rECIqgKhNO0vNstrs9MDM8dkM4YJYIRog55j9UIZvUKHmwBL/bBV3K kE29k//KHKZhAvQNvPAMIE2uqcZVeeZxeVVMX2H1xsoeFhZgNfOTzxt9ME7oeYTbb4/X 3WkITfuXhK1fResScz7j4mpqNf2UKUJCdf2thyMobK+9jzUIzG9rgN46mi6EsquIrB8z vjqQ== X-Forwarded-Encrypted: i=1; AJvYcCW2pHnXdOANA0KD1XH8C+sC20HKPxh6gFGzirRjCh+VrxDTN0whFnd0rUFTWXZcz3F+dcDwc4g7tDZ5HTg=@vger.kernel.org X-Gm-Message-State: AOJu0Yy/Ra5+IANj7FJAH+6KcQtu7eMuEIBGRsosKH1aIu6mjWuSHgw/ 1mrIzZXLLJnV2vqxKbkkhT2PTF4XvpC3Rdx3Be5trplS4bK5W0z3e7PLUvbaq9q8YeUE7wAd5zl 55KN2znoq+OUmadEXtLg6U02mBNtPMWgbwFuk6uOcKJIG1UvoE1k8pTW4DR7UWLcpH3w= X-Gm-Gg: ASbGnctVDij49xbjhpCXMmD6ZWdy9bftsdr3C6joici1Gg+Eqt+fgJjmTGPvKOUm5NN sSUJaM+dHRLyF+aROQdvdWCNqzxZjSyl2t+61nq/4a3rYHTiMLvfyG5zCphmAGP+/lcYHwBU1bf vbr3CVa1jiaPcOTXj1UPD+a0y+ikd6Dz36tgS9vSKgeK9YyoGwxUXhf4rw26FooicqY9zM4zWjQ ACsOnnirH2DUHzci2pCHfKAk1eD+kfy+NqLGwf0bsfe2RFZVtHjrNFNfiv+uM7h9MzG/oN6mBrs FGAgIM8sSSHJ2/kjrtknFOpCg0pfTUp9JB5Hn5yM2lrCrAWrNQOEjT/abdOYaMIOdjw= X-Received: by 2002:a17:902:ea11:b0:242:9bbc:6018 with SMTP id d9443c01a7336-245e051092bmr51315345ad.56.1755622566636; Tue, 19 Aug 2025 09:56:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IECdBDJr9BaOa9/J98OCpO/ByhVvfRXLinprKgpMUZLUWytix2y9gTMERA8CUJSmYI74CBLNw== X-Received: by 2002:a17:902:ea11:b0:242:9bbc:6018 with SMTP id d9443c01a7336-245e051092bmr51314965ad.56.1755622566169; Tue, 19 Aug 2025 09:56:06 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed33aa3esm2273885ad.24.2025.08.19.09.56.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 09:56:05 -0700 (PDT) From: Mukesh Ojha To: Bjorn Andersson , Konrad Dybcio , Vikash Garodia , Dikshita Agarwal , Mauro Carvalho Chehab , Mathieu Poirier Cc: Abhinav Kumar , "Bryan O'Donoghue" , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, linux-remoteproc@vger.kernel.org, Mukesh Ojha Subject: [PATCH v2 11/11] media: iris: Enable Secure PAS support with IOMMU managed by Linux Date: Tue, 19 Aug 2025 22:24:46 +0530 Message-ID: <20250819165447.4149674-12-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> References: <20250819165447.4149674-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: 8FY34prqD5-lIMW5CqhXBEZfUkXROJgD X-Proofpoint-GUID: 8FY34prqD5-lIMW5CqhXBEZfUkXROJgD X-Authority-Analysis: v=2.4 cv=IvQecK/g c=1 sm=1 tr=0 ts=68a4aca7 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=2OwXVqhp2XgA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=BWwITLIJPpf_DTsiswIA:9 a=1OuFwYUASf3TG4hYMiVC:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE4MDE0NyBTYWx0ZWRfX+srdmmMigvEt CsYjCTCBrFBNeNtwjgrX7xbPH2nIOx8oI43Y8Mu5YJ5vTXg/ZOVIJ8gtG1QisFPdXKLyfIa+HjO wUI6oAJAZ9OM32dp5jftMpkg+rLaTzgXXgWfuaV2WM4fMH+eLl/kUMfOQbzpxROddoGZUXqgwY0 LirifSDhCB0s1xIMHEsKlMko/IjIYDfKadtNmt+q+WXE0Qau+gsN0Uxi1U/hRYit7Ak5PdXBh4B 20IImSRsyG4sRswC+ob5CJsz2aSi2XtkfTwPFCyYj0nJ5afMC81SaWTp0NFu3rIVvI4vudgBNVf g8ylWH9hSZrTIPHKylulVknMN4L82rTUxVSCMiIaga3bSY0sw+gQ3Hxq+5SwPpWWN1YEJ4Ls1sK kD44E7kD X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_02,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 phishscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508180147 Content-Type: text/plain; charset="utf-8" Most Qualcomm platforms feature a proprietary hypervisor (such as Gunyah or QHEE), which typically handles IOMMU configuration. This includes mapping memory regions and device memory resources for remote processors by intercepting qcom_scm_pas_auth_and_reset() calls. These mappings are later removed during teardown. Additionally, SHM bridge setup is required to enable memory protection for both remoteproc metadata and its memory regions. When the hypervisor is absent, the operating system must perform these configurations instead. Support for handling IOMMU and SHM setup in the absence of a hypervisor is now in place. Extend the Iris driver to enable this functionality on platforms where IOMMU is managed by Linux (i.e., non-Gunyah, non-QHEE). Additionally, the Iris driver must map the firmware and its required resources to the firmware SID, which is now specified via the device tree. Co-developed-by: Vikash Garodia Signed-off-by: Vikash Garodia Signed-off-by: Mukesh Ojha --- drivers/media/platform/qcom/iris/iris_core.c | 9 +- drivers/media/platform/qcom/iris/iris_core.h | 6 + .../media/platform/qcom/iris/iris_firmware.c | 156 ++++++++++++++++-- .../media/platform/qcom/iris/iris_firmware.h | 2 + 4 files changed, 155 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.c b/drivers/media/p= latform/qcom/iris/iris_core.c index 0fa0a3b549a2..57417d4d7e05 100644 --- a/drivers/media/platform/qcom/iris/iris_core.c +++ b/drivers/media/platform/qcom/iris/iris_core.c @@ -17,6 +17,7 @@ void iris_core_deinit(struct iris_core *core) mutex_lock(&core->lock); iris_fw_unload(core); iris_vpu_power_off(core); + iris_fw_deinit(core); iris_hfi_queues_deinit(core); core->state =3D IRIS_CORE_DEINIT; mutex_unlock(&core->lock); @@ -65,10 +66,14 @@ int iris_core_init(struct iris_core *core) if (ret) goto error_queue_deinit; =20 - ret =3D iris_fw_load(core); + ret =3D iris_fw_init(core); if (ret) goto error_power_off; =20 + ret =3D iris_fw_load(core); + if (ret) + goto error_firmware_deinit; + ret =3D iris_vpu_boot_firmware(core); if (ret) goto error_unload_fw; @@ -83,6 +88,8 @@ int iris_core_init(struct iris_core *core) =20 error_unload_fw: iris_fw_unload(core); +error_firmware_deinit: + iris_fw_deinit(core); error_power_off: iris_vpu_power_off(core); error_queue_deinit: diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index aeeac32a1f6d..57eeefb38f22 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -73,6 +73,12 @@ struct iris_core { int irq; struct v4l2_device v4l2_dev; struct video_device *vdev_dec; + bool has_iommu; + struct video_firmware { + struct device *dev; + struct qcom_scm_pas_ctx *ctx; + struct iommu_domain *iommu_domain; + } fw; const struct v4l2_file_operations *iris_v4l2_file_ops; const struct v4l2_ioctl_ops *iris_v4l2_ioctl_ops; const struct vb2_ops *iris_vb2_ops; diff --git a/drivers/media/platform/qcom/iris/iris_firmware.c b/drivers/med= ia/platform/qcom/iris/iris_firmware.c index f1b5cd56db32..e3f2fe5c9d7a 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.c +++ b/drivers/media/platform/qcom/iris/iris_firmware.c @@ -3,10 +3,18 @@ * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights res= erved. */ =20 +#include #include -#include +#include +#include +#include +#include #include #include +#include +#include +#include +#include #include =20 #include "iris_core.h" @@ -17,15 +25,14 @@ static int iris_load_fw_to_memory(struct iris_core *core, const char *fw_n= ame) { u32 pas_id =3D core->iris_platform_data->pas_id; + struct qcom_scm_pas_ctx *ctx; const struct firmware *firmware =3D NULL; struct device *dev =3D core->dev; - struct reserved_mem *rmem; - struct device_node *node; - phys_addr_t mem_phys; - size_t res_size; - ssize_t fw_size; - void *mem_virt; - int ret; + struct reserved_mem *rmem =3D NULL; + struct device_node *node =3D NULL; + ssize_t fw_size =3D 0; + void *mem_virt =3D NULL; + int ret =3D 0; =20 if (strlen(fw_name) >=3D MAX_FIRMWARE_NAME_SIZE - 4) return -EINVAL; @@ -39,36 +46,64 @@ static int iris_load_fw_to_memory(struct iris_core *cor= e, const char *fw_name) if (!rmem) return -EINVAL; =20 - mem_phys =3D rmem->base; - res_size =3D rmem->size; + if (core->has_iommu) + dev =3D core->fw.dev; =20 + ctx =3D qcom_scm_pas_ctx_init(dev, pas_id, rmem->base, rmem->size, false); + if (!ctx) + return -ENOMEM; + + ctx->has_iommu =3D core->has_iommu; ret =3D request_firmware(&firmware, fw_name, dev); if (ret) return ret; =20 fw_size =3D qcom_mdt_get_size(firmware); - if (fw_size < 0 || res_size < (size_t)fw_size) { + if (fw_size < 0 || rmem->size < (size_t)fw_size) { ret =3D -EINVAL; goto err_release_fw; } =20 - mem_virt =3D memremap(mem_phys, res_size, MEMREMAP_WC); + mem_virt =3D memremap(rmem->base, rmem->size, MEMREMAP_WC); if (!mem_virt) { ret =3D -ENOMEM; goto err_release_fw; } =20 - ret =3D qcom_mdt_load(dev, firmware, fw_name, - pas_id, mem_virt, mem_phys, res_size, NULL); + ret =3D qcom_mdt_pas_load(ctx, firmware, fw_name, mem_virt, NULL); if (ret) goto err_mem_unmap; =20 - ret =3D qcom_scm_pas_auth_and_reset(pas_id); + if (core->has_iommu) { + ret =3D iommu_map(core->fw.iommu_domain, 0, rmem->base, rmem->size, + IOMMU_READ | IOMMU_WRITE | IOMMU_PRIV, GFP_KERNEL); + if (ret) + goto err_mem_unmap; + + /* + * Firmware has no support for resource table for now, so, lets + * pass NULL and zero for input resource table and input resource + * table respectively. + */ + ret =3D qcom_mdt_pas_map_devmem_rscs(ctx, core->fw.iommu_domain, NULL, 0= ); + if (ret) + goto err_unmap_carveout; + } + + ret =3D qcom_scm_pas_prepare_and_auth_reset(ctx); if (ret) - goto err_mem_unmap; + goto err_unmap_devmem_rscs; + + core->fw.ctx =3D ctx; =20 return ret; =20 +err_unmap_devmem_rscs: + if (core->has_iommu) + qcom_mdt_pas_unmap_devmem_rscs(ctx, core->fw.iommu_domain); +err_unmap_carveout: + if (core->has_iommu) + iommu_unmap(core->fw.iommu_domain, 0, rmem->size); err_mem_unmap: memunmap(mem_virt); err_release_fw: @@ -109,10 +144,97 @@ int iris_fw_load(struct iris_core *core) =20 int iris_fw_unload(struct iris_core *core) { - return qcom_scm_pas_shutdown(core->iris_platform_data->pas_id); + struct qcom_scm_pas_ctx *ctx; + int ret; + + ctx =3D core->fw.ctx; + ret =3D qcom_scm_pas_shutdown(ctx->peripheral); + if (core->has_iommu) { + iommu_unmap(core->fw.iommu_domain, 0, ctx->mem_size); + qcom_mdt_pas_unmap_devmem_rscs(ctx, core->fw.iommu_domain); + } + + return ret; } =20 int iris_set_hw_state(struct iris_core *core, bool resume) { return qcom_scm_set_remote_state(resume, 0); } + +int iris_fw_init(struct iris_core *core) +{ + struct platform_device_info info; + struct iommu_domain *iommu_dom; + struct platform_device *pdev; + struct device_node *np; + int ret; + + np =3D of_get_child_by_name(core->dev->of_node, "video-firmware"); + if (!np) + return 0; + + core->has_iommu =3D true; + memset(&info, 0, sizeof(info)); + info.fwnode =3D &np->fwnode; + info.parent =3D core->dev; + info.name =3D np->name; + info.dma_mask =3D DMA_BIT_MASK(32); + + pdev =3D platform_device_register_full(&info); + if (IS_ERR(pdev)) { + of_node_put(np); + return PTR_ERR(pdev); + } + + pdev->dev.of_node =3D np; + + ret =3D of_dma_configure(&pdev->dev, np, true); + if (ret) { + dev_err(core->dev, "failed to allocate domain\n"); + goto err_unregister; + } + + core->fw.dev =3D &pdev->dev; + + iommu_dom =3D iommu_get_domain_for_dev(core->fw.dev); + if (!iommu_dom) { + dev_err(core->fw.dev, "Failed to get iommu domain\n"); + ret =3D -EINVAL; + goto err_iommu_free; + } + + ret =3D iommu_attach_device(iommu_dom, core->fw.dev); + if (ret) { + dev_err(core->fw.dev, "could not attach device\n"); + goto err_iommu_free; + } + + core->fw.iommu_domain =3D iommu_dom; + + of_node_put(np); + + return 0; + +err_iommu_free: + iommu_domain_free(iommu_dom); +err_unregister: + platform_device_unregister(pdev); + of_node_put(np); + return ret; +} + +void iris_fw_deinit(struct iris_core *core) +{ + struct iommu_domain *iommu_dom; + + if (!core->has_iommu) + return; + + iommu_dom =3D core->fw.iommu_domain; + iommu_detach_device(iommu_dom, core->fw.dev); + iommu_domain_free(iommu_dom); + + core->fw.iommu_domain =3D NULL; + platform_device_unregister(to_platform_device(core->fw.dev)); +} diff --git a/drivers/media/platform/qcom/iris/iris_firmware.h b/drivers/med= ia/platform/qcom/iris/iris_firmware.h index e833ecd34887..adde46109966 100644 --- a/drivers/media/platform/qcom/iris/iris_firmware.h +++ b/drivers/media/platform/qcom/iris/iris_firmware.h @@ -11,5 +11,7 @@ struct iris_core; int iris_fw_load(struct iris_core *core); int iris_fw_unload(struct iris_core *core); int iris_set_hw_state(struct iris_core *core, bool resume); +int iris_fw_init(struct iris_core *core); +void iris_fw_deinit(struct iris_core *core); =20 #endif --=20 2.50.1