From nobody Sat Oct 4 06:33:13 2025 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EE8D258ED2; Tue, 19 Aug 2025 16:24:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755620699; cv=none; b=alFZ2FvKVoRFT400OFeAS1OGN6WlW34MhZd0RXTtw5GvCJd46IkV+CAcsSAUEizcdNTeHIkLVHl5K0TjqvqW1jVuTdYaXrQ0kVCF/xFOtEL9+cGegFcmeRHiLvtlo+eM6eNN1LKK5ckHF5NBvA2esUfhTquVHDq8dQMkaCUWPZc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755620699; c=relaxed/simple; bh=8pVEV6oITofEjYeY+xm9jxWRganabhKV6CxEQcgo0LA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WpGt451T/m/2Mg8ADIrhrLddJlYIsmC8T9NUR8cHaJGa/7H8nSY3JvqqS1J38r7hz93TJ8JK14j2x1IXHqcgzDjtrB+JRdHf+COHV5m0S8Hs+8JVk9lbHIqVhdxmVbkkBl8KuOdNQC0LXm/mawTXdNYf1lmP3GTLqhdn3rEHaHI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=aXDDHoan; arc=none smtp.client-ip=192.198.163.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="aXDDHoan" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755620699; x=1787156699; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8pVEV6oITofEjYeY+xm9jxWRganabhKV6CxEQcgo0LA=; b=aXDDHoanZ2HqrIR6j0hHgAJNeC7ZgiJI4hp8kdeVXGjriqbKSGiBBt3x bbllC1W5kyS8L4GOGDu2Iq2npwT3kMpGtNsimVG4t6M98aM30TG76Iwtd uOF7qqK9PIYYSF8Jnn0oEO/9Q61MGJ8l8WEre2H3m7z6mOF37q0tJxo+6 MSQD0LmNQoX8vHvO7BrEF/5h2eLwWXAcjTSTPMHpgSv3gjJVWW1+fgaS8 2vCIUcM2dcxKcsARgB2oTpJ+ZC1H5E++jmRMROKzwogb3abupzmFRZcnr DQHDIC4/l0AQuMUOWyXTIKcr6fuVsi0DSc6fpnTS0RgLU8QtlkbobtE97 g==; X-CSE-ConnectionGUID: PZYJHxfCR4uOMe2ClNHCQA== X-CSE-MsgGUID: EGYmt5+eTIyqzSSH2ue5rw== X-IronPort-AV: E=McAfee;i="6800,10657,11527"; a="60499966" X-IronPort-AV: E=Sophos;i="6.17,302,1747724400"; d="scan'208";a="60499966" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by fmvoesa107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2025 09:24:58 -0700 X-CSE-ConnectionGUID: g0L01IFbQ0CEtUKGmGsupg== X-CSE-MsgGUID: 4cTtyWDoQX+GIRj8lZD5EQ== X-ExtLoop1: 1 Received: from cpetruta-mobl1.ger.corp.intel.com (HELO localhost.localdomain) ([10.245.244.66]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Aug 2025 09:24:52 -0700 From: Adrian Hunter To: Dave Hansen , Tony Luck , pbonzini@redhat.com, seanjc@google.com Cc: vannapurve@google.com, Borislav Petkov , Thomas Gleixner , Ingo Molnar , x86@kernel.org, H Peter Anvin , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rick.p.edgecombe@intel.com, kai.huang@intel.com, reinette.chatre@intel.com, xiaoyao.li@intel.com, tony.lindgren@linux.intel.com, binbin.wu@linux.intel.com, ira.weiny@intel.com, isaku.yamahata@intel.com, Fan Du , Yazen Ghannam , yan.y.zhao@intel.com, chao.gao@intel.com Subject: [PATCH RESEND V2 1/2] x86/mce: Fix missing address mask in recovery for errors in TDX/SEAM non-root mode Date: Tue, 19 Aug 2025 19:24:34 +0300 Message-ID: <20250819162436.137625-2-adrian.hunter@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819162436.137625-1-adrian.hunter@intel.com> References: <20250819162436.137625-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Commit 8a01ec97dc066 ("x86/mce: Mask out non-address bits from machine check bank") introduced a new #define MCI_ADDR_PHYSADDR for the mask of valid physical address bits within the machine check bank address register. This is particularly needed in the case of errors in TDX/SEAM non-root mode because the reported address contains the TDX KeyID. Refer to TDX and TME-MK documentation for more information about KeyIDs. Commit 7911f145de5fe ("x86/mce: Implement recovery for errors in TDX/SEAM non-root mode") uses the address to mark the affected page as poisoned, but omits to use the aforementioned mask. Investigation of user space expectations has concluded it would be more correct for the address to contain only address bits in the first place. Refer https://lore.kernel.org/r/807ff02d-7af0-419d-8d14-a4d6c5d5420d@intel.= com Mask the address when it is read from the machine check bank address register. Do not use MCI_ADDR_PHYSADDR because that will be removed in a later patch. It is assumed __log_error() in arch/x86/kernel/cpu/mce/amd.c does not need similar treatment. Amend struct mce addr member description slightly to reflect that it is not, and never has been, an exact copy of the bank's MCi_ADDR MSR. Fixes: 8a01ec97dc066 ("x86/mce: Mask out non-address bits from machine chec= k bank") Fixes: 7911f145de5fe ("x86/mce: Implement recovery for errors in TDX/SEAM n= on-root mode") Link: https://lore.kernel.org/r/807ff02d-7af0-419d-8d14-a4d6c5d5420d@intel.= com Cc: stable@vger.kernel.org Signed-off-by: Adrian Hunter --- Changes in V2: Mask address when it is read Amend struct mce addr description arch/x86/include/uapi/asm/mce.h | 2 +- arch/x86/kernel/cpu/mce/core.c | 3 +++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/uapi/asm/mce.h b/arch/x86/include/uapi/asm/mc= e.h index cb6b48a7c22b..abf6ee43f5f8 100644 --- a/arch/x86/include/uapi/asm/mce.h +++ b/arch/x86/include/uapi/asm/mce.h @@ -14,7 +14,7 @@ struct mce { __u64 status; /* Bank's MCi_STATUS MSR */ __u64 misc; /* Bank's MCi_MISC MSR */ - __u64 addr; /* Bank's MCi_ADDR MSR */ + __u64 addr; /* Address from bank's MCi_ADDR MSR */ __u64 mcgstatus; /* Machine Check Global Status MSR */ __u64 ip; /* Instruction Pointer when the error happened */ __u64 tsc; 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19 Aug 2025 09:24:58 -0700 From: Adrian Hunter To: Dave Hansen , Tony Luck , pbonzini@redhat.com, seanjc@google.com Cc: vannapurve@google.com, Borislav Petkov , Thomas Gleixner , Ingo Molnar , x86@kernel.org, H Peter Anvin , linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, rick.p.edgecombe@intel.com, kai.huang@intel.com, reinette.chatre@intel.com, xiaoyao.li@intel.com, tony.lindgren@linux.intel.com, binbin.wu@linux.intel.com, ira.weiny@intel.com, isaku.yamahata@intel.com, Fan Du , Yazen Ghannam , yan.y.zhao@intel.com, chao.gao@intel.com Subject: [PATCH RESEND V2 2/2] x86/mce: Remove MCI_ADDR_PHYSADDR Date: Tue, 19 Aug 2025 19:24:35 +0300 Message-ID: <20250819162436.137625-3-adrian.hunter@intel.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819162436.137625-1-adrian.hunter@intel.com> References: <20250819162436.137625-1-adrian.hunter@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Now that the address is masked when it is read from the machine check bank address register (refer patch "x86/mce: Fix missing address mask in recovery for errors in TDX/SEAM non-root mode"), the MCI_ADDR_PHYSADDR macro is no longer needed. Remove it. Note MCE address information also enters the kernel from APEI via the Common Platform Error Record (CPER) Memory Error Section "Physical Address" field (struct cper_sec_mem_err physical_addr), refer the UEFI specification. It is assumed that field contains only the physical address. Signed-off-by: Adrian Hunter --- Changes in V2: New patch arch/x86/include/asm/mce.h | 3 --- arch/x86/kernel/cpu/mce/core.c | 6 +++--- drivers/cxl/core/mce.c | 2 +- drivers/edac/skx_common.c | 2 +- 4 files changed, 5 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h index 6c77c03139f7..0cf8017dcae9 100644 --- a/arch/x86/include/asm/mce.h +++ b/arch/x86/include/asm/mce.h @@ -91,9 +91,6 @@ #define MCI_MISC_ADDR_MEM 3 /* memory address */ #define MCI_MISC_ADDR_GENERIC 7 /* generic */ =20 -/* MCi_ADDR register defines */ -#define MCI_ADDR_PHYSADDR GENMASK_ULL(boot_cpu_data.x86_phys_bits - 1, 0) - /* CTL2 register defines */ #define MCI_CTL2_CMCI_EN BIT_ULL(30) #define MCI_CTL2_CMCI_THRESHOLD_MASK 0x7fffULL diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c index deb47463a75d..80e06d6728a7 100644 --- a/arch/x86/kernel/cpu/mce/core.c +++ b/arch/x86/kernel/cpu/mce/core.c @@ -642,7 +642,7 @@ static int uc_decode_notifier(struct notifier_block *nb= , unsigned long val, mce->severity !=3D MCE_DEFERRED_SEVERITY) return NOTIFY_DONE; =20 - pfn =3D (mce->addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT; + pfn =3D mce->addr >> PAGE_SHIFT; if (!memory_failure(pfn, 0)) { set_mce_nospec(pfn); mce->kflags |=3D MCE_HANDLED_UC; @@ -1415,7 +1415,7 @@ static void kill_me_maybe(struct callback_head *cb) if (!p->mce_ripv) flags |=3D MF_MUST_KILL; =20 - pfn =3D (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT; + pfn =3D p->mce_addr >> PAGE_SHIFT; ret =3D memory_failure(pfn, flags); if (!ret) { set_mce_nospec(pfn); @@ -1444,7 +1444,7 @@ static void kill_me_never(struct callback_head *cb) =20 p->mce_count =3D 0; pr_err("Kernel accessed poison in user space at %llx\n", p->mce_addr); - pfn =3D (p->mce_addr & MCI_ADDR_PHYSADDR) >> PAGE_SHIFT; + pfn =3D p->mce_addr >> PAGE_SHIFT; if (!memory_failure(pfn, 0)) set_mce_nospec(pfn); } diff --git a/drivers/cxl/core/mce.c b/drivers/cxl/core/mce.c index ff8d078c6ca1..4ba8b7ae3de7 100644 --- a/drivers/cxl/core/mce.c +++ b/drivers/cxl/core/mce.c @@ -24,7 +24,7 @@ static int cxl_handle_mce(struct notifier_block *nb, unsi= gned long val, if (!endpoint) return NOTIFY_DONE; =20 - spa =3D mce->addr & MCI_ADDR_PHYSADDR; + spa =3D mce->addr; =20 pfn =3D spa >> PAGE_SHIFT; if (!pfn_valid(pfn)) diff --git a/drivers/edac/skx_common.c b/drivers/edac/skx_common.c index 39c733dbc5b9..2de675958560 100644 --- a/drivers/edac/skx_common.c +++ b/drivers/edac/skx_common.c @@ -732,7 +732,7 @@ int skx_mce_check_error(struct notifier_block *nb, unsi= gned long val, =20 memset(&res, 0, sizeof(res)); res.mce =3D mce; - res.addr =3D mce->addr & MCI_ADDR_PHYSADDR; + res.addr =3D mce->addr; if (!pfn_to_online_page(res.addr >> PAGE_SHIFT) && !arch_is_platform_page= (res.addr)) { pr_err("Invalid address 0x%llx in IA32_MC%d_ADDR\n", mce->addr, mce->ban= k); return NOTIFY_DONE; --=20 2.48.1