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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:12 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 18/19] ARM: tegra: add CSI binding for Tegra20 and Tegra30 Date: Tue, 19 Aug 2025 15:16:30 +0300 Message-ID: <20250819121631.84280-19-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CSI node to Tegra20 and Tegra30 device trees. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra20.dtsi | 17 ++++++++++++++++- arch/arm/boot/dts/nvidia/tegra30.dtsi | 19 ++++++++++++++++++- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvid= ia/tegra20.dtsi index 606839fd40bb..d00786368115 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -64,7 +64,7 @@ mpe@54040000 { =20 vi@54080000 { compatible =3D "nvidia,tegra20-vi"; - reg =3D <0x54080000 0x00040000>; + reg =3D <0x54080000 0x00000800>; interrupts =3D ; clocks =3D <&tegra_car TEGRA20_CLK_VI>; resets =3D <&tegra_car 20>; @@ -72,6 +72,21 @@ vi@54080000 { power-domains =3D <&pd_venc>; operating-points-v2 =3D <&vi_dvfs_opp_table>; status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x0 0x54080000 0x4000>; + + csi@800 { + compatible =3D "nvidia,tegra20-csi"; + reg =3D <0x800 0x200>; + clocks =3D <&tegra_car TEGRA20_CLK_CSI>; + clock-names =3D "csi"; + power-domains =3D <&pd_venc>; + + status =3D "disabled"; + }; }; =20 /* DSI MIPI calibration logic is a part of VI/CSI */ diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvid= ia/tegra30.dtsi index d9223bd7cf3b..c3e9212d5edf 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -151,7 +151,7 @@ mpe@54040000 { =20 vi@54080000 { compatible =3D "nvidia,tegra30-vi"; - reg =3D <0x54080000 0x00040000>; + reg =3D <0x54080000 0x00000800>; interrupts =3D ; clocks =3D <&tegra_car TEGRA30_CLK_VI>; resets =3D <&tegra_car 20>; @@ -162,6 +162,23 @@ vi@54080000 { iommus =3D <&mc TEGRA_SWGROUP_VI>; =20 status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x0 0x54080000 0x4000>; + + csi@800 { + compatible =3D "nvidia,tegra30-csi"; + reg =3D <0x800 0x200>; + clocks =3D <&tegra_car TEGRA30_CLK_CSI>, + <&tegra_car TEGRA30_CLK_CSIA_PAD>, + <&tegra_car TEGRA30_CLK_CSIB_PAD>; + clock-names =3D "csi", "csia_pad", "csib_pad"; + power-domains =3D <&pd_venc>; + + status =3D "disabled"; + }; }; =20 /* DSI MIPI calibration logic is a part of VI/CSI */ --=20 2.48.1