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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:43 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 01/19] clk: tegra: init CSUS clock for Tegra20 and Tegra30 Date: Tue, 19 Aug 2025 15:16:13 +0300 Message-ID: <20250819121631.84280-2-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" CSUS clock is required to be enabled on camera device configuration or else camera module refuses to initiate properly. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/clk-tegra20.c | 1 + drivers/clk/tegra/clk-tegra30.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra2= 0.c index 551ef0cf0c9a..42f8150c6110 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1043,6 +1043,7 @@ static struct tegra_clk_init_table init_table[] =3D { { TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_VDE, TEGRA20_CLK_PLL_C, 300000000, 0 }, { TEGRA20_CLK_PWM, TEGRA20_CLK_PLL_P, 48000000, 0 }, + { TEGRA20_CLK_CSUS, TEGRA20_CLK_CLK_MAX, 6000000, 1 }, /* must be the last entry */ { TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0 }, }; diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra3= 0.c index 82a8cb9545eb..70e85e2949e0 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -1237,6 +1237,7 @@ static struct tegra_clk_init_table init_table[] =3D { { TEGRA30_CLK_HDA, TEGRA30_CLK_PLL_P, 102000000, 0 }, { TEGRA30_CLK_HDA2CODEC_2X, TEGRA30_CLK_PLL_P, 48000000, 0 }, { TEGRA30_CLK_PWM, TEGRA30_CLK_PLL_P, 48000000, 0 }, + { TEGRA30_CLK_CSUS, TEGRA30_CLK_CLK_MAX, 6000000, 1 }, /* must be the last entry */ { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 }, }; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:44 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 02/19] dt-bindings: clock: tegra20: Add IDs for CSI PAD clocks Date: Tue, 19 Aug 2025 15:16:14 +0300 Message-ID: <20250819121631.84280-3-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra30 has CSI PAD clock enable bits embedded into PLLD/PLLD2 registers. Add ids for these clocks. Signed-off-by: Svyatoslav Ryhel --- include/dt-bindings/clock/tegra30-car.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/tegra30-car.h b/include/dt-bindings/= clock/tegra30-car.h index f193663e6f28..14b83e90a0fc 100644 --- a/include/dt-bindings/clock/tegra30-car.h +++ b/include/dt-bindings/clock/tegra30-car.h @@ -271,6 +271,8 @@ #define TEGRA30_CLK_AUDIO3_MUX 306 #define TEGRA30_CLK_AUDIO4_MUX 307 #define TEGRA30_CLK_SPDIF_MUX 308 -#define TEGRA30_CLK_CLK_MAX 309 +#define TEGRA30_CLK_CSIA_PAD 309 +#define TEGRA30_CLK_CSIB_PAD 310 +#define TEGRA30_CLK_CLK_MAX 311 =20 #endif /* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */ --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF49C33EB05; Tue, 19 Aug 2025 12:16:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:46 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 03/19] clk: tegra30: add CSI PAD clock gates Date: Tue, 19 Aug 2025 15:16:15 +0300 Message-ID: <20250819121631.84280-4-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra30 has CSI PAD bits in both PLLD and PLLD2 clocks, that are required for correct work of CSI block. Signed-off-by: Svyatoslav Ryhel --- drivers/clk/tegra/clk-tegra30.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk-tegra30.c b/drivers/clk/tegra/clk-tegra3= 0.c index 70e85e2949e0..f033eb1ac26a 100644 --- a/drivers/clk/tegra/clk-tegra30.c +++ b/drivers/clk/tegra/clk-tegra30.c @@ -153,6 +153,7 @@ static unsigned long input_freq; =20 static DEFINE_SPINLOCK(cml_lock); static DEFINE_SPINLOCK(pll_d_lock); +static DEFINE_SPINLOCK(pll_d2_lock); =20 #define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \ _clk_num, _gate_flags, _clk_id) \ @@ -859,7 +860,7 @@ static void __init tegra30_pll_init(void) =20 /* PLLD2 */ clk =3D tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0, - &pll_d2_params, NULL); + &pll_d2_params, &pll_d2_lock); clks[TEGRA30_CLK_PLL_D2] =3D clk; =20 /* PLLD2_OUT0 */ @@ -1008,6 +1009,18 @@ static void __init tegra30_periph_clk_init(void) 0, 48, periph_clk_enb_refcnt); clks[TEGRA30_CLK_DSIA] =3D clk; =20 + /* csia_pad */ + clk =3D clk_register_gate(NULL, "csia_pad", "pll_d", CLK_SET_RATE_PARENT, + clk_base + PLLD_BASE, 26, 0, &pll_d_lock); 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Tue, 19 Aug 2025 05:16:48 -0700 (PDT) Received: from xeon.. ([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:48 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 04/19] dt-bindings: display: tegra: document Tegra30 VIP Date: Tue, 19 Aug 2025 15:16:16 +0300 Message-ID: <20250819121631.84280-5-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parallel VI interface found in Tegra30 is exactly the same as Tegra20 has. Signed-off-by: Svyatoslav Ryhel --- .../devicetree/bindings/display/tegra/nvidia,tegra20-vip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20= -vip.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-= vip.yaml index 14294edb8d8c..39e9b3297dbd 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.ya= ml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vip.ya= ml @@ -13,6 +13,7 @@ properties: compatible: enum: - nvidia,tegra20-vip + - nvidia,tegra30-vip =20 ports: $ref: /schemas/graph.yaml#/properties/ports --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3711A340DBF; Tue, 19 Aug 2025 12:16:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:49 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 05/19] staging: media: tegra-video: expand VI and VIP support to Tegra30 Date: Tue, 19 Aug 2025 15:16:17 +0300 Message-ID: <20250819121631.84280-6-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Exisitng VI and VIP implementation for Tegra20 is fully compatible with Tegra30. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/Makefile | 1 + drivers/staging/media/tegra-video/vi.c | 3 +++ drivers/staging/media/tegra-video/vi.h | 2 +- drivers/staging/media/tegra-video/video.c | 4 ++++ drivers/staging/media/tegra-video/vip.c | 5 ++++- 5 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/tegra-video/Makefile b/drivers/staging/m= edia/tegra-video/Makefile index 6c7552e05109..96380b5dbd8b 100644 --- a/drivers/staging/media/tegra-video/Makefile +++ b/drivers/staging/media/tegra-video/Makefile @@ -6,5 +6,6 @@ tegra-video-objs :=3D \ csi.o =20 tegra-video-$(CONFIG_ARCH_TEGRA_2x_SOC) +=3D tegra20.o +tegra-video-$(CONFIG_ARCH_TEGRA_3x_SOC) +=3D tegra20.o tegra-video-$(CONFIG_ARCH_TEGRA_210_SOC) +=3D tegra210.o obj-$(CONFIG_VIDEO_TEGRA) +=3D tegra-video.o diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media= /tegra-video/vi.c index c9276ff76157..71be205cacb5 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -1959,6 +1959,9 @@ static const struct of_device_id tegra_vi_of_id_table= [] =3D { #if defined(CONFIG_ARCH_TEGRA_2x_SOC) { .compatible =3D "nvidia,tegra20-vi", .data =3D &tegra20_vi_soc }, #endif +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) + { .compatible =3D "nvidia,tegra30-vi", .data =3D &tegra20_vi_soc }, +#endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) { .compatible =3D "nvidia,tegra210-vi", .data =3D &tegra210_vi_soc }, #endif diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media= /tegra-video/vi.h index 1e6a5caa7082..cac0c0d0e225 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -296,7 +296,7 @@ struct tegra_video_format { u32 fourcc; }; =20 -#if defined(CONFIG_ARCH_TEGRA_2x_SOC) +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC) extern const struct tegra_vi_soc tegra20_vi_soc; #endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) diff --git a/drivers/staging/media/tegra-video/video.c b/drivers/staging/me= dia/tegra-video/video.c index 074ad0dc56ca..a25885f93cd7 100644 --- a/drivers/staging/media/tegra-video/video.c +++ b/drivers/staging/media/tegra-video/video.c @@ -127,6 +127,10 @@ static const struct of_device_id host1x_video_subdevs[= ] =3D { { .compatible =3D "nvidia,tegra20-vip", }, { .compatible =3D "nvidia,tegra20-vi", }, #endif +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) + { .compatible =3D "nvidia,tegra30-vip", }, + { .compatible =3D "nvidia,tegra30-vi", }, +#endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) { .compatible =3D "nvidia,tegra210-csi", }, { .compatible =3D "nvidia,tegra210-vi", }, diff --git a/drivers/staging/media/tegra-video/vip.c b/drivers/staging/medi= a/tegra-video/vip.c index 5ec717f3afd5..00e08a9971d5 100644 --- a/drivers/staging/media/tegra-video/vip.c +++ b/drivers/staging/media/tegra-video/vip.c @@ -263,13 +263,16 @@ static void tegra_vip_remove(struct platform_device *= pdev) pm_runtime_disable(&pdev->dev); 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:51 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 06/19] staging: media: tegra-video: csi: move CSI helpers to header Date: Tue, 19 Aug 2025 15:16:18 +0300 Message-ID: <20250819121631.84280-7-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move CSI helpers into the header for easier access from SoC-specific video driver parts. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/csi.c | 11 ----------- drivers/staging/media/tegra-video/csi.h | 10 ++++++++++ 2 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/medi= a/tegra-video/csi.c index 604185c00a1a..74c92db1032f 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -20,17 +20,6 @@ =20 #define MHZ 1000000 =20 -static inline struct tegra_csi * -host1x_client_to_csi(struct host1x_client *client) -{ - return container_of(client, struct tegra_csi, client); -} - -static inline struct tegra_csi_channel *to_csi_chan(struct v4l2_subdev *su= bdev) -{ - return container_of(subdev, struct tegra_csi_channel, subdev); -} - /* * CSI is a separate subdevice which has 6 source pads to generate * test pattern. CSI subdevice pad ops are used only for TPG and diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/medi= a/tegra-video/csi.h index 3e6e5ee1bb1e..3ed2dbc73ce9 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -151,6 +151,16 @@ struct tegra_csi { struct list_head csi_chans; }; =20 +static inline struct tegra_csi *host1x_client_to_csi(struct host1x_client = *client) +{ + return container_of(client, struct tegra_csi, client); +} + +static inline struct tegra_csi_channel *to_csi_chan(struct v4l2_subdev *su= bdev) +{ + return container_of(subdev, struct tegra_csi_channel, subdev); +} + void tegra_csi_error_recover(struct v4l2_subdev *subdev); void tegra_csi_calc_settle_time(struct tegra_csi_channel *csi_chan, u8 csi_port_num, --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f47.google.com (mail-ej1-f47.google.com [209.85.218.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 00864342C9B; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:53 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 07/19] staging: media: tegra-video: csi: parametrize MIPI calibration device presence Date: Tue, 19 Aug 2025 15:16:19 +0300 Message-ID: <20250819121631.84280-8-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dedicated MIPI calibration block appears only in Tegra114, before Tegra114 all MIPI calibration pads were part of VI block. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/csi.c | 12 +++++++----- drivers/staging/media/tegra-video/csi.h | 1 + drivers/staging/media/tegra-video/tegra210.c | 1 + 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/medi= a/tegra-video/csi.c index 74c92db1032f..2f9907a20db1 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -485,11 +485,13 @@ static int tegra_csi_channel_alloc(struct tegra_csi *= csi, if (IS_ENABLED(CONFIG_VIDEO_TEGRA_TPG)) return 0; =20 - chan->mipi =3D tegra_mipi_request(csi->dev, node); - if (IS_ERR(chan->mipi)) { - ret =3D PTR_ERR(chan->mipi); - chan->mipi =3D NULL; - dev_err(csi->dev, "failed to get mipi device: %d\n", ret); + if (csi->soc->has_mipi_calibration) { + chan->mipi =3D tegra_mipi_request(csi->dev, node); + if (IS_ERR(chan->mipi)) { + ret =3D PTR_ERR(chan->mipi); + chan->mipi =3D NULL; + dev_err(csi->dev, "failed to get mipi device: %d\n", ret); + } } =20 return ret; diff --git a/drivers/staging/media/tegra-video/csi.h b/drivers/staging/medi= a/tegra-video/csi.h index 3ed2dbc73ce9..400b913bb1cb 100644 --- a/drivers/staging/media/tegra-video/csi.h +++ b/drivers/staging/media/tegra-video/csi.h @@ -128,6 +128,7 @@ struct tegra_csi_soc { unsigned int num_clks; const struct tpg_framerate *tpg_frmrate_table; unsigned int tpg_frmrate_table_size; + bool has_mipi_calibration; }; =20 /** diff --git a/drivers/staging/media/tegra-video/tegra210.c b/drivers/staging= /media/tegra-video/tegra210.c index da99f19a39e7..305472e94af4 100644 --- a/drivers/staging/media/tegra-video/tegra210.c +++ b/drivers/staging/media/tegra-video/tegra210.c @@ -1218,4 +1218,5 @@ const struct tegra_csi_soc tegra210_csi_soc =3D { .num_clks =3D ARRAY_SIZE(tegra210_csi_cil_clks), .tpg_frmrate_table =3D tegra210_tpg_frmrate_table, .tpg_frmrate_table_size =3D ARRAY_SIZE(tegra210_tpg_frmrate_table), + .has_mipi_calibration =3D true, }; --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EDC243431F0; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:55 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 08/19] staging: media: tegra-video: vi: adjust get_selection op check Date: Tue, 19 Aug 2025 15:16:20 +0300 Message-ID: <20250819121631.84280-9-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Get_selection operation may be implemented only for sink pad and may return error code. Set try_crop to 0 instead of returning error. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/vi.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media= /tegra-video/vi.c index 71be205cacb5..4f67adc395ac 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -476,15 +476,11 @@ static int __tegra_channel_try_format(struct tegra_vi= _channel *chan, fse.code =3D fmtinfo->code; ret =3D v4l2_subdev_call(subdev, pad, enum_frame_size, sd_state, &fse); if (ret) { - if (!v4l2_subdev_has_op(subdev, pad, get_selection)) { + if (!v4l2_subdev_has_op(subdev, pad, get_selection) || + v4l2_subdev_call(subdev, pad, get_selection, NULL, &sdsel)) { try_crop->width =3D 0; try_crop->height =3D 0; } else { - ret =3D v4l2_subdev_call(subdev, pad, get_selection, - NULL, &sdsel); - if (ret) - return -EINVAL; - try_crop->width =3D sdsel.r.width; try_crop->height =3D sdsel.r.height; } --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f52.google.com (mail-ej1-f52.google.com [209.85.218.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 550C3343205; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:57 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 09/19] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Date: Tue, 19 Aug 2025 15:16:21 +0300 Message-ID: <20250819121631.84280-10-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add HFLIP and VFLIP from SoC only if camera sensor does not provide those controls. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/vi.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media= /tegra-video/vi.c index 4f67adc395ac..61b65a2c1436 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -961,6 +961,7 @@ static int tegra_channel_setup_ctrl_handler(struct tegr= a_vi_channel *chan) } #else struct v4l2_subdev *subdev; + struct v4l2_ctrl *hflip, *vflip; =20 /* custom control */ v4l2_ctrl_new_custom(&chan->ctrl_handler, &syncpt_timeout_ctrl, NULL); @@ -986,11 +987,13 @@ static int tegra_channel_setup_ctrl_handler(struct te= gra_vi_channel *chan) return ret; } =20 - if (chan->vi->soc->has_h_v_flip) { + hflip =3D v4l2_ctrl_find(subdev->ctrl_handler, V4L2_CID_HFLIP); + if (chan->vi->soc->has_h_v_flip && !hflip) v4l2_ctrl_new_std(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_HFLIP, 0, = 1, 1, 0); - v4l2_ctrl_new_std(&chan->ctrl_handler, &vi_ctrl_ops, V4L2_CID_VFLIP, 0, = 1, 1, 0); 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:16:58 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 10/19] staging: media: tegra-video: tegra20: set correct maximum width and height Date: Tue, 19 Aug 2025 15:16:22 +0300 Message-ID: <20250819121631.84280-11-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Maximum width and height for Tegra20 and Tegra30 is determined by respective register field, rounded down to factor of 2, which is 8191U rounded down to 8190U. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/staging/media/tegra-video/tegra20.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index 7b8f8f810b35..3e2d746638b6 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -23,11 +23,10 @@ =20 #define TEGRA_VI_SYNCPT_WAIT_TIMEOUT msecs_to_jiffies(200) =20 -/* This are just good-sense numbers. The actual min/max is not documented.= */ #define TEGRA20_MIN_WIDTH 32U +#define TEGRA20_MAX_WIDTH 8190U #define TEGRA20_MIN_HEIGHT 32U -#define TEGRA20_MAX_WIDTH 2048U -#define TEGRA20_MAX_HEIGHT 2048U +#define TEGRA20_MAX_HEIGHT 8190U =20 /* -----------------------------------------------------------------------= --- * Registers --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f50.google.com (mail-ej1-f50.google.com [209.85.218.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5395F34573D; Tue, 19 Aug 2025 12:17:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755605825; cv=none; b=GSPfCLRQ9Xxnpaxlj4GqLp67TaNu6LppGYQ1vhHaur9ebiVgV7TSYLCA+E+SUKD6r1o1aBpVMOkHzCLF4PFdgn3AMmPO3B8tkcZZqbQvNXEkSxiTX75NPdN4wojbC0ECNa/YH12OM1Owa/rQT3zT3xXyfNWeSNWz1xSWsW/tOU4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755605825; c=relaxed/simple; bh=Aulklx+X+Ecd2UHuEmFTkzfiktgCXEuIjcoFVF2HmI0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=u161OiPXsgBQfszlcJzfNCrsBRIli9TZ6fUZBu4xg2WM6YdOG1rOlrwBieFY9/PtZ/7O7knmwQIeIi95QwRnlf/9Ttm3C4RWwgH1A5/8Zfp1WLE+QlI86/ri7zgZ7flxoJmrOtHo7oHSUkoJ3GkFgIvv0hXCFrbNQylybeET78Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Wn+z5W3z; arc=none smtp.client-ip=209.85.218.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Wn+z5W3z" Received: by mail-ej1-f50.google.com with SMTP id a640c23a62f3a-afcb78d5e74so886926066b.1; Tue, 19 Aug 2025 05:17:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1755605822; x=1756210622; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=shQaKXu/njlANO2DVrc7DiO3su78TsC3dLkVV67F9Z4=; b=Wn+z5W3zSmmKeYMLa2H+hjKm2CSYbTcLHib6xYy4skeu4H6eTt3cEOnlzfLEClisWr HuR4L+Ox6duAauWKGMpWVyXbaZU01tqU//WPQhPixv+CZv4/xJ2y0omgI/G26bc1VUFA lcPjFJ3Hnym2i0ZInZEiM9yZ14+uiZglPwCWkdbKI2ibkxsSEK8S5gBchQuQ0kigzgtj dmpihijatqJHBTP2LmZtN/0+aKAvMTEKWJsPG725ziq4vW3I4/jhUv+duaymkH1lzle+ BirZE//6jePoCZ2k7xU42rMe/Ee0veYH7fdBBcbWQ2QrozLm45IkCPZR8fdbfQH0c4Xc uwYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755605822; x=1756210622; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=shQaKXu/njlANO2DVrc7DiO3su78TsC3dLkVV67F9Z4=; b=qvOElD4RUl4xsL5lqQHG/JvkRkOhsFXiRaFkHzyXq/khq3Qlaj6Wf+YVbVlDFGofk6 zRLQo1yxv9Ao+MDNCnikBZA7J2CO+416GyxXaRSMKMoYf4azmz/gL+2yRXzfhH0Wg3Aw j4UzG/gzoUFsHKXidvTF3gKrUTTZ85yAqb37I4xg7SEyA7rae40Z4rh4HjDk7SvyjvZa c3iHAjBSttp9Mx2Iropb//bqGLIgcfgKAzkpikici72vdUx32Bb3vEnErbXxeUsvg6E7 CUJmEIa8e+8Fusk4rl2UpMp+P+FP2kjvwzMUcq2Y2yichXhOSRCa0UMrIa1H0/1PHLdS Bllw== X-Forwarded-Encrypted: i=1; AJvYcCUU2TfJM8CCLTh/uLXvpYRmFavoXO84dDotvj+LZNYia2SY9KFbrVg2kc3ErCAEZtHlEfHRDCwfTpof@vger.kernel.org, AJvYcCVlk+nyjd/M4SveDweSDDz6rMshJGmZrPOrufK+KB/Wty+vA4cJJOE2hiwoNrkHStE+j2+DWP3uLSEn@vger.kernel.org, AJvYcCX5NOO8vHywIun655LUav7EeFIEGuIp6EQXZycGR4MiuRTqjoLPLovTO4E6qAT9vD5AsDa/jGR4oLBuDt8=@vger.kernel.org, AJvYcCXhGFtixYTh6K3oS6o+x2Oc8Q7xw8AjHJ1fu4E6msNoRNPhW0Rx2FRI9GYtXXAwA6BxMAUS8RrVjUt0wMY4@vger.kernel.org X-Gm-Message-State: AOJu0Yy8D+4/A2bkRI24dXIhr9ycawN7PMmS6j0MdUDzUBvsHea445KG T2RdFGUGGqx1gMJcPk3P0uLGS93DbPqqW3GTiC81Y5FwZv33Z+Lwmb6t X-Gm-Gg: ASbGncskizMia7tPyOVTbzzKdbdtJkHkbsGt3v6IVC11+hwOSRAXN4P2RpUhvLMWLek kfNYMa+523/VWTjZyTv5r8OiTFohrf5mZ8DJKWZo7c/P4kyhzjsxC+GZMrJBcI6wWtUp4BSfokW 1mMz7MR+ANaxyl9PLTXo5W2h2vXU2+2wbXb5m+5tla1mxWl06/+M4f2odLzuypIXEFX4GjUbkmI kAaeuQJAV88gtnEscnNVsfsLe5YUcBnkh6MdYb64n35dEF2yL7Ct26oD6ej2sUh65BKjWcIEa9T LgfqmRQXQ3CLoRx6PosUoJeP293EiM/CZvz7H5cUfFBk9P12Uml5ci6eqlZpMu3xLBQ4EcDFx8j HHQvb2va3K9CfPPSpWxg/oubv X-Google-Smtp-Source: AGHT+IGHQNk5sEHbSAt0c6aQxUV1mNpgXt8T3nzwF45TY8RuVQeGldiAsO8epN25S9EOAnkHPe3uew== X-Received: by 2002:a17:907:72d4:b0:ad5:7bc4:84be with SMTP id a640c23a62f3a-afddd1eb116mr214034866b.52.1755605821572; Tue, 19 Aug 2025 05:17:01 -0700 (PDT) Received: from xeon.. ([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.16.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:00 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 11/19] staging: media: tegra-video: tegra20: add support for second output of VI Date: Tue, 19 Aug 2025 15:16:23 +0300 Message-ID: <20250819121631.84280-12-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" VI in Tegra20/Tegra30 has 2 VI outputs with different set of supported formats. Convert output registers to macros for simpler work with both outputs since apart formats their layout matches. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/tegra20.c | 80 ++++++++++++--------- 1 file changed, 45 insertions(+), 35 deletions(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index 3e2d746638b6..54512d1ecf83 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -28,13 +28,19 @@ #define TEGRA20_MIN_HEIGHT 32U #define TEGRA20_MAX_HEIGHT 8190U =20 +/* Tegra20/Tegra30 has 2 outputs in VI */ +enum { + OUT_1, + OUT_2, +}; + /* -----------------------------------------------------------------------= --- * Registers */ =20 -#define TEGRA_VI_CONT_SYNCPT_OUT_1 0x0060 -#define VI_CONT_SYNCPT_OUT_1_CONTINUOUS_SYNCPT BIT(8) -#define VI_CONT_SYNCPT_OUT_1_SYNCPT_IDX_SFT 0 +#define TEGRA_VI_CONT_SYNCPT_OUT(n) (0x0060 + (n) * 4) +#define VI_CONT_SYNCPT_OUT_CONTINUOUS_SYNCPT BIT(8) +#define VI_CONT_SYNCPT_OUT_SYNCPT_IDX_SFT 0 =20 #define TEGRA_VI_VI_INPUT_CONTROL 0x0088 #define VI_INPUT_FIELD_DETECT BIT(27) @@ -46,6 +52,7 @@ #define VI_INPUT_YUV_INPUT_FORMAT_YVYU (3 << VI_INPUT_YUV_INPUT_FOR= MAT_SFT) #define VI_INPUT_INPUT_FORMAT_SFT 2 /* bits [5:2] */ #define VI_INPUT_INPUT_FORMAT_YUV422 (0 << VI_INPUT_INPUT_FORMAT_SF= T) +#define VI_INPUT_INPUT_FORMAT_BAYER (2 << VI_INPUT_INPUT_FORMAT_SFT) #define VI_INPUT_VIP_INPUT_ENABLE BIT(1) =20 #define TEGRA_VI_VI_CORE_CONTROL 0x008c @@ -66,7 +73,7 @@ #define VI_VI_CORE_CONTROL_OUTPUT_TO_EPP_SFT 2 #define VI_VI_CORE_CONTROL_OUTPUT_TO_ISP_SFT 0 =20 -#define TEGRA_VI_VI_FIRST_OUTPUT_CONTROL 0x0090 +#define TEGRA_VI_VI_OUTPUT_CONTROL(n) (0x0090 + (n) * 4) #define VI_OUTPUT_FORMAT_EXT BIT(22) #define VI_OUTPUT_V_DIRECTION BIT(20) #define VI_OUTPUT_H_DIRECTION BIT(19) @@ -80,6 +87,7 @@ #define VI_OUTPUT_OUTPUT_FORMAT_SFT 0 #define VI_OUTPUT_OUTPUT_FORMAT_YUV422POST (3 << VI_OUTPUT_OUTPUT_FO= RMAT_SFT) #define VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR (6 << VI_OUTPUT_OUTPUT_= FORMAT_SFT) +#define VI_OUTPUT_OUTPUT_FORMAT_VIP_BAYER_DIRECT (9 << VI_OUTPUT_OUT= PUT_FORMAT_SFT) =20 #define TEGRA_VI_VIP_H_ACTIVE 0x00a4 #define VI_VIP_H_ACTIVE_PERIOD_SFT 16 /* active pixels/line, must b= e even */ @@ -89,26 +97,26 @@ #define VI_VIP_V_ACTIVE_PERIOD_SFT 16 /* active lines */ #define VI_VIP_V_ACTIVE_START_SFT 0 =20 -#define TEGRA_VI_VB0_START_ADDRESS_FIRST 0x00c4 -#define TEGRA_VI_VB0_BASE_ADDRESS_FIRST 0x00c8 +#define TEGRA_VI_VB0_START_ADDRESS(n) (0x00c4 + (n) * 44) +#define TEGRA_VI_VB0_BASE_ADDRESS(n) (0x00c8 + (n) * 44) #define TEGRA_VI_VB0_START_ADDRESS_U 0x00cc #define TEGRA_VI_VB0_BASE_ADDRESS_U 0x00d0 #define TEGRA_VI_VB0_START_ADDRESS_V 0x00d4 #define TEGRA_VI_VB0_BASE_ADDRESS_V 0x00d8 =20 -#define TEGRA_VI_FIRST_OUTPUT_FRAME_SIZE 0x00e0 -#define VI_FIRST_OUTPUT_FRAME_HEIGHT_SFT 16 -#define VI_FIRST_OUTPUT_FRAME_WIDTH_SFT 0 +#define TEGRA_VI_OUTPUT_FRAME_SIZE(n) (0x00e0 + (n) * 24) +#define VI_OUTPUT_FRAME_HEIGHT_SFT 16 +#define VI_OUTPUT_FRAME_WIDTH_SFT 0 =20 -#define TEGRA_VI_VB0_COUNT_FIRST 0x00e4 +#define TEGRA_VI_VB0_COUNT(n) (0x00e4 + (n) * 24) =20 -#define TEGRA_VI_VB0_SIZE_FIRST 0x00e8 -#define VI_VB0_SIZE_FIRST_V_SFT 16 -#define VI_VB0_SIZE_FIRST_H_SFT 0 +#define TEGRA_VI_VB0_SIZE(n) (0x00e8 + (n) * 24) +#define VI_VB0_SIZE_V_SFT 16 +#define VI_VB0_SIZE_H_SFT 0 =20 -#define TEGRA_VI_VB0_BUFFER_STRIDE_FIRST 0x00ec -#define VI_VB0_BUFFER_STRIDE_FIRST_CHROMA_SFT 30 -#define VI_VB0_BUFFER_STRIDE_FIRST_LUMA_SFT 0 +#define TEGRA_VI_VB0_BUFFER_STRIDE(n) (0x00ec + (n) * 24) +#define VI_VB0_BUFFER_STRIDE_CHROMA_SFT 30 +#define VI_VB0_BUFFER_STRIDE_LUMA_SFT 0 =20 #define TEGRA_VI_H_LPF_CONTROL 0x0108 #define VI_H_LPF_CONTROL_CHROMA_SFT 16 @@ -136,7 +144,7 @@ #define VI_CAMERA_CONTROL_TEST_MODE BIT(1) #define VI_CAMERA_CONTROL_VIP_ENABLE BIT(0) =20 -#define TEGRA_VI_VI_ENABLE 0x01a4 +#define TEGRA_VI_VI_ENABLE(n) (0x01a4 + (n) * 4) #define VI_VI_ENABLE_SW_FLOW_CONTROL_OUT1 BIT(1) #define VI_VI_ENABLE_FIRST_OUTPUT_TO_MEM_DISABLE BIT(0) =20 @@ -366,8 +374,8 @@ static void tegra20_channel_vi_buffer_setup(struct tegr= a_vi_channel *chan, case V4L2_PIX_FMT_VYUY: case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_YVYU: - tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS_FIRST, base); - tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS_FIRST, base + chan->st= art_offset); + tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(OUT_1), base); + tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(OUT_1), base + chan->s= tart_offset); break; } } @@ -455,6 +463,7 @@ static void tegra20_camera_capture_setup(struct tegra_v= i_channel *chan) int stride_l =3D chan->format.bytesperline; int stride_c =3D (output_fourcc =3D=3D V4L2_PIX_FMT_YUV420 || output_fourcc =3D=3D V4L2_PIX_FMT_YVU420) ? 1 : 0; + int output_channel =3D OUT_1; int main_output_format; int yuv_output_format; =20 @@ -472,33 +481,33 @@ static void tegra20_camera_capture_setup(struct tegra= _vi_channel *chan) /* Set up raise-on-edge, so we get an interrupt on end of frame. */ tegra20_vi_write(chan, TEGRA_VI_VI_RAISE, VI_VI_RAISE_ON_EDGE); =20 - tegra20_vi_write(chan, TEGRA_VI_VI_FIRST_OUTPUT_CONTROL, + tegra20_vi_write(chan, TEGRA_VI_VI_OUTPUT_CONTROL(output_channel), (chan->vflip ? VI_OUTPUT_V_DIRECTION : 0) | (chan->hflip ? VI_OUTPUT_H_DIRECTION : 0) | yuv_output_format << VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT | main_output_format << VI_OUTPUT_OUTPUT_FORMAT_SFT); =20 /* Set up frame size */ - tegra20_vi_write(chan, TEGRA_VI_FIRST_OUTPUT_FRAME_SIZE, - height << VI_FIRST_OUTPUT_FRAME_HEIGHT_SFT | - width << VI_FIRST_OUTPUT_FRAME_WIDTH_SFT); + tegra20_vi_write(chan, TEGRA_VI_OUTPUT_FRAME_SIZE(output_channel), + height << VI_OUTPUT_FRAME_HEIGHT_SFT | + width << VI_OUTPUT_FRAME_WIDTH_SFT); =20 /* First output memory enabled */ - tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE, 0); + tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE(output_channel), 0); =20 /* Set the number of frames in the buffer */ - tegra20_vi_write(chan, TEGRA_VI_VB0_COUNT_FIRST, 1); + tegra20_vi_write(chan, TEGRA_VI_VB0_COUNT(output_channel), 1); =20 /* Set up buffer frame size */ - tegra20_vi_write(chan, TEGRA_VI_VB0_SIZE_FIRST, - height << VI_VB0_SIZE_FIRST_V_SFT | - width << VI_VB0_SIZE_FIRST_H_SFT); + tegra20_vi_write(chan, TEGRA_VI_VB0_SIZE(output_channel), + height << VI_VB0_SIZE_V_SFT | + width << VI_VB0_SIZE_H_SFT); =20 - tegra20_vi_write(chan, TEGRA_VI_VB0_BUFFER_STRIDE_FIRST, - stride_l << VI_VB0_BUFFER_STRIDE_FIRST_LUMA_SFT | - stride_c << VI_VB0_BUFFER_STRIDE_FIRST_CHROMA_SFT); + tegra20_vi_write(chan, TEGRA_VI_VB0_BUFFER_STRIDE(output_channel), + stride_l << VI_VB0_BUFFER_STRIDE_LUMA_SFT | + stride_c << VI_VB0_BUFFER_STRIDE_CHROMA_SFT); =20 - tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE, 0); + tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE(output_channel), 0); } =20 static int tegra20_vi_start_streaming(struct vb2_queue *vq, u32 count) @@ -607,6 +616,7 @@ static int tegra20_vip_start_streaming(struct tegra_vip= _channel *vip_chan) struct tegra_vi_channel *vi_chan =3D v4l2_get_subdev_hostdata(&vip_chan->= subdev); int width =3D vi_chan->format.width; int height =3D vi_chan->format.height; + int output_channel =3D OUT_1; =20 unsigned int main_input_format; unsigned int yuv_input_format; @@ -637,10 +647,10 @@ static int tegra20_vip_start_streaming(struct tegra_v= ip_channel *vip_chan) GENMASK(9, 2) << VI_DATA_INPUT_SFT); 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:02 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 12/19] staging: media: tegra-video: tegra20: simplify format align calculations Date: Tue, 19 Aug 2025 15:16:24 +0300 Message-ID: <20250819121631.84280-13-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Simplify format align calculations by slightly modifying supported formats structure. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/tegra20.c | 41 ++++++++------------- 1 file changed, 16 insertions(+), 25 deletions(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index 54512d1ecf83..735611c3c47d 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -279,20 +279,8 @@ static void tegra20_fmt_align(struct v4l2_pix_format *= pix, unsigned int bpp) pix->width =3D clamp(pix->width, TEGRA20_MIN_WIDTH, TEGRA20_MAX_WIDTH); pix->height =3D clamp(pix->height, TEGRA20_MIN_HEIGHT, TEGRA20_MAX_HEIGHT= ); =20 - switch (pix->pixelformat) { - case V4L2_PIX_FMT_UYVY: - case V4L2_PIX_FMT_VYUY: - case V4L2_PIX_FMT_YUYV: - case V4L2_PIX_FMT_YVYU: - pix->bytesperline =3D roundup(pix->width, 2) * 2; - pix->sizeimage =3D roundup(pix->width, 2) * 2 * pix->height; - break; - case V4L2_PIX_FMT_YUV420: - case V4L2_PIX_FMT_YVU420: - pix->bytesperline =3D roundup(pix->width, 8); - pix->sizeimage =3D roundup(pix->width, 8) * pix->height * 3 / 2; - break; - } + pix->bytesperline =3D DIV_ROUND_UP(pix->width * bpp, 8); + pix->sizeimage =3D pix->bytesperline * pix->height; } =20 /* @@ -575,20 +563,23 @@ static const struct tegra_vi_ops tegra20_vi_ops =3D { .vi_stop_streaming =3D tegra20_vi_stop_streaming, }; =20 -#define TEGRA20_VIDEO_FMT(MBUS_CODE, BPP, FOURCC) \ -{ \ - .code =3D MEDIA_BUS_FMT_##MBUS_CODE, \ - .bpp =3D BPP, \ - .fourcc =3D V4L2_PIX_FMT_##FOURCC, \ +#define TEGRA20_VIDEO_FMT(DATA_TYPE, BIT_WIDTH, MBUS_CODE, BPP, FOURCC) \ +{ \ + .img_dt =3D TEGRA_IMAGE_DT_##DATA_TYPE, \ + .bit_width =3D BIT_WIDTH, \ + .code =3D MEDIA_BUS_FMT_##MBUS_CODE, \ + .bpp =3D BPP, \ + .fourcc =3D V4L2_PIX_FMT_##FOURCC, \ } =20 static const struct tegra_video_format tegra20_video_formats[] =3D { - TEGRA20_VIDEO_FMT(UYVY8_2X8, 2, UYVY), - TEGRA20_VIDEO_FMT(VYUY8_2X8, 2, VYUY), - TEGRA20_VIDEO_FMT(YUYV8_2X8, 2, YUYV), - TEGRA20_VIDEO_FMT(YVYU8_2X8, 2, YVYU), - TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YUV420), - TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YVU420), + /* YUV422 */ + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 16, UYVY), + TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 16, VYUY), + TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 16, YUYV), + TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 16, YVYU), + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YUV420), + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YVU420), }; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:04 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 13/19] staging: media: tegra-video: tegra20: set VI HW revision Date: Tue, 19 Aug 2025 15:16:25 +0300 Message-ID: <20250819121631.84280-14-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Tegra20, Tegra30 and Tegra114 have VI revision 1. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/tegra20.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index 735611c3c47d..71dcb982c97b 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -587,6 +587,7 @@ const struct tegra_vi_soc tegra20_vi_soc =3D { .nformats =3D ARRAY_SIZE(tegra20_video_formats), .default_video_format =3D &tegra20_video_formats[0], .ops =3D &tegra20_vi_ops, + .hw_revision =3D 1, .vi_max_channels =3D 1, /* parallel input (VIP) */ .vi_max_clk_hz =3D 150000000, .has_h_v_flip =3D true, --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f54.google.com (mail-ej1-f54.google.com [209.85.218.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 56E84346A05; Tue, 19 Aug 2025 12:17:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:06 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 14/19] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Date: Tue, 19 Aug 2025 15:16:26 +0300 Message-ID: <20250819121631.84280-15-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Increase maximum VI clock frequency to 450MHz to allow correct work with high resolution camera sensors. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index 71dcb982c97b..67631e0c9ffc 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -589,7 +589,7 @@ const struct tegra_vi_soc tegra20_vi_soc =3D { .ops =3D &tegra20_vi_ops, .hw_revision =3D 1, .vi_max_channels =3D 1, /* parallel input (VIP) */ - .vi_max_clk_hz =3D 150000000, + .vi_max_clk_hz =3D 450000000, .has_h_v_flip =3D true, }; =20 --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f51.google.com (mail-ej1-f51.google.com [209.85.218.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E70EA34AB18; Tue, 19 Aug 2025 12:17:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 19 Aug 2025 05:17:08 -0700 (PDT) Received: from xeon.. ([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:07 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 15/19] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Date: Tue, 19 Aug 2025 15:16:27 +0300 Message-ID: <20250819121631.84280-16-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Bayer formats (RAW8 and RAW10) and YUV422_8 1X16 versions of existing YUV422_8 2X8. Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/tegra20.c | 71 ++++++++++++++++++++- 1 file changed, 69 insertions(+), 2 deletions(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index 67631e0c9ffc..b466fe7f4504 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -186,6 +186,18 @@ static void tegra20_vi_get_input_formats(struct tegra_= vi_channel *chan, case MEDIA_BUS_FMT_YVYU8_2X8: (*yuv_input_format) =3D VI_INPUT_YUV_INPUT_FORMAT_YVYU; break; + /* RAW8 */ + case MEDIA_BUS_FMT_SBGGR8_1X8: + case MEDIA_BUS_FMT_SGBRG8_1X8: + case MEDIA_BUS_FMT_SGRBG8_1X8: + case MEDIA_BUS_FMT_SRGGB8_1X8: + /* RAW10 */ + case MEDIA_BUS_FMT_SBGGR10_1X10: + case MEDIA_BUS_FMT_SGBRG10_1X10: + case MEDIA_BUS_FMT_SGRBG10_1X10: + case MEDIA_BUS_FMT_SRGGB10_1X10: + (*yuv_input_format) =3D VI_INPUT_INPUT_FORMAT_BAYER; + break; } } =20 @@ -220,6 +232,18 @@ static void tegra20_vi_get_output_formats(struct tegra= _vi_channel *chan, case V4L2_PIX_FMT_YVU420: (*main_output_format) =3D VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR; break; + /* RAW8 */ + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + /* RAW10 */ + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + (*main_output_format) =3D VI_OUTPUT_OUTPUT_FORMAT_VIP_BAYER_DIRECT; + break; } } =20 @@ -300,6 +324,16 @@ static void tegra20_channel_queue_setup(struct tegra_v= i_channel *chan) case V4L2_PIX_FMT_VYUY: case V4L2_PIX_FMT_YUYV: case V4L2_PIX_FMT_YVYU: + /* RAW8 */ + case V4L2_PIX_FMT_SRGGB8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SBGGR8: + /* RAW10 */ + case V4L2_PIX_FMT_SRGGB10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SBGGR10: if (chan->vflip) chan->start_offset +=3D stride * (height - 1); if (chan->hflip) @@ -365,6 +399,19 @@ static void tegra20_channel_vi_buffer_setup(struct teg= ra_vi_channel *chan, tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(OUT_1), base); tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(OUT_1), base + chan->s= tart_offset); break; + /* RAW8 */ + case V4L2_PIX_FMT_SRGGB8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SBGGR8: + /* RAW10 */ + case V4L2_PIX_FMT_SRGGB10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SBGGR10: + tegra20_vi_write(chan, TEGRA_VI_VB0_BASE_ADDRESS(OUT_2), base); + tegra20_vi_write(chan, TEGRA_VI_VB0_START_ADDRESS(OUT_2), base + chan->s= tart_offset); + break; } } =20 @@ -446,12 +493,15 @@ static int tegra20_chan_capture_kthread_start(void *d= ata) static void tegra20_camera_capture_setup(struct tegra_vi_channel *chan) { u32 output_fourcc =3D chan->format.pixelformat; + u32 data_type =3D chan->fmtinfo->img_dt; int width =3D chan->format.width; int height =3D chan->format.height; int stride_l =3D chan->format.bytesperline; int stride_c =3D (output_fourcc =3D=3D V4L2_PIX_FMT_YUV420 || output_fourcc =3D=3D V4L2_PIX_FMT_YVU420) ? 1 : 0; - int output_channel =3D OUT_1; + int output_channel =3D (data_type =3D=3D TEGRA_IMAGE_DT_RAW8 || + data_type =3D=3D TEGRA_IMAGE_DT_RAW10) ? + OUT_2 : OUT_1; int main_output_format; int yuv_output_format; =20 @@ -580,6 +630,20 @@ static const struct tegra_video_format tegra20_video_f= ormats[] =3D { TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 16, YVYU), TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YUV420), TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YVU420), + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_1X16, 16, UYVY), + TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_1X16, 16, VYUY), + TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_1X16, 16, YUYV), + TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_1X16, 16, YVYU), + /* RAW 8 */ + TEGRA20_VIDEO_FMT(RAW8, 8, SRGGB8_1X8, 16, SRGGB8), + TEGRA20_VIDEO_FMT(RAW8, 8, SGRBG8_1X8, 16, SGRBG8), + TEGRA20_VIDEO_FMT(RAW8, 8, SGBRG8_1X8, 16, SGBRG8), + TEGRA20_VIDEO_FMT(RAW8, 8, SBGGR8_1X8, 16, SBGGR8), + /* RAW 10 */ + TEGRA20_VIDEO_FMT(RAW10, 10, SRGGB10_1X10, 16, SRGGB10), + TEGRA20_VIDEO_FMT(RAW10, 10, SGRBG10_1X10, 16, SGRBG10), + TEGRA20_VIDEO_FMT(RAW10, 10, SGBRG10_1X10, 16, SGBRG10), + TEGRA20_VIDEO_FMT(RAW10, 10, SBGGR10_1X10, 16, SBGGR10), }; =20 const struct tegra_vi_soc tegra20_vi_soc =3D { @@ -606,9 +670,12 @@ const struct tegra_vi_soc tegra20_vi_soc =3D { static int tegra20_vip_start_streaming(struct tegra_vip_channel *vip_chan) { struct tegra_vi_channel *vi_chan =3D v4l2_get_subdev_hostdata(&vip_chan->= subdev); + u32 data_type =3D vi_chan->fmtinfo->img_dt; int width =3D vi_chan->format.width; int height =3D vi_chan->format.height; - int output_channel =3D OUT_1; + int output_channel =3D (data_type =3D=3D TEGRA_IMAGE_DT_RAW8 || + data_type =3D=3D TEGRA_IMAGE_DT_RAW10) ? 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:09 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 16/19] staging: media: tegra-video: tegra20: adjust luma buffer stride Date: Tue, 19 Aug 2025 15:16:28 +0300 Message-ID: <20250819121631.84280-17-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Luma buffer stride is calculated by multiplying height in pixels of image by bytes per line. Adjust that value accordingly. Signed-off-by: Svyatoslav Ryhel Reviewed-by: Mikko Perttunen --- drivers/staging/media/tegra-video/tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index b466fe7f4504..a06afe91d2de 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -496,7 +496,7 @@ static void tegra20_camera_capture_setup(struct tegra_v= i_channel *chan) u32 data_type =3D chan->fmtinfo->img_dt; int width =3D chan->format.width; int height =3D chan->format.height; - int stride_l =3D chan->format.bytesperline; + int stride_l =3D chan->format.bytesperline * height; int stride_c =3D (output_fourcc =3D=3D V4L2_PIX_FMT_YUV420 || output_fourcc =3D=3D V4L2_PIX_FMT_YVU420) ? 1 : 0; int output_channel =3D (data_type =3D=3D TEGRA_IMAGE_DT_RAW8 || --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f42.google.com (mail-ej1-f42.google.com [209.85.218.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44FC33570AD; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:11 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 17/19] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Date: Tue, 19 Aug 2025 15:16:29 +0300 Message-ID: <20250819121631.84280-18-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Document CSI hw block found in Tegra20 and Tegra30 SoC. Signed-off-by: Svyatoslav Ryhel --- .../display/tegra/nvidia,tegra210-csi.yaml | 78 +++++++++++++++---- 1 file changed, 63 insertions(+), 15 deletions(-) diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra21= 0-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra21= 0-csi.yaml index fa07a40d1004..a5669447a33b 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.y= aml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.y= aml @@ -16,30 +16,78 @@ properties: =20 compatible: enum: + - nvidia,tegra20-csi + - nvidia,tegra30-csi - nvidia,tegra210-csi =20 reg: maxItems: 1 =20 - clocks: - items: - - description: module clock - - description: A/B lanes clock - - description: C/D lanes clock - - description: E lane clock - - description: test pattern generator clock - - clock-names: - items: - - const: csi - - const: cilab - - const: cilcd - - const: cile - - const: csi_tpg + clocks: true + clock-names: true =20 power-domains: maxItems: 1 =20 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra20-csi + then: + properties: + clocks: + items: + - description: module clock + + clock-names: + items: + - const: csi + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra30-csi + then: + properties: + clocks: + items: + - description: module clock + - description: PAD A clock + - description: PAD B clock + + clock-names: + items: + - const: csi + - const: csia_pad + - const: csib_pad + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra210-csi + then: + properties: + clocks: + items: + - description: module clock + - description: A/B lanes clock + - description: C/D lanes clock + - description: E lane clock + - description: test pattern generator clock + + clock-names: + items: + - const: csi + - const: cilab + - const: cilcd + - const: cile + - const: csi_tpg + additionalProperties: false =20 required: --=20 2.48.1 From nobody Sat Oct 4 06:35:15 2025 Received: from mail-ej1-f48.google.com (mail-ej1-f48.google.com [209.85.218.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0560350858; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:12 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 18/19] ARM: tegra: add CSI binding for Tegra20 and Tegra30 Date: Tue, 19 Aug 2025 15:16:30 +0300 Message-ID: <20250819121631.84280-19-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CSI node to Tegra20 and Tegra30 device trees. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra20.dtsi | 17 ++++++++++++++++- arch/arm/boot/dts/nvidia/tegra30.dtsi | 19 ++++++++++++++++++- 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/nvidia/tegra20.dtsi b/arch/arm/boot/dts/nvid= ia/tegra20.dtsi index 606839fd40bb..d00786368115 100644 --- a/arch/arm/boot/dts/nvidia/tegra20.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra20.dtsi @@ -64,7 +64,7 @@ mpe@54040000 { =20 vi@54080000 { compatible =3D "nvidia,tegra20-vi"; - reg =3D <0x54080000 0x00040000>; + reg =3D <0x54080000 0x00000800>; interrupts =3D ; clocks =3D <&tegra_car TEGRA20_CLK_VI>; resets =3D <&tegra_car 20>; @@ -72,6 +72,21 @@ vi@54080000 { power-domains =3D <&pd_venc>; operating-points-v2 =3D <&vi_dvfs_opp_table>; status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x0 0x54080000 0x4000>; + + csi@800 { + compatible =3D "nvidia,tegra20-csi"; + reg =3D <0x800 0x200>; + clocks =3D <&tegra_car TEGRA20_CLK_CSI>; + clock-names =3D "csi"; + power-domains =3D <&pd_venc>; + + status =3D "disabled"; + }; }; =20 /* DSI MIPI calibration logic is a part of VI/CSI */ diff --git a/arch/arm/boot/dts/nvidia/tegra30.dtsi b/arch/arm/boot/dts/nvid= ia/tegra30.dtsi index d9223bd7cf3b..c3e9212d5edf 100644 --- a/arch/arm/boot/dts/nvidia/tegra30.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra30.dtsi @@ -151,7 +151,7 @@ mpe@54040000 { =20 vi@54080000 { compatible =3D "nvidia,tegra30-vi"; - reg =3D <0x54080000 0x00040000>; + reg =3D <0x54080000 0x00000800>; interrupts =3D ; clocks =3D <&tegra_car TEGRA30_CLK_VI>; resets =3D <&tegra_car 20>; @@ -162,6 +162,23 @@ vi@54080000 { iommus =3D <&mc TEGRA_SWGROUP_VI>; =20 status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <1>; + + ranges =3D <0x0 0x54080000 0x4000>; + + csi@800 { + compatible =3D "nvidia,tegra30-csi"; + reg =3D <0x800 0x200>; + clocks =3D <&tegra_car TEGRA30_CLK_CSI>, + <&tegra_car TEGRA30_CLK_CSIA_PAD>, + <&tegra_car TEGRA30_CLK_CSIB_PAD>; + clock-names =3D "csi", "csia_pad", "csib_pad"; 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([188.163.112.76]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-afcdce72cbbsm1012018666b.35.2025.08.19.05.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 05:17:14 -0700 (PDT) From: Svyatoslav Ryhel To: Thierry Reding , Thierry Reding , Mikko Perttunen , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Peter De Schrijver , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Svyatoslav Ryhel , Dmitry Osipenko , Charan Pedumuru Cc: linux-media@vger.kernel.org, linux-tegra@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Subject: [PATCH v1 19/19] staging: media: tegra-video: add CSI support for Tegra20 and Tegra30 Date: Tue, 19 Aug 2025 15:16:31 +0300 Message-ID: <20250819121631.84280-20-clamor95@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250819121631.84280-1-clamor95@gmail.com> References: <20250819121631.84280-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Add support for MIPI CSI device found in Tegra20 and Tegra30 SoC. Co-developed-by: Jonas Schw=C3=B6bel Signed-off-by: Jonas Schw=C3=B6bel Signed-off-by: Svyatoslav Ryhel --- drivers/staging/media/tegra-video/csi.c | 12 + drivers/staging/media/tegra-video/tegra20.c | 575 ++++++++++++++++++-- drivers/staging/media/tegra-video/vi.h | 2 + drivers/staging/media/tegra-video/video.c | 2 + 4 files changed, 553 insertions(+), 38 deletions(-) diff --git a/drivers/staging/media/tegra-video/csi.c b/drivers/staging/medi= a/tegra-video/csi.c index 2f9907a20db1..714ce52a793c 100644 --- a/drivers/staging/media/tegra-video/csi.c +++ b/drivers/staging/media/tegra-video/csi.c @@ -826,11 +826,23 @@ static void tegra_csi_remove(struct platform_device *= pdev) pm_runtime_disable(&pdev->dev); } =20 +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) +extern const struct tegra_csi_soc tegra20_csi_soc; +#endif +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) +extern const struct tegra_csi_soc tegra30_csi_soc; +#endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) extern const struct tegra_csi_soc tegra210_csi_soc; #endif =20 static const struct of_device_id tegra_csi_of_id_table[] =3D { +#if defined(CONFIG_ARCH_TEGRA_2x_SOC) + { .compatible =3D "nvidia,tegra20-csi", .data =3D &tegra20_csi_soc }, +#endif +#if defined(CONFIG_ARCH_TEGRA_3x_SOC) + { .compatible =3D "nvidia,tegra30-csi", .data =3D &tegra30_csi_soc }, +#endif #if defined(CONFIG_ARCH_TEGRA_210_SOC) { .compatible =3D "nvidia,tegra210-csi", .data =3D &tegra210_csi_soc }, #endif diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/= media/tegra-video/tegra20.c index a06afe91d2de..e528ba280ae4 100644 --- a/drivers/staging/media/tegra-video/tegra20.c +++ b/drivers/staging/media/tegra-video/tegra20.c @@ -4,6 +4,9 @@ * * Copyright (C) 2023 SKIDATA GmbH * Author: Luca Ceresoli + * + * Copyright (c) 2025 Svyatoslav Ryhel + * Copyright (c) 2025 Jonas Schw=C3=B6bel */ =20 /* @@ -12,12 +15,16 @@ */ =20 #include +#include +#include #include #include +#include #include #include #include =20 +#include "csi.h" #include "vip.h" #include "vi.h" =20 @@ -42,6 +49,9 @@ enum { #define VI_CONT_SYNCPT_OUT_CONTINUOUS_SYNCPT BIT(8) #define VI_CONT_SYNCPT_OUT_SYNCPT_IDX_SFT 0 =20 +#define TEGRA_VI_CONT_SYNCPT_CSI_PP_FRAME_START(n) (0x0070 + (n) * 8) +#define TEGRA_VI_CONT_SYNCPT_CSI_PP_FRAME_END(n) (0x0074 + (n) * 8) + #define TEGRA_VI_VI_INPUT_CONTROL 0x0088 #define VI_INPUT_FIELD_DETECT BIT(27) #define VI_INPUT_BT656 BIT(25) @@ -87,6 +97,8 @@ enum { #define VI_OUTPUT_OUTPUT_FORMAT_SFT 0 #define VI_OUTPUT_OUTPUT_FORMAT_YUV422POST (3 << VI_OUTPUT_OUTPUT_FO= RMAT_SFT) #define VI_OUTPUT_OUTPUT_FORMAT_YUV420PLANAR (6 << VI_OUTPUT_OUTPUT_= FORMAT_SFT) +#define VI_OUTPUT_OUTPUT_FORMAT_CSI_PPA_BAYER (7 << VI_OUTPUT_OUTPUT= _FORMAT_SFT) +#define VI_OUTPUT_OUTPUT_FORMAT_CSI_PPB_BAYER (8 << VI_OUTPUT_OUTPUT= _FORMAT_SFT) #define VI_OUTPUT_OUTPUT_FORMAT_VIP_BAYER_DIRECT (9 << VI_OUTPUT_OUT= PUT_FORMAT_SFT) =20 #define TEGRA_VI_VIP_H_ACTIVE 0x00a4 @@ -151,8 +163,106 @@ enum { #define TEGRA_VI_VI_RAISE 0x01ac #define VI_VI_RAISE_ON_EDGE BIT(0) =20 +#define TEGRA_VI_CSI_PP_RAISE_FRAME_START(n) (0x01d8 + (n) * 8) +#define TEGRA_VI_CSI_PP_RAISE_FRAME_END(n) (0x01dc + (n) * 8) +#define TEGRA_VI_CSI_PP_H_ACTIVE(n) (0x01e8 + (n) * 8) +#define TEGRA_VI_CSI_PP_V_ACTIVE(n) (0x01ec + (n) * 8) + +/* Tegra20 CSI registers: Starts from 0x800, offset 0x0 */ +#define TEGRA_CSI_VI_INPUT_STREAM_CONTROL 0x0000 +#define TEGRA_CSI_HOST_INPUT_STREAM_CONTROL 0x0008 +#define TEGRA_CSI_INPUT_STREAM_CONTROL(n) (0x0010 + (n) * 0x2c) +#define CSI_SKIP_PACKET_THRESHOLD(n) (((n) & 0xff) << 16) +#define TEGRA_CSI_PIXEL_STREAM_CONTROL0(n) (0x0018 + (n) * 0x2c) +#define CSI_PP_PAD_FRAME_PAD0S (0 << 28) +#define CSI_PP_PAD_FRAME_PAD1S (1 << 28) +#define CSI_PP_PAD_FRAME_NOPAD (2 << 28) +#define CSI_PP_HEADER_EC_ENABLE BIT(27) +#define CSI_PP_PAD_SHORT_LINE_PAD0S (0 << 24) +#define CSI_PP_PAD_SHORT_LINE_PAD1S (1 << 24) +#define CSI_PP_PAD_SHORT_LINE_NOPAD (2 << 24) +#define CSI_PP_EMBEDDED_DATA_EMBEDDED BIT(20) +#define CSI_PP_OUTPUT_FORMAT_ARBITRARY (0 << 16) +#define CSI_PP_OUTPUT_FORMAT_PIXEL (1 << 16) +#define CSI_PP_OUTPUT_FORMAT_PIXEL_REP (2 << 16) +#define CSI_PP_OUTPUT_FORMAT_STORE (3 << 16) +#define CSI_PP_VIRTUAL_CHANNEL_ID(n) (((n) - 1) << 14) +#define CSI_PP_DATA_TYPE(n) ((n) << 8) +#define CSI_PP_CRC_CHECK_ENABLE BIT(7) +#define CSI_PP_WORD_COUNT_HEADER BIT(6) +#define CSI_PP_DATA_IDENTIFIER_ENABLE BIT(5) +#define CSI_PP_PACKET_HEADER_SENT BIT(4) +#define TEGRA_CSI_PIXEL_STREAM_CONTROL1(n) (0x001c + (n) * 0x2c) +#define TEGRA_CSI_PIXEL_STREAM_WORD_COUNT(n) (0x0020 + (n) * 0x2c) +#define TEGRA_CSI_PIXEL_STREAM_GAP(n) (0x0024 + (n) * 0x2c) +#define CSI_PP_FRAME_MIN_GAP(n) (((n) & 0xffff) << 16) +#define CSI_PP_LINE_MIN_GAP(n) (((n) & 0xffff)) +#define TEGRA_CSI_PIXEL_STREAM_PP_COMMAND(n) (0x0028 + (n) * 0x2c) +#define CSI_PP_START_MARKER_FRAME_MAX(n) (((n) & 0xf) << 12) +#define CSI_PP_START_MARKER_FRAME_MIN(n) (((n) & 0xf) << 8) +#define CSI_PP_VSYNC_START_MARKER BIT(4) +#define CSI_PP_SINGLE_SHOT BIT(2) +#define CSI_PP_NOP 0 +#define CSI_PP_ENABLE 1 +#define CSI_PP_DISABLE 2 +#define CSI_PP_RST 3 +#define TEGRA_CSI_PHY_CIL_COMMAND 0x0068 +#define CSI_A_PHY_CIL_NOP 0x0 +#define CSI_A_PHY_CIL_ENABLE 0x1 +#define CSI_A_PHY_CIL_DISABLE 0x2 +#define CSI_A_PHY_CIL_ENABLE_MASK 0x3 +#define CSI_B_PHY_CIL_NOP (0x0 << 16) +#define CSI_B_PHY_CIL_ENABLE (0x1 << 16) +#define CSI_B_PHY_CIL_DISABLE (0x2 << 16) +#define CSI_B_PHY_CIL_ENABLE_MASK (0x3 << 16) +#define TEGRA_CSI_PHY_CIL_CONTROL0(n) (0x006c + (n) * 4) +#define CSI_CONTINUOUS_CLOCK_MODE_ENABLE BIT(5) +#define TEGRA_CSI_CSI_PIXEL_PARSER_STATUS 0x0078 +#define TEGRA_CSI_CSI_CIL_STATUS 0x007c +#define CSI_MIPI_AUTO_CAL_DONE BIT(15) +#define TEGRA_CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK 0x0080 +#define TEGRA_CSI_CSI_CIL_INTERRUPT_MASK 0x0084 +#define TEGRA_CSI_CSI_READONLY_STATUS 0x0088 +#define TEGRA_CSI_ESCAPE_MODE_COMMAND 0x008c +#define TEGRA_CSI_ESCAPE_MODE_DATA 0x0090 +#define TEGRA_CSI_CIL_PAD_CONFIG0(n) (0x0094 + (n) * 8) +#define TEGRA_CSI_CIL_PAD_CONFIG1(n) (0x0098 + (n) * 8) +#define TEGRA_CSI_CIL_PAD_CONFIG 0x00a4 +#define TEGRA_CSI_CILA_MIPI_CAL_CONFIG 0x00a8 +#define TEGRA_CSI_CILB_MIPI_CAL_CONFIG 0x00ac +#define CSI_CIL_MIPI_CAL_STARTCAL BIT(31) +#define CSI_CIL_MIPI_CAL_OVERIDE_A BIT(30) +#define CSI_CIL_MIPI_CAL_OVERIDE_B BIT(30) +#define CSI_CIL_MIPI_CAL_NOISE_FLT(n) (((n) & 0xf) << 26) +#define CSI_CIL_MIPI_CAL_PRESCALE(n) (((n) & 0x3) << 24) +#define CSI_CIL_MIPI_CAL_SEL_A BIT(21) +#define CSI_CIL_MIPI_CAL_SEL_B BIT(21) +#define CSI_CIL_MIPI_CAL_HSPDOS(n) (((n) & 0x1f) << 16) +#define CSI_CIL_MIPI_CAL_HSPUOS(n) (((n) & 0x1f) << 8) +#define CSI_CIL_MIPI_CAL_TERMOS(n) (((n) & 0x1f)) +#define TEGRA_CSI_CIL_MIPI_CAL_STATUS 0x00b0 +#define TEGRA_CSI_CLKEN_OVERRIDE 0x00b4 +#define TEGRA_CSI_DEBUG_CONTROL 0x00b8 +#define CSI_DEBUG_CONTROL_DEBUG_EN_ENABLED BIT(0) +#define CSI_DEBUG_CONTROL_CLR_DBG_CNT_0 BIT(4) +#define CSI_DEBUG_CONTROL_CLR_DBG_CNT_1 BIT(5) +#define CSI_DEBUG_CONTROL_CLR_DBG_CNT_2 BIT(6) +#define CSI_DEBUG_CONTROL_DBG_CNT_SEL(n, v) ((v) << (8 + 8 * (n))) +#define TEGRA_CSI_DEBUG_COUNTER(n) (0x00bc + (n) * 4) +#define TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME(n) (0x00c8 + (n) * 4) +#define CSI_PP_EXP_FRAME_HEIGHT(n) (((n) & 0x1fff) << 16) +#define CSI_PP_MAX_CLOCKS(n) (((n) & 0xfff) << 4) +#define CSI_PP_LINE_TIMEOUT_ENABLE BIT(0) +#define TEGRA_CSI_DSI_MIPI_CAL_CONFIG 0x00d0 +#define TEGRA_CSI_MIPIBIAS_PAD_CONFIG0 0x00d4 +#define CSI_PAD_DRIV_DN_REF(n) (((n) & 0x7) << 16) +#define CSI_PAD_DRIV_UP_REF(n) (((n) & 0x7) << 8) +#define CSI_PAD_TERM_REF(n) (((n) & 0x7) << 0) +#define TEGRA_CSI_CSI_CILA_STATUS 0x00d8 +#define TEGRA_CSI_CSI_CILB_STATUS 0x00dc + /* -----------------------------------------------------------------------= --- - * VI + * Read and Write helpers */ =20 static void tegra20_vi_write(struct tegra_vi_channel *chan, unsigned int a= ddr, u32 val) @@ -160,6 +270,25 @@ static void tegra20_vi_write(struct tegra_vi_channel *= chan, unsigned int addr, u writel(val, chan->vi->iomem + addr); } =20 +static int __maybe_unused tegra20_vi_read(struct tegra_vi_channel *chan, u= nsigned int addr) +{ + return readl(chan->vi->iomem + addr); +} + +static void tegra20_csi_write(struct tegra_csi_channel *csi_chan, unsigned= int addr, u32 val) +{ + writel(val, csi_chan->csi->iomem + addr); +} + +static int __maybe_unused tegra20_csi_read(struct tegra_csi_channel *csi_c= han, unsigned int addr) +{ + return readl(csi_chan->csi->iomem + addr); +} + +/* -----------------------------------------------------------------------= --- + * VI + */ + /* * Get the main input format (YUV/RGB...) and the YUV variant as values to * be written into registers for the current VI input mbus code. @@ -282,20 +411,27 @@ static int tegra20_vi_enable(struct tegra_vi *vi, boo= l on) static int tegra20_channel_host1x_syncpt_init(struct tegra_vi_channel *cha= n) { struct tegra_vi *vi =3D chan->vi; - struct host1x_syncpt *out_sp; + struct host1x_syncpt *out_sp, *fs_sp; =20 out_sp =3D host1x_syncpt_request(&vi->client, HOST1X_SYNCPT_CLIENT_MANAGE= D); if (!out_sp) - return dev_err_probe(vi->dev, -ENOMEM, "failed to request syncpoint\n"); + return dev_err_probe(vi->dev, -ENOMEM, "failed to request mw ack syncpoi= nt\n"); =20 chan->mw_ack_sp[0] =3D out_sp; =20 + fs_sp =3D host1x_syncpt_request(&vi->client, HOST1X_SYNCPT_CLIENT_MANAGED= ); + if (!fs_sp) + return dev_err_probe(vi->dev, -ENOMEM, "failed to request frame start sy= ncpoint\n"); + + chan->frame_start_sp[0] =3D fs_sp; + return 0; } =20 static void tegra20_channel_host1x_syncpt_free(struct tegra_vi_channel *ch= an) { host1x_syncpt_put(chan->mw_ack_sp[0]); + host1x_syncpt_put(chan->frame_start_sp[0]); } =20 static void tegra20_fmt_align(struct v4l2_pix_format *pix, unsigned int bp= p) @@ -418,30 +554,60 @@ static void tegra20_channel_vi_buffer_setup(struct te= gra_vi_channel *chan, static int tegra20_channel_capture_frame(struct tegra_vi_channel *chan, struct tegra_channel_buffer *buf) { + struct v4l2_subdev *csi_subdev =3D NULL; + struct tegra_csi_channel *csi_chan =3D NULL; + u32 port; int err; =20 - chan->next_out_sp_idx++; + csi_subdev =3D tegra_channel_get_remote_csi_subdev(chan); + if (csi_subdev) { + /* CSI subdevs are named after nodes, channel@0 or channel@1 */ + if (!strncmp(csi_subdev->name, "channel", 7)) { + csi_chan =3D to_csi_chan(csi_subdev); + port =3D csi_chan->csi_port_nums[0] & 1; + } + } =20 tegra20_channel_vi_buffer_setup(chan, buf); =20 - tegra20_vi_write(chan, TEGRA_VI_CAMERA_CONTROL, VI_CAMERA_CONTROL_VIP_ENA= BLE); + if (csi_chan) { + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND(port), + CSI_PP_START_MARKER_FRAME_MAX(0xf) | + CSI_PP_SINGLE_SHOT | CSI_PP_ENABLE); + + chan->next_fs_sp_idx++; + err =3D host1x_syncpt_wait(chan->frame_start_sp[0], chan->next_fs_sp_idx, + TEGRA_VI_SYNCPT_WAIT_TIMEOUT, NULL); + if (err) { + host1x_syncpt_incr(chan->frame_start_sp[0]); + if (err !=3D -ERESTARTSYS) + dev_err_ratelimited(&chan->video.dev, + "frame start syncpt timeout: %d\n", err); + } + + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND(port), + CSI_PP_START_MARKER_FRAME_MAX(0xf) | + CSI_PP_DISABLE); + } else { + tegra20_vi_write(chan, TEGRA_VI_CAMERA_CONTROL, VI_CAMERA_CONTROL_VIP_EN= ABLE); + } =20 - /* Wait for syncpt counter to reach frame start event threshold */ + chan->next_out_sp_idx++; err =3D host1x_syncpt_wait(chan->mw_ack_sp[0], chan->next_out_sp_idx, TEGRA_VI_SYNCPT_WAIT_TIMEOUT, NULL); if (err) { host1x_syncpt_incr(chan->mw_ack_sp[0]); - dev_err_ratelimited(&chan->video.dev, "frame start syncpt timeout: %d\n"= , err); - release_buffer(chan, buf, VB2_BUF_STATE_ERROR); - return err; + if (err !=3D -ERESTARTSYS) + dev_err_ratelimited(&chan->video.dev, "mw ack syncpt timeout: %d\n", er= r); } =20 - tegra20_vi_write(chan, TEGRA_VI_CAMERA_CONTROL, - VI_CAMERA_CONTROL_STOP_CAPTURE | VI_CAMERA_CONTROL_VIP_ENABLE); + if (!csi_chan) + tegra20_vi_write(chan, TEGRA_VI_CAMERA_CONTROL, + VI_CAMERA_CONTROL_STOP_CAPTURE | VI_CAMERA_CONTROL_VIP_ENABLE); =20 release_buffer(chan, buf, VB2_BUF_STATE_DONE); =20 - return 0; + return err; } =20 static int tegra20_chan_capture_kthread_start(void *data) @@ -502,28 +668,6 @@ static void tegra20_camera_capture_setup(struct tegra_= vi_channel *chan) int output_channel =3D (data_type =3D=3D TEGRA_IMAGE_DT_RAW8 || data_type =3D=3D TEGRA_IMAGE_DT_RAW10) ? OUT_2 : OUT_1; - int main_output_format; - int yuv_output_format; - - tegra20_vi_get_output_formats(chan, &main_output_format, &yuv_output_form= at); - - /* - * Set up low pass filter. Use 0x240 for chromaticity and 0x240 - * for luminance, which is the default and means not to touch - * anything. - */ - tegra20_vi_write(chan, TEGRA_VI_H_LPF_CONTROL, - 0x0240 << VI_H_LPF_CONTROL_LUMA_SFT | - 0x0240 << VI_H_LPF_CONTROL_CHROMA_SFT); - - /* Set up raise-on-edge, so we get an interrupt on end of frame. */ - tegra20_vi_write(chan, TEGRA_VI_VI_RAISE, VI_VI_RAISE_ON_EDGE); - - tegra20_vi_write(chan, TEGRA_VI_VI_OUTPUT_CONTROL(output_channel), - (chan->vflip ? VI_OUTPUT_V_DIRECTION : 0) | - (chan->hflip ? VI_OUTPUT_H_DIRECTION : 0) | - yuv_output_format << VI_OUTPUT_YUV_OUTPUT_FORMAT_SFT | - main_output_format << VI_OUTPUT_OUTPUT_FORMAT_SFT); =20 /* Set up frame size */ tegra20_vi_write(chan, TEGRA_VI_OUTPUT_FRAME_SIZE(output_channel), @@ -548,24 +692,148 @@ static void tegra20_camera_capture_setup(struct tegr= a_vi_channel *chan) tegra20_vi_write(chan, TEGRA_VI_VI_ENABLE(output_channel), 0); } =20 +static int tegra20_csi_pad_calibration(struct tegra_csi_channel *csi_chan) +{ + struct tegra_csi *csi =3D csi_chan->csi; + void __iomem *cil_status_reg =3D csi_chan->csi->iomem + TEGRA_CSI_CSI_CIL= _STATUS; + unsigned int port =3D csi_chan->csi_port_nums[0] & 1; + u32 value, pp, cil; + int ret; + + tegra20_csi_write(csi_chan, TEGRA_CSI_DSI_MIPI_CAL_CONFIG, + CSI_CIL_MIPI_CAL_HSPDOS(4) | + CSI_CIL_MIPI_CAL_HSPUOS(3) | + CSI_CIL_MIPI_CAL_TERMOS(0)); + tegra20_csi_write(csi_chan, TEGRA_CSI_MIPIBIAS_PAD_CONFIG0, + CSI_PAD_DRIV_DN_REF(5) | + CSI_PAD_DRIV_UP_REF(7) | + CSI_PAD_TERM_REF(0)); + + /* CSI B */ + value =3D CSI_CIL_MIPI_CAL_HSPDOS(0) | + CSI_CIL_MIPI_CAL_HSPUOS(0) | + CSI_CIL_MIPI_CAL_TERMOS(4); + + if (port =3D=3D PORT_B || csi_chan->numlanes =3D=3D 4) + value |=3D CSI_CIL_MIPI_CAL_SEL_B; + + tegra20_csi_write(csi_chan, TEGRA_CSI_CILB_MIPI_CAL_CONFIG, value); + + /* CSI A */ + value =3D CSI_CIL_MIPI_CAL_STARTCAL | + CSI_CIL_MIPI_CAL_NOISE_FLT(0xa) | + CSI_CIL_MIPI_CAL_PRESCALE(0x2) | + CSI_CIL_MIPI_CAL_HSPDOS(0) | + CSI_CIL_MIPI_CAL_HSPUOS(0) | + CSI_CIL_MIPI_CAL_TERMOS(4); + + if (port =3D=3D PORT_A) + value |=3D CSI_CIL_MIPI_CAL_SEL_A; + + tegra20_csi_write(csi_chan, TEGRA_CSI_CILA_MIPI_CAL_CONFIG, value); + + ret =3D readl_relaxed_poll_timeout(cil_status_reg, value, + value & CSI_MIPI_AUTO_CAL_DONE, 50, 250000); + if (ret < 0) { + dev_warn(csi->dev, "MIPI calibration timeout!\n"); + goto exit; + } + + /* clear status */ + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_CIL_STATUS, value); + ret =3D readl_relaxed_poll_timeout(cil_status_reg, value, + !(value & CSI_MIPI_AUTO_CAL_DONE), 50, 250000); + if (ret < 0) { + dev_warn(csi->dev, "MIPI calibration status timeout!\n"); + goto exit; + } + + pp =3D tegra20_csi_read(csi_chan, TEGRA_CSI_CSI_PIXEL_PARSER_STATUS); + cil =3D tegra20_csi_read(csi_chan, TEGRA_CSI_CSI_CIL_STATUS); + if (pp | cil) { + dev_warn(csi->dev, "Calibration status not been cleared!\n"); + ret =3D -EINVAL; + goto exit; + } + +exit: + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_CIL_STATUS, pp); + + /* un-select to avoid interference with DSI */ + tegra20_csi_write(csi_chan, TEGRA_CSI_CILB_MIPI_CAL_CONFIG, + CSI_CIL_MIPI_CAL_HSPDOS(0) | + CSI_CIL_MIPI_CAL_HSPUOS(0) | + CSI_CIL_MIPI_CAL_TERMOS(4)); + + tegra20_csi_write(csi_chan, TEGRA_CSI_CILA_MIPI_CAL_CONFIG, + CSI_CIL_MIPI_CAL_NOISE_FLT(0xa) | + CSI_CIL_MIPI_CAL_PRESCALE(0x2) | + CSI_CIL_MIPI_CAL_HSPDOS(0) | + CSI_CIL_MIPI_CAL_HSPUOS(0) | + CSI_CIL_MIPI_CAL_TERMOS(4)); + + return ret; +} + static int tegra20_vi_start_streaming(struct vb2_queue *vq, u32 count) { struct tegra_vi_channel *chan =3D vb2_get_drv_priv(vq); struct media_pipeline *pipe =3D &chan->video.pipe; + struct v4l2_subdev *csi_subdev, *src_subdev; + struct tegra_csi_channel *csi_chan =3D NULL; int err; =20 + csi_subdev =3D tegra_channel_get_remote_csi_subdev(chan); + if (csi_subdev) { + if (!strncmp(csi_subdev->name, "channel", 7)) + csi_chan =3D to_csi_chan(csi_subdev); + } + + chan->next_fs_sp_idx =3D host1x_syncpt_read(chan->frame_start_sp[0]); chan->next_out_sp_idx =3D host1x_syncpt_read(chan->mw_ack_sp[0]); =20 err =3D video_device_pipeline_start(&chan->video, pipe); if (err) goto error_pipeline_start; =20 - tegra20_camera_capture_setup(chan); + /* + * Set up low pass filter. Use 0x240 for chromaticity and 0x240 + * for luminance, which is the default and means not to touch + * anything. + */ + tegra20_vi_write(chan, TEGRA_VI_H_LPF_CONTROL, + 0x0240 << VI_H_LPF_CONTROL_LUMA_SFT | + 0x0240 << VI_H_LPF_CONTROL_CHROMA_SFT); + + /* Set up raise-on-edge, so we get an interrupt on end of frame. */ + tegra20_vi_write(chan, TEGRA_VI_VI_RAISE, VI_VI_RAISE_ON_EDGE); =20 err =3D tegra_channel_set_stream(chan, true); if (err) goto error_set_stream; =20 + tegra20_camera_capture_setup(chan); + + if (csi_chan) { + /* + * TRM has incorrectly documented to wait for done status from + * calibration logic after CSI interface power on. + * As per the design, calibration results are latched and applied + * to the pads only when the link is in LP11 state which will happen + * during the sensor stream-on. + * CSI subdev stream-on triggers start of MIPI pads calibration. + * Wait for calibration to finish here after sensor subdev stream-on. + */ + src_subdev =3D tegra_channel_get_remote_source_subdev(chan); + if (!src_subdev->s_stream_enabled) { + err =3D v4l2_subdev_call(src_subdev, video, s_stream, true); + if (err < 0 && err !=3D -ENOIOCTLCMD) + goto error_set_stream; + } + + tegra20_csi_pad_calibration(csi_chan); + } + chan->sequence =3D 0; =20 chan->kthread_start_capture =3D kthread_run(tegra20_chan_capture_kthread_= start, @@ -592,12 +860,17 @@ static int tegra20_vi_start_streaming(struct vb2_queu= e *vq, u32 count) static void tegra20_vi_stop_streaming(struct vb2_queue *vq) { struct tegra_vi_channel *chan =3D vb2_get_drv_priv(vq); + struct v4l2_subdev *src_subdev; =20 if (chan->kthread_start_capture) { kthread_stop(chan->kthread_start_capture); chan->kthread_start_capture =3D NULL; } =20 + src_subdev =3D tegra_channel_get_remote_source_subdev(chan); + if (src_subdev->s_stream_enabled) + v4l2_subdev_call(src_subdev, video, s_stream, false); + tegra_channel_release_buffers(chan, VB2_BUF_STATE_ERROR); tegra_channel_set_stream(chan, false); video_device_pipeline_stop(&chan->video); @@ -652,11 +925,231 @@ const struct tegra_vi_soc tegra20_vi_soc =3D { .default_video_format =3D &tegra20_video_formats[0], .ops =3D &tegra20_vi_ops, .hw_revision =3D 1, - .vi_max_channels =3D 1, /* parallel input (VIP) */ + .vi_max_channels =3D 4, /* parallel input (VIP), CSIA, CSIB, HOST */ .vi_max_clk_hz =3D 450000000, .has_h_v_flip =3D true, }; =20 +/* -----------------------------------------------------------------------= --- + * CSI + */ +static void tegra20_csi_capture_clean(struct tegra_csi_channel *csi_chan) +{ + tegra20_csi_write(csi_chan, TEGRA_CSI_VI_INPUT_STREAM_CONTROL, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_HOST_INPUT_STREAM_CONTROL, 0); + + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_PIXEL_PARSER_STATUS, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_CIL_STATUS, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_PIXEL_PARSER_INTERRUPT_MASK, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_CIL_INTERRUPT_MASK, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_READONLY_STATUS, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_ESCAPE_MODE_COMMAND, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_ESCAPE_MODE_DATA, 0); + + tegra20_csi_write(csi_chan, TEGRA_CSI_CIL_PAD_CONFIG, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_CIL_MIPI_CAL_STATUS, 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_CLKEN_OVERRIDE, 0); + + tegra20_csi_write(csi_chan, TEGRA_CSI_DEBUG_CONTROL, + CSI_DEBUG_CONTROL_CLR_DBG_CNT_0 | + CSI_DEBUG_CONTROL_CLR_DBG_CNT_1 | + CSI_DEBUG_CONTROL_CLR_DBG_CNT_2); +} + +static int tegra20_csi_port_start_streaming(struct tegra_csi_channel *csi_= chan, + u8 portno) +{ + struct tegra_vi_channel *vi_chan =3D v4l2_get_subdev_hostdata(&csi_chan->= subdev); + int width =3D vi_chan->format.width; + int height =3D vi_chan->format.height; + u32 data_type =3D vi_chan->fmtinfo->img_dt; + u32 word_count =3D (width * vi_chan->fmtinfo->bit_width) / 8; + int output_channel =3D OUT_1; + + unsigned int main_output_format, yuv_output_format; + unsigned int port =3D portno & 1; + u32 value; + + tegra20_vi_get_output_formats(vi_chan, &main_output_format, &yuv_output_f= ormat); + + switch (data_type) { + case TEGRA_IMAGE_DT_RAW8: + case TEGRA_IMAGE_DT_RAW10: + output_channel =3D OUT_2; + if (port =3D=3D PORT_A) + main_output_format =3D VI_OUTPUT_OUTPUT_FORMAT_CSI_PPA_BAYER; + else + main_output_format =3D VI_OUTPUT_OUTPUT_FORMAT_CSI_PPB_BAYER; + break; + } + + tegra20_csi_capture_clean(csi_chan); + + /* CSI port cleanup */ + tegra20_csi_write(csi_chan, TEGRA_CSI_INPUT_STREAM_CONTROL(port), 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_CONTROL0(port), 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_CONTROL1(port), 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_WORD_COUNT(port), 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_GAP(port), 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND(port), 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME(port), = 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_PHY_CIL_CONTROL0(port), 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_CIL_PAD_CONFIG0(port), 0); + tegra20_csi_write(csi_chan, TEGRA_CSI_CIL_PAD_CONFIG1(port), 0); + + tegra20_vi_write(vi_chan, TEGRA_VI_VI_CORE_CONTROL, BIT(25 + port)); /* C= SI_PP_YUV422 */ + + tegra20_vi_write(vi_chan, TEGRA_VI_H_DOWNSCALE_CONTROL, BIT(2 + port)); /= * CSI_PP */ + tegra20_vi_write(vi_chan, TEGRA_VI_V_DOWNSCALE_CONTROL, BIT(2 + port)); /= * CSI_PP */ + + tegra20_vi_write(vi_chan, TEGRA_VI_CSI_PP_H_ACTIVE(port), width << 16); + tegra20_vi_write(vi_chan, TEGRA_VI_CSI_PP_V_ACTIVE(port), height << 16); + + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_CONTROL1(port), 0x1); + + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_WORD_COUNT(port), word= _count); + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_GAP(port), + CSI_PP_FRAME_MIN_GAP(0x14)); /* 14 vi clks between frames */ + + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_EXPECTED_FRAME(port), + CSI_PP_EXP_FRAME_HEIGHT(height) | + CSI_PP_MAX_CLOCKS(0x300) | /* wait 0x300 vi clks for timeout */ + CSI_PP_LINE_TIMEOUT_ENABLE); + + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_CONTROL0(port), + CSI_PP_OUTPUT_FORMAT_PIXEL | + CSI_PP_DATA_TYPE(data_type) | + CSI_PP_CRC_CHECK_ENABLE | + CSI_PP_WORD_COUNT_HEADER | + CSI_PP_DATA_IDENTIFIER_ENABLE | + CSI_PP_PACKET_HEADER_SENT | + port); + + tegra20_csi_write(csi_chan, TEGRA_CSI_INPUT_STREAM_CONTROL(port), + CSI_SKIP_PACKET_THRESHOLD(0x3f) | + (csi_chan->numlanes - 1)); + + tegra20_csi_write(csi_chan, TEGRA_CSI_PHY_CIL_CONTROL0(port), + CSI_CONTINUOUS_CLOCK_MODE_ENABLE | + 0x5); /* Clock settle time */ + + tegra20_vi_write(vi_chan, TEGRA_VI_CONT_SYNCPT_CSI_PP_FRAME_START(port), + VI_CONT_SYNCPT_OUT_CONTINUOUS_SYNCPT | + host1x_syncpt_id(vi_chan->frame_start_sp[0]) + << VI_CONT_SYNCPT_OUT_SYNCPT_IDX_SFT); + + tegra20_vi_write(vi_chan, TEGRA_VI_CONT_SYNCPT_OUT(output_channel), + VI_CONT_SYNCPT_OUT_CONTINUOUS_SYNCPT | + host1x_syncpt_id(vi_chan->mw_ack_sp[0]) + << VI_CONT_SYNCPT_OUT_SYNCPT_IDX_SFT); + + value =3D (port =3D=3D PORT_A) ? CSI_A_PHY_CIL_ENABLE | CSI_B_PHY_CIL_DIS= ABLE : + CSI_B_PHY_CIL_ENABLE | CSI_A_PHY_CIL_DISABLE; + tegra20_csi_write(csi_chan, TEGRA_CSI_PHY_CIL_COMMAND, value); + + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND(port), + CSI_PP_START_MARKER_FRAME_MAX(0xf) | + CSI_PP_DISABLE); + + tegra20_vi_write(vi_chan, TEGRA_VI_VI_OUTPUT_CONTROL(output_channel), + (vi_chan->vflip ? VI_OUTPUT_V_DIRECTION : 0) | + (vi_chan->hflip ? VI_OUTPUT_H_DIRECTION : 0) | + yuv_output_format | main_output_format); + + return 0; +}; + +static void tegra20_csi_port_stop_streaming(struct tegra_csi_channel *csi_= chan, u8 portno) +{ + struct tegra_csi *csi =3D csi_chan->csi; + unsigned int port =3D portno & 1; + u32 value; + + value =3D tegra20_csi_read(csi_chan, TEGRA_CSI_CSI_PIXEL_PARSER_STATUS); + dev_dbg(csi->dev, "TEGRA_CSI_CSI_PIXEL_PARSER_STATUS 0x%08x\n", value); + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_PIXEL_PARSER_STATUS, value); + + value =3D tegra20_csi_read(csi_chan, TEGRA_CSI_CSI_CIL_STATUS); + dev_dbg(csi->dev, "TEGRA_CSI_CSI_CIL_STATUS 0x%08x\n", value); + tegra20_csi_write(csi_chan, TEGRA_CSI_CSI_CIL_STATUS, value); + + tegra20_csi_write(csi_chan, TEGRA_CSI_PIXEL_STREAM_PP_COMMAND(port), + CSI_PP_START_MARKER_FRAME_MAX(0xf) | + CSI_PP_DISABLE); + + if (csi_chan->numlanes =3D=3D 4) { + tegra20_csi_write(csi_chan, TEGRA_CSI_PHY_CIL_COMMAND, + CSI_A_PHY_CIL_DISABLE | CSI_B_PHY_CIL_DISABLE); + } else { + value =3D (port =3D=3D PORT_A) ? CSI_A_PHY_CIL_DISABLE | CSI_B_PHY_CIL_N= OP : + CSI_B_PHY_CIL_DISABLE | CSI_A_PHY_CIL_NOP; + tegra20_csi_write(csi_chan, TEGRA_CSI_PHY_CIL_COMMAND, value); + } +} + +static int tegra20_csi_start_streaming(struct tegra_csi_channel *csi_chan) +{ + u8 *portnos =3D csi_chan->csi_port_nums; + int ret, i; + + for (i =3D 0; i < csi_chan->numgangports; i++) { + ret =3D tegra20_csi_port_start_streaming(csi_chan, portnos[i]); + if (ret) + goto stream_start_fail; + } + + return 0; + +stream_start_fail: + for (i =3D i - 1; i >=3D 0; i--) + tegra20_csi_port_stop_streaming(csi_chan, portnos[i]); + + return ret; +} + +static void tegra20_csi_stop_streaming(struct tegra_csi_channel *csi_chan) +{ + u8 *portnos =3D csi_chan->csi_port_nums; + int i; + + for (i =3D 0; i < csi_chan->numgangports; i++) + tegra20_csi_port_stop_streaming(csi_chan, portnos[i]); +} + +/* Tegra20 CSI operations */ +static const struct tegra_csi_ops tegra20_csi_ops =3D { + .csi_start_streaming =3D tegra20_csi_start_streaming, + .csi_stop_streaming =3D tegra20_csi_stop_streaming, +}; + +static const char * const tegra20_csi_clks[] =3D { + "csi", +}; + +/* Tegra20 CSI SoC data */ +const struct tegra_csi_soc tegra20_csi_soc =3D { + .ops =3D &tegra20_csi_ops, + .csi_max_channels =3D 2, /* CSI-A and CSI-B */ + .clk_names =3D tegra20_csi_clks, + .num_clks =3D ARRAY_SIZE(tegra20_csi_clks), + .has_mipi_calibration =3D false, +}; + +static const char * const tegra30_csi_clks[] =3D { + "csi", + "csia_pad", + "csib_pad", +}; + +/* Tegra30 CSI SoC data */ +const struct tegra_csi_soc tegra30_csi_soc =3D { + .ops =3D &tegra20_csi_ops, + .csi_max_channels =3D 2, /* CSI-A and CSI-B */ + .clk_names =3D tegra30_csi_clks, + .num_clks =3D ARRAY_SIZE(tegra30_csi_clks), + .has_mipi_calibration =3D false, +}; + /* -----------------------------------------------------------------------= --- * VIP */ @@ -677,10 +1170,11 @@ static int tegra20_vip_start_streaming(struct tegra_= vip_channel *vip_chan) data_type =3D=3D TEGRA_IMAGE_DT_RAW10) ? OUT_2 : OUT_1; =20 - unsigned int main_input_format; - unsigned int yuv_input_format; + unsigned int main_input_format, yuv_input_format; + unsigned int main_output_format, yuv_output_format; =20 tegra20_vi_get_input_formats(vi_chan, &main_input_format, &yuv_input_form= at); + tegra20_vi_get_output_formats(vi_chan, &main_output_format, &yuv_output_f= ormat); =20 tegra20_vi_write(vi_chan, TEGRA_VI_VI_CORE_CONTROL, 0); =20 @@ -713,6 +1207,11 @@ static int tegra20_vip_start_streaming(struct tegra_v= ip_channel *vip_chan) =20 tegra20_vi_write(vi_chan, TEGRA_VI_CAMERA_CONTROL, VI_CAMERA_CONTROL_STOP= _CAPTURE); =20 + tegra20_vi_write(vi_chan, TEGRA_VI_VI_OUTPUT_CONTROL(output_channel), + (vi_chan->vflip ? VI_OUTPUT_V_DIRECTION : 0) | + (vi_chan->hflip ? VI_OUTPUT_H_DIRECTION : 0) | + yuv_output_format | main_output_format); + return 0; } =20 diff --git a/drivers/staging/media/tegra-video/vi.h b/drivers/staging/media= /tegra-video/vi.h index cac0c0d0e225..c02517c9e09b 100644 --- a/drivers/staging/media/tegra-video/vi.h +++ b/drivers/staging/media/tegra-video/vi.h @@ -127,6 +127,7 @@ struct tegra_vi { * frame through host1x syncpoint counters (On Tegra20 used for the * OUT_1 syncpt) * @sp_incr_lock: protects cpu syncpoint increment. + * @next_fs_sp_idx: next expected value for frame_start_sp[0] (Tegra20) * @next_out_sp_idx: next expected value for mw_ack_sp[0], i.e. OUT_1 (Teg= ra20) * * @kthread_start_capture: kthread to start capture of single frame when @@ -191,6 +192,7 @@ struct tegra_vi_channel { /* protects the cpu syncpoint increment */ spinlock_t sp_incr_lock[GANG_PORTS_MAX]; u32 next_out_sp_idx; + u32 next_fs_sp_idx; =20 struct task_struct *kthread_start_capture; wait_queue_head_t start_wait; diff --git a/drivers/staging/media/tegra-video/video.c b/drivers/staging/me= dia/tegra-video/video.c index a25885f93cd7..8fa660431eb0 100644 --- a/drivers/staging/media/tegra-video/video.c +++ b/drivers/staging/media/tegra-video/video.c @@ -124,10 +124,12 @@ static int host1x_video_remove(struct host1x_device *= dev) =20 static const struct of_device_id host1x_video_subdevs[] =3D { #if defined(CONFIG_ARCH_TEGRA_2x_SOC) + { .compatible =3D "nvidia,tegra20-csi", }, { .compatible =3D "nvidia,tegra20-vip", }, { .compatible =3D "nvidia,tegra20-vi", }, #endif #if defined(CONFIG_ARCH_TEGRA_3x_SOC) + { .compatible =3D "nvidia,tegra30-csi", }, { .compatible =3D "nvidia,tegra30-vip", }, { .compatible =3D "nvidia,tegra30-vi", }, #endif --=20 2.48.1