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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 73FE841604E0; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 01/15] PCI: cadence: Add module support for platform controller driver Date: Tue, 19 Aug 2025 19:52:25 +0800 Message-ID: <20250819115239.4170604-2-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CF:EE_|TY1PPF0B80138A3:EE_ X-MS-Office365-Filtering-Correlation-Id: c63b6302-dff7-42b5-2788-08dddf173fc5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|82310400026|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?KkY9ratcdUwQyu2bZCo30RwcGMBvWqj8mQF3lLGut0kt1ZhVdkLZHwunvjOT?= =?us-ascii?Q?SQwlr2Ie4YAqi+JIkZnreCDxHXjkFL/fbenEz4yrAmae1yPxUhJANznCLWI+?= =?us-ascii?Q?KY6KCXhAxAMdW5wa6wwLMAdx35Yjx4QyOLPmfjXEeYvVyqOhU7HwXIBD4Z5g?= =?us-ascii?Q?jt4e8glTSta5julqb7GE1Gl85NHupnDJONuv98/XFE0OIfiDEBGMQ1L7TnfQ?= =?us-ascii?Q?D9uM5ur/2SDpl6Mfjare5Jv1BoPURpw41si5BBnDA+NFQzxNk0NbK5mqPRzV?= =?us-ascii?Q?2XCghADqtRpK+xORvbGkbGXifWMWwIybPybZDupAMMCNa1vZPVPW8MxYLhNc?= =?us-ascii?Q?oOiRtUHj+jGdLvPa2nsL6uMIWQ0pVBdGytM7K2x1I9qBN5MOQoDq9ytoCpMC?= =?us-ascii?Q?U/wyXmk30c0P96VvSCusvXGWoSUAhAPI2Qm4NlGOV8TwoV96SvUx/pNY5Uxl?= =?us-ascii?Q?9NSIFhPhHX/CG3t7ElnJUK9XPEnlke+GQ7AZb/4BpxcZ46ZNTso4FFx0FpZL?= =?us-ascii?Q?1RfEBiezGXoLige6C9upMl8l7ZmN+UhSydwv/4eIHoK4gH1Z19YT1Jf0XLTB?= =?us-ascii?Q?0OIaVeKLzh0pYR9oJWTq8s5d3xxQHXWBZC2DT1TvulS5OYx4jmy/fxE6rp+I?= =?us-ascii?Q?WOtKsOdZRP/U5wbQ8x/vkq6WWvLSLAK5a/T0MtGnz7XiqUqzJnayFGIwygI5?= =?us-ascii?Q?asu56oh5KUg1PJOuJ7xYoNHmdZuehyVsFO8WcvVpBstVZzIdWKdEbxCzvi9z?= =?us-ascii?Q?StgMlsSl8y9Br2nGrc5cQ/A7sZcz1gBKg/pPrAdZH1n5XzW3Iz/ookFYle9o?= =?us-ascii?Q?LNPJOfHO6HErJfGXNsEin2/wUgl6QWZFMCSCcL8weuVmAlrb3wgHxupLzT++?= =?us-ascii?Q?jjZBDtfQJ6cG30+3UsfRm5fp45IvBumMBehHUPtYijsBH5bKcx1lMywN55zm?= =?us-ascii?Q?KvK+gNp53Bs2KYYcnUj89YUYNwvY8BYgp2/8OPwHQqCCI7qi7DzpG2htKV9i?= =?us-ascii?Q?iijzpVdD1jC99bqIZJQPKsBp6C+ho/nBaESbOUqDxmaOWYCEbHOQzWulupQ4?= =?us-ascii?Q?9hGr5b2qnASk0IfYyA8QoakHODtl9a3Uj4LBXrpjQ9cq92S/RvwgfyjwyiSB?= =?us-ascii?Q?j22Y5zdYy366Ip84/Ud8cRRGfa2MIBuQWcolX23XxQJmwZBwnwAag0qqgK0c?= =?us-ascii?Q?WcOtzZ7jOK3gwV4+U261HFtibd86qidT6Ua9a65mdFd1aI1jx1+sgdUxdkPa?= =?us-ascii?Q?sMCKrEdT/QnGDPd9fSYngwhFHnUnLf9IeOP4uifilypvC0BQjcBBVzXxb5Cb?= =?us-ascii?Q?rpR8m5KMvEBg+ix89xMvj8ZEoEGpaFkPZAPO1vTWEvv7RYTi8REy0ToUpnVJ?= =?us-ascii?Q?01PWX8zcKE8MfEpZKRx22ZVnYV9dWD0xRNB/25gu038JUHEIq/Vk6xOXY3jX?= =?us-ascii?Q?6mNV4vcr3IDMi/cgoPOzF+wr3lBtsvWObjDobRX8tm/93p7zU/OGiOdiNDpB?= =?us-ascii?Q?nhFN6uR5xR1cCmTjjJ9wfy0c0KoulrvNUy0f?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(82310400026)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:10.1868 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c63b6302-dff7-42b5-2788-08dddf173fc5 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CF.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY1PPF0B80138A3 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add support for building PCI cadence platforms as a module. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Kconfig | 6 +++--- drivers/pci/controller/cadence/pcie-cadence-plat.c | 5 ++++- drivers/pci/controller/cadence/pcie-cadence.c | 1 + 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 666e16b6367f..117677a23d68 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -19,10 +19,10 @@ config PCIE_CADENCE_EP select PCIE_CADENCE =20 config PCIE_CADENCE_PLAT - bool + tristate =20 config PCIE_CADENCE_PLAT_HOST - bool "Cadence platform PCIe controller (host mode)" + tristate "Cadence platform PCIe controller (host mode)" depends on OF select PCIE_CADENCE_HOST select PCIE_CADENCE_PLAT @@ -32,7 +32,7 @@ config PCIE_CADENCE_PLAT_HOST vendors SoCs. =20 config PCIE_CADENCE_PLAT_EP - bool "Cadence platform PCIe controller (endpoint mode)" + tristate "Cadence platform PCIe controller (endpoint mode)" depends on OF depends on PCI_ENDPOINT select PCIE_CADENCE_EP diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index 0456845dabb9..ebd5c3afdfcd 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -177,4 +177,7 @@ static struct platform_driver cdns_plat_pcie_driver =3D= { .probe =3D cdns_plat_pcie_probe, .shutdown =3D cdns_plat_pcie_shutdown, }; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 84ECC41604E5; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 02/15] PCI: cadence: Split PCIe controller header file Date: Tue, 19 Aug 2025 19:52:26 +0800 Message-ID: <20250819115239.4170604-3-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E5:EE_|SEZPR06MB7188:EE_ X-MS-Office365-Filtering-Correlation-Id: 09ee9add-1a54-41fe-d4cd-08dddf173fc3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|376014|82310400026|7416014|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?h+UOevznaXd6Bb1RHE4xrQrI+BwwarnaTiTB8e6c+HoaTUzNn9Av7UIbaNj4?= =?us-ascii?Q?mR4MyXShnooMIa08d6lcHrdCKlCOW5DhUTbRWGePk5JrPPx3teFqHAMIQH4X?= =?us-ascii?Q?xEzIzpJMhzNEtoE22Z3B2ocMNcXPJptZgUvIXbWEQ3g0AbSvaR88Oc2QzYnq?= =?us-ascii?Q?Q4ZJbPNoO3SBBeuCZ0h0hVs5CbwPNv6+XYF/FGsIHFi119FHM9rXO36wMLTs?= =?us-ascii?Q?1DPGg06EMFSHEV4AsTg4R8pbpp4zDz5J4G1/oaZEnsWwS+1RfPaVtUuliiiK?= =?us-ascii?Q?9aGeolFUdIvpV4aBbpOn+63CUMmQCzmQjsgYT485u69COxfEsISTMV4ItyOd?= =?us-ascii?Q?/PhTh6yJfLnniCmF5Uhvu4A84RANWX70IeuWAyDDBgUn/ULudJIg4eVhDLrq?= =?us-ascii?Q?T1kI2wDjX3iAH9qcwXVT/6bd2YlAlv6fywNo8WHGNZ39wc3X4JfF7q2itKf4?= =?us-ascii?Q?kejLSYK3IqPhQ99z46cMbJTHgCu7zUqbKvR+INAtvEziy/L0CoQECTZwCAH4?= =?us-ascii?Q?hlahRnNaIsR2gpXcHWaCEqho/fQsXnQg7uC6/5EEyXxRNutlm++RJCmKISh6?= =?us-ascii?Q?cRY9cKZDRDbhLqT/wLOeqWVgWB2ENgn3iqxAqTn02Z1pVbrqQ794SkaLx0By?= =?us-ascii?Q?/menwc74o8HENmRoXYTQY2cA80JZStFZqtDB2jNNvpCcmxBQb17WtvASYQPr?= =?us-ascii?Q?UFQ0iElhoiZrf3ymw04tedG2gVPQGYFdwCrUd5kd553tz9Jd7fgS6qmNvvJg?= =?us-ascii?Q?ZIHfcfvPEocVMOPxUIT5Plk5gGkb75yH5emgMBrf8G1fNcRHjQco/+V4BlhL?= =?us-ascii?Q?/XoYnQEqAekSlBckT26+w+2P/3Mm+c4d2+p1Ao6kgiPpIgopCok+ayO2sGX5?= =?us-ascii?Q?KhuI8ud9a57CEl3VnGCHOoxApgzhb5h0xucWlqaRe8swP+m3PFr/blp1h1lw?= =?us-ascii?Q?4vVsZJ9TXHr5ro1DtIJJjq4+rV4F8YtZA3iOgRXvtIdGKHKHwJBJ2pn+ZgqG?= =?us-ascii?Q?4TKl3+ilK8vCof/Msdez7ahXy4/gSqABZGU827/Xu/ESJWbcGaPQAVtTG/aE?= =?us-ascii?Q?Rz2AxgiGXJLG7EuOYrtZ5PbrtTkpNOCB0BhklLcFDGAGSglk1cLfLORli+gc?= =?us-ascii?Q?wfHyXg7xs6oayIeduR+xKcNoUJJhTsMZtmf91sFrAoKK3qg8Itl2TuQNMaeP?= =?us-ascii?Q?psSE6WHEDMtlzAjpAZx3hwx5yeHlqcvvxMvjHzDhmasE9Yzp41BAiC/KOhV8?= =?us-ascii?Q?BZKqOggO92uGqSOH9e1x+1MgOMnPWSTPFeiSPghx211f2Cif4D/fvvyJZArv?= =?us-ascii?Q?8af5uq7dEd6i6vAxbudbNUuegsPk3r7oxOQjY1vEZTtpXJxlseGQWL43AW9N?= =?us-ascii?Q?DWYS3e2HL7PPK/zoPR7HgrtFp+hKsPLHqANPTy0L/b0m9TJvdng3LuBjqh6o?= =?us-ascii?Q?XjgfSqmfmZ7tFrT4XVQJjJz+/RzQSWHDFhDMWeTTh4LwJkdy21njgX7iBlwM?= =?us-ascii?Q?wsMaw1svCVY7vGPy1U6dXyHmuFbvbqLHOh3f?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(376014)(82310400026)(7416014)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:10.1813 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 09ee9add-1a54-41fe-d4cd-08dddf173fc3 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E5.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB7188 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Split the Cadence PCIe header file by moving the Legacy (LGA) controller register definitions to a separate header file for support of next generation PCIe controller architecture. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../cadence/pcie-cadence-lga-regs.h | 228 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 226 +---------------- 2 files changed, 229 insertions(+), 225 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-lga-regs.h diff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-lga-regs.h new file mode 100644 index 000000000000..afff0c35828a --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h @@ -0,0 +1,228 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Cyrille Pitchen + +#ifndef _PCIE_CADENCE_LGA_REGS_H +#define _PCIE_CADENCE_LGA_REGS_H + +#include + +/* Parameters for the waiting for link up routine */ +#define LINK_WAIT_MAX_RETRIES 10 +#define LINK_WAIT_USLEEP_MIN 90000 +#define LINK_WAIT_USLEEP_MAX 100000 + +/* Local Management Registers */ +#define CDNS_PCIE_LM_BASE 0x00100000 + +/* Vendor ID Register */ +#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) +#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 +#define CDNS_PCIE_LM_ID_VENDOR(vid) \ + (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) +#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) +#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 +#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ + (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) + +/* Root Port Requester ID Register */ +#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) +#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) +#define CDNS_PCIE_LM_RP_RID_SHIFT 0 +#define CDNS_PCIE_LM_RP_RID_(rid) \ + (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) + +/* Endpoint Bus and Device Number Register */ +#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022C) +#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) +#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 +#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) +#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 + +/* Endpoint Function f BAR b Configuration Registers */ +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FU= NC_BAR_CFG1(fn)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_V= FUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ + (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ + (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ + (GENMASK(4, 0) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ + (GENMASK(7, 5) << ((b) * 8)) +#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) + +/* Endpoint Function Configuration Register */ +#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02C0) + +/* Root Complex BAR Configuration Register */ +#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) +#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 +#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) +#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) + +/* BAR control values applicable to both Endpoint Function and Root Comple= x */ +#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 +#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 + +#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) +#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 2) << ((bar) * 8)) + +/* PTM Control Register */ +#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0DA8) +#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) + +/* + * Endpoint Function Registers (PCI configuration space for endpoint funct= ions) + */ +#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) + +#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 +#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xB0 +#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xC0 +#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 + +/* Endpoint PF Registers */ +#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) +#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) + +/* Root Port Registers (PCI configuration space for the root port function= ) */ +#define CDNS_PCIE_RP_BASE 0x00200000 +#define CDNS_PCIE_RP_CAP_OFFSET 0xC0 + +/* Address Translation Registers */ +#define CDNS_PCIE_AT_BASE 0x00400000 + +/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) + +/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1F) * 0x0020) + +/* Region r Outbound PCIe Descriptor Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ + (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xA +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xB +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xC +#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xD +/* Bit 23 MUST be set in RC mode. */ +#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) +#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ + (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) + +/* Region r Outbound PCIe Descriptor Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ + (CDNS_PCIE_AT_BASE + 0x000C + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) +#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ + ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) + +/* Region r AXI Region Base Address Register 0 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ + (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1F) * 0x0020) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) + +/* Region r AXI Region Base Address Register 1 */ +#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ + (CDNS_PCIE_AT_BASE + 0x001C + ((r) & 0x1F) * 0x0020) + +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ + (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) +#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ + (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) + +/* AXI link down register */ +#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) + +/* LTSSM Capabilities register */ +#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x0054) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 +#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ + (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ + CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) + +#define CDNS_PCIE_RP_MAX_IB 0x3 +#define CDNS_PCIE_MAX_OB 32 + +/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008) +#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \ + (CDNS_PCIE_AT_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008) + +/* Normal/Vendor specific message access: offset inside some outbound regi= on */ +#define CDNS_PCIE_NORMAL_MSG_ROUTING_MASK GENMASK(7, 5) +#define CDNS_PCIE_NORMAL_MSG_ROUTING(route) \ + (((route) << 5) & CDNS_PCIE_NORMAL_MSG_ROUTING_MASK) +#define CDNS_PCIE_NORMAL_MSG_CODE_MASK GENMASK(15, 8) +#define CDNS_PCIE_NORMAL_MSG_CODE(code) \ + (((code) << 8) & CDNS_PCIE_NORMAL_MSG_CODE_MASK) +#define CDNS_PCIE_MSG_NO_DATA BIT(16) + +#endif /* _PCIE_CADENCE_LGA_REGS_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 1d81c4bf6c6d..79df86117fde 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -10,213 +10,7 @@ #include #include #include - -/* Parameters for the waiting for link up routine */ -#define LINK_WAIT_MAX_RETRIES 10 -#define LINK_WAIT_USLEEP_MIN 90000 -#define LINK_WAIT_USLEEP_MAX 100000 - -/* - * Local Management Registers - */ -#define CDNS_PCIE_LM_BASE 0x00100000 - -/* Vendor ID Register */ -#define CDNS_PCIE_LM_ID (CDNS_PCIE_LM_BASE + 0x0044) -#define CDNS_PCIE_LM_ID_VENDOR_MASK GENMASK(15, 0) -#define CDNS_PCIE_LM_ID_VENDOR_SHIFT 0 -#define CDNS_PCIE_LM_ID_VENDOR(vid) \ - (((vid) << CDNS_PCIE_LM_ID_VENDOR_SHIFT) & CDNS_PCIE_LM_ID_VENDOR_MASK) -#define CDNS_PCIE_LM_ID_SUBSYS_MASK GENMASK(31, 16) -#define CDNS_PCIE_LM_ID_SUBSYS_SHIFT 16 -#define CDNS_PCIE_LM_ID_SUBSYS(sub) \ - (((sub) << CDNS_PCIE_LM_ID_SUBSYS_SHIFT) & CDNS_PCIE_LM_ID_SUBSYS_MASK) - -/* Root Port Requester ID Register */ -#define CDNS_PCIE_LM_RP_RID (CDNS_PCIE_LM_BASE + 0x0228) -#define CDNS_PCIE_LM_RP_RID_MASK GENMASK(15, 0) -#define CDNS_PCIE_LM_RP_RID_SHIFT 0 -#define CDNS_PCIE_LM_RP_RID_(rid) \ - (((rid) << CDNS_PCIE_LM_RP_RID_SHIFT) & CDNS_PCIE_LM_RP_RID_MASK) - -/* Endpoint Bus and Device Number Register */ -#define CDNS_PCIE_LM_EP_ID (CDNS_PCIE_LM_BASE + 0x022c) -#define CDNS_PCIE_LM_EP_ID_DEV_MASK GENMASK(4, 0) -#define CDNS_PCIE_LM_EP_ID_DEV_SHIFT 0 -#define CDNS_PCIE_LM_EP_ID_BUS_MASK GENMASK(15, 8) -#define CDNS_PCIE_LM_EP_ID_BUS_SHIFT 8 - -/* Endpoint Function f BAR b Configuration Registers */ -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG(bar, fn) \ - (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_FU= NC_BAR_CFG1(fn)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn) \ - (CDNS_PCIE_LM_BASE + 0x0240 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn) \ - (CDNS_PCIE_LM_BASE + 0x0244 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG(bar, fn) \ - (((bar) < BAR_4) ? CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) : CDNS_PCIE_LM_EP_V= FUNC_BAR_CFG1(fn)) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG0(fn) \ - (CDNS_PCIE_LM_BASE + 0x0280 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_VFUNC_BAR_CFG1(fn) \ - (CDNS_PCIE_LM_BASE + 0x0284 + (fn) * 0x0008) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) \ - (GENMASK(4, 0) << ((b) * 8)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ - (((a) << ((b) * 8)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b) \ - (GENMASK(7, 5) << ((b) * 8)) -#define CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ - (((c) << ((b) * 8 + 5)) & CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)) - -/* Endpoint Function Configuration Register */ -#define CDNS_PCIE_LM_EP_FUNC_CFG (CDNS_PCIE_LM_BASE + 0x02c0) - -/* Root Complex BAR Configuration Register */ -#define CDNS_PCIE_LM_RC_BAR_CFG (CDNS_PCIE_LM_BASE + 0x0300) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(5, 0) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ - (((a) << 0) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_APERTURE_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(8, 6) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL(c) \ - (((c) << 6) & CDNS_PCIE_LM_RC_BAR_CFG_BAR0_CTRL_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(13, 9) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ - (((a) << 9) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_APERTURE_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(16, 14) -#define CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL(c) \ - (((c) << 14) & CDNS_PCIE_LM_RC_BAR_CFG_BAR1_CTRL_MASK) -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(17) -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_32BITS 0 -#define CDNS_PCIE_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(18) -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_ENABLE BIT(19) -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_16BITS 0 -#define CDNS_PCIE_LM_RC_BAR_CFG_IO_32BITS BIT(20) -#define CDNS_PCIE_LM_RC_BAR_CFG_CHECK_ENABLE BIT(31) - -/* BAR control values applicable to both Endpoint Function and Root Comple= x */ -#define CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED 0x0 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS 0x1 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS 0x4 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x5 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS 0x6 -#define CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0x7 - -#define LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ - (CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << (((bar) * 8) + 6)) -#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \ - (((aperture) - 2) << ((bar) * 8)) - -/* PTM Control Register */ -#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8) -#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17) - -/* - * Endpoint Function Registers (PCI configuration space for endpoint funct= ions) - */ -#define CDNS_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12)) - -#define CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET 0x90 -#define CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET 0xb0 -#define CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET 0xc0 -#define CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET 0x200 - -/* - * Endpoint PF Registers - */ -#define CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(fn) (0x144 + (fn) * 0x1000) -#define CDNS_PCIE_ARI_CAP_NFN_MASK GENMASK(15, 8) - -/* - * Root Port Registers (PCI configuration space for the root port function) - */ -#define CDNS_PCIE_RP_BASE 0x00200000 -#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 - -/* - * Address Translation Registers - */ -#define CDNS_PCIE_AT_BASE 0x00400000 - -/* Region r Outbound AXI to PCIe Address Translation Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0(r) \ - (CDNS_PCIE_AT_BASE + 0x0000 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_NBITS_MASK) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ - (((devfn) << 12) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20) -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ - (((bus) << 20) & CDNS_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK) - -/* Region r Outbound AXI to PCIe Address Translation Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(r) \ - (CDNS_PCIE_AT_BASE + 0x0004 + ((r) & 0x1f) * 0x0020) - -/* Region r Outbound PCIe Descriptor Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_DESC0(r) \ - (CDNS_PCIE_AT_BASE + 0x0008 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(3, 0) -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_MEM 0x2 -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_IO 0x6 -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 0xa -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 0xb -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG 0xc -#define CDNS_PCIE_AT_OB_REGION_DESC0_TYPE_VENDOR_MSG 0xd -/* Bit 23 MUST be set in RC mode. */ -#define CDNS_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23) -#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24) -#define CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \ - (((devfn) << 24) & CDNS_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK) - -/* Region r Outbound PCIe Descriptor Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_DESC1(r) \ - (CDNS_PCIE_AT_BASE + 0x000c + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK GENMASK(7, 0) -#define CDNS_PCIE_AT_OB_REGION_DESC1_BUS(bus) \ - ((bus) & CDNS_PCIE_AT_OB_REGION_DESC1_BUS_MASK) - -/* Region r AXI Region Base Address Register 0 */ -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0(r) \ - (CDNS_PCIE_AT_BASE + 0x0018 + ((r) & 0x1f) * 0x0020) -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS_MASK) - -/* Region r AXI Region Base Address Register 1 */ -#define CDNS_PCIE_AT_OB_REGION_CPU_ADDR1(r) \ - (CDNS_PCIE_AT_BASE + 0x001c + ((r) & 0x1f) * 0x0020) - -/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0(bar) \ - (CDNS_PCIE_AT_BASE + 0x0800 + (bar) * 0x0008) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ - (((nbits) - 1) & CDNS_PCIE_AT_IB_RP_BAR_ADDR0_NBITS_MASK) -#define CDNS_PCIE_AT_IB_RP_BAR_ADDR1(bar) \ - (CDNS_PCIE_AT_BASE + 0x0804 + (bar) * 0x0008) - -/* AXI link down register */ -#define CDNS_PCIE_AT_LINKDOWN (CDNS_PCIE_AT_BASE + 0x0824) - -/* LTSSM Capabilities register */ -#define CDNS_PCIE_LTSSM_CONTROL_CAP (CDNS_PCIE_LM_BASE + 0x005= 4) -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK GENMASK(2, 1) -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT 1 -#define CDNS_PCIE_DETECT_QUIET_MIN_DELAY(delay) \ - (((delay) << CDNS_PCIE_DETECT_QUIET_MIN_DELAY_SHIFT) & \ - CDNS_PCIE_DETECT_QUIET_MIN_DELAY_MASK) +#include "pcie-cadence-lga-regs.h" =20 enum cdns_pcie_rp_bar { RP_BAR_UNDEFINED =3D -1, @@ -225,29 +19,11 @@ enum cdns_pcie_rp_bar { RP_NO_BAR }; =20 -#define CDNS_PCIE_RP_MAX_IB 0x3 -#define CDNS_PCIE_MAX_OB 32 - struct cdns_pcie_rp_ib_bar { u64 size; bool free; }; =20 -/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ -#define CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \ - 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 8A7E841604E6; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 03/15] PCI: cadence: Add register definitions for High Perf Architecture (HPA) Date: Tue, 19 Aug 2025 19:52:27 +0800 Message-ID: <20250819115239.4170604-4-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CB:EE_|TY0PR06MB5305:EE_ X-MS-Office365-Filtering-Correlation-Id: 33b2e7ec-d004-4d1c-df5b-08dddf17401d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|82310400026|7416014|376014|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?lwzCgftAyhbGBfBl+fY+IvtgrSgqa2tBqyOzO1eOMbMzPswDnsTCz1uWSNgI?= =?us-ascii?Q?obXnJne6etOUPLTJ1V9szKp/vH+Z/U1i4MhqlUq3tpp1FMXoIE5s5ZPSNETT?= =?us-ascii?Q?WQYuQsuPvOGsmgHzU4malMZeYKTXT8qRNLNavgg485XUwbrGmpM0MNTNU79M?= =?us-ascii?Q?QxL6ooKIOTHHrk+Wlp1ydiiTz+a7ny/ChOBkxqUjzacbzBeXv+IDCRR0wqcI?= =?us-ascii?Q?oh2qbgGfaa9u8BviNygoEklhEUA8DceuVm5zsd8DerPSgXPrOfk0umzyYzq9?= =?us-ascii?Q?4eQJC+bJ0T6tpC2bm7lx/WkjdQT6uU5Rj6/YZpChDMF639AWpkXuw347/ngN?= =?us-ascii?Q?vvLr7LFmvc1WxaaYjjL7nRhUiGSg4ImnCHYkh7Ce6IZqZNDwfLc2xfxbXtcs?= =?us-ascii?Q?NQ+FCpnx2+bWfvOFaJqv1F5miMGGdU44rP0laUjkPnYbeWOdu9naa8XYZ5Y1?= =?us-ascii?Q?h2ZCAa9sAaj3KNmok7PeFv1ruUB7UoDlJuEVwFsoSxhND4TSMqAvYRonhJmf?= =?us-ascii?Q?dYDkou7LCa6PQJ1KTaq2dePCvVUlGBOabtBgQ8sZmhl4lpShnu2/q3b2iPJR?= =?us-ascii?Q?X1uCpDUbZOZOwLqQFD3ZeoqHYLsRH1wEmoyA32U1WQqMqK4CfzUIdb4P51fA?= =?us-ascii?Q?IVryx/cAnNcqtYSNUD0ZB/LktCwTI5AfXj0RDIFkdEwO2/lGJ/7r97btobPC?= =?us-ascii?Q?aUZ6FIMUl6Lec1RKtfNuPozZoceSuDP2SWZw/WFH0QMWznR8eveuUod2BAbE?= =?us-ascii?Q?nIqsjkM6pIkS6KcC8NJcaWYPUjcgpjEErteuATz3TEVUWFLTf1eTHC2day6C?= =?us-ascii?Q?BSTcJJXaH9ncAsn4QxauawOlpxJHlJi573Qj3BKJJtmpG3VcENCbT+XWIUIu?= =?us-ascii?Q?jNjF0eUWELmWJeAKeLkKzjl47jyIfCKfB8vWmeTPdXfncy0otGeUDMncYJ0O?= =?us-ascii?Q?0IvAduCrqmhma4bTLmT+ErcE3AsPfTMNbnMsX87iJMw/45U1gyKs+JK9LZsL?= =?us-ascii?Q?OB81j1j0flzlcfXEW3mpLOsmX7eN4/MrH6FKokqLk04kM9BVlkxHeh5OmjiC?= =?us-ascii?Q?fCpBvUIiN9Of1I1rrp3h/YhqwQzHEt2LYk50K9bw8dM8ja6zKhwlit9PKO0F?= =?us-ascii?Q?JelJK3+6zuHICuX6U+U13mGkWMfnVum+gVpLM7OFHf0VzjT9elIiYRP7s6p8?= =?us-ascii?Q?Zw10htTK+fWC/3G3LEl5ZaBX7NJYH/iWTV32dQTbZeXQcFwVhDLaEk224R4z?= =?us-ascii?Q?GCKJ24XVKnMu7M/5PU/lQ2ZtWngqFMq7PD3HvoQ+JDpDppIuj/VpSJDD14qg?= =?us-ascii?Q?/XD6owyqa7sC+lOczauuin/Qe8k6vcchvurbHYJqSfD4E9lzKuTApJ5FAcp9?= =?us-ascii?Q?rx6HR6bqJVqzJRxbGqSZ72jJJoQCgUHOYhGa3ua+ocyH0BMfjJLr20eRCKt4?= =?us-ascii?Q?YgU9tcr622JJGOUNvVXAFlmON6vPD1vmtvBc81MYxUDOXXCDPPxfu4x0NldY?= =?us-ascii?Q?mEif/lVqJRKlQhR+7WhtlSDv1r3soj2mYK7b?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(82310400026)(7416014)(376014)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:10.7692 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 33b2e7ec-d004-4d1c-df5b-08dddf17401d X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CB.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY0PR06MB5305 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add the register offsets and register definitions for High Performance Architecture (HPA) PCIe controllers from Cadence. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../cadence/pcie-cadence-hpa-regs.h | 182 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.h | 1 + 2 files changed, 183 insertions(+) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h b/drive= rs/pci/controller/cadence/pcie-cadence-hpa-regs.h new file mode 100644 index 000000000000..01c1bd94a34d --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa-regs.h @@ -0,0 +1,182 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Manikandan K Pillai + +#ifndef _PCIE_CADENCE_HPA_REGS_H +#define _PCIE_CADENCE_HPA_REGS_H + +#include +#include +#include +#include +#include + +/* High Performance Architecture (HPA) PCIe controller registers */ +#define CDNS_PCIE_HPA_IP_REG_BANK 0x01000000 +#define CDNS_PCIE_HPA_IP_CFG_CTRL_REG_BANK 0x01003C00 +#define CDNS_PCIE_HPA_IP_AXI_MASTER_COMMON 0x01020000 + +/* Address Translation Registers */ +#define CDNS_PCIE_HPA_AXI_SLAVE 0x03000000 +#define CDNS_PCIE_HPA_AXI_MASTER 0x03002000 + +/* Root Port register base address */ +#define CDNS_PCIE_HPA_RP_BASE 0x0 + +#define CDNS_PCIE_HPA_LM_ID 0x1420 + +/* Endpoint Function BARs */ +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(fn) : \ + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG0(pfn) (0x4000 * (pfn)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG1(pfn) ((0x4000 * (pfn)) + 0x04) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn) \ + (((bar) < BAR_3) ? CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(fn) : \ + CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(fn)) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG0(vfn) ((0x4000 * (vfn)) + 0x08) +#define CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG1(vfn) ((0x4000 * (vfn)) + 0x0C) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(f) \ + (GENMASK(9, 4) << ((f) * 10)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, a) \ + (((a) << (4 + ((b) * 10))) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTU= RE_MASK(b))) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(f) \ + (GENMASK(3, 0) << ((f) * 10)) +#define CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, c) \ + (((c) << ((b) * 10)) & (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)= )) + +/* Endpoint Function Configuration Register */ +#define CDNS_PCIE_HPA_LM_EP_FUNC_CFG 0x02C0 + +/* Root Complex BAR Configuration Register */ +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG 0x14 +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK GENMASK(9, 4) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE(a) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_APERTURE_MASK, a) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK GENMASK(3, 0) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(c) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL_MASK, c) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK GENMASK(19, 14) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE(a) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_APERTURE_MASK, a) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK GENMASK(13, 10) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(c) \ + FIELD_PREP(CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL_MASK, c) + +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE BIT(20) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS BIT(21) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE BIT(22) +#define CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS BIT(23) + +/* BAR control values applicable to both Endpoint Function and Root Comple= x */ +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED 0x0 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS 0x3 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS 0x1 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS 0x9 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS 0x5 +#define CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS 0xD + +#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \ + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10)) +#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \ + (((aperture) - 7) << ((bar) * 10)) + +#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520 +#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN BIT(17) + +/* Root Port Registers PCI config space for root port function */ +#define CDNS_PCIE_HPA_RP_CAP_OFFSET 0xC0 + +/* Region r Outbound AXI to PCIe Address Translation Register 0 */ +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r) (0x1010 + ((r) = & 0x1F) * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS_MASK, ((nbits) - 1)) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(23, 16) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK, devfn) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(31, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(bus) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS_MASK, bus) + +/* Region r Outbound AXI to PCIe Address Translation Register 1 */ +#define CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r) (0x1014 + ((r) = & 0x1F) * 0x0080) + +/* Region r Outbound PCIe Descriptor Register */ +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r) (0x1008 + ((r) = & 0x1F) * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK GENMASK(28, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x0) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x2) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0 \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x4) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1 \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x5) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MASK, 0x10) + +/* Region r Outbound PCIe Descriptor Register */ +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r) (0x100C + ((r) & 0x1F) = * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK GENMASK(31, 24) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(bus) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS_MASK, bus) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK GENMASK(23, 16) +#define CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(devfn) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK, devfn) + +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r) (0x1018 + ((r) & 0x1F)= * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS BIT(26) +#define CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN BIT(25) + +/* Region r AXI Region Base Address Register 0 */ +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r) (0x1000 + ((r) & 0x1F)= * 0x0080) +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS_MASK, ((nbits) - 1)) + +/* Region r AXI Region Base Address Register 1 */ +#define CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r) (0x1004 + ((r) & 0x1F)= * 0x0080) + +/* Root Port BAR Inbound PCIe to AXI Address Translation Register */ +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar) (((bar) * 0x000= 8)) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK GENMASK(5, 0) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(nbits) \ + FIELD_PREP(CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS_MASK, ((nbits) - 1)) +#define CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar) (0x04 + ((bar) = * 0x0008)) + +/* AXI link down register */ +#define CDNS_PCIE_HPA_AT_LINKDOWN 0x04 + +/* + * Physical Layer Configuration Register 0 + * This register contains the parameters required for functional setup + * of Physical Layer. + */ +#define CDNS_PCIE_HPA_PHY_LAYER_CFG0 0x0400 +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK GENMASK(26, 24) +#define CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay) \ + FIELD_PREP(CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK, delay) +#define CDNS_PCIE_HPA_LINK_TRNG_EN_MASK GENMASK(27, 27) + +#define CDNS_PCIE_HPA_PHY_DBG_STS_REG0 0x0420 + +#define CDNS_PCIE_HPA_RP_MAX_IB 0x3 +#define CDNS_PCIE_HPA_MAX_OB 15 + +/* Endpoint Function BAR Inbound PCIe to AXI Address Translation Register = */ +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) (((fn) * 0x0040) + = ((bar) * 0x0008)) +#define CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) (0x4 + ((fn) * 0x00= 40) + ((bar) * 0x0008)) + +#endif /* _PCIE_CADENCE_HPA_REGS_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 79df86117fde..ddfc44f8d3ef 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -11,6 +11,7 @@ #include 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 8E26D41604E7; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 04/15] PCI: cadence: Add helper functions for supporting High Perf Architecture (HPA) Date: Tue, 19 Aug 2025 19:52:28 +0800 Message-ID: <20250819115239.4170604-5-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C7:EE_|TYSPR06MB7068:EE_ X-MS-Office365-Filtering-Correlation-Id: 2dfaae86-30c9-4ae9-e064-08dddf174088 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|7416014|36860700013|376014|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?UJU4xm16hH/JEwxxiPrcGq48SxcSZ4Wc1LJsIgeUhoqdx9Qjjl7w/nCGBeDS?= =?us-ascii?Q?+Wt+UVnFrHBa9WndGzn93oo+dLDN+XhHhgOdXZqEDr5Bwd4d7VNYx9sjMOjA?= =?us-ascii?Q?HtYIHPED31V3IhsI/qGhs6ltBBPhhjv6HK9fHYRB2u/c5EembJqXvtpd8ewg?= =?us-ascii?Q?dirzFwmu4EsFXf4H78Zvv0RQSwyfDyJkota5An8IcwrZTpbpDW/PiBp1D0PO?= =?us-ascii?Q?/g/fxCx8ZpkuRESjUt9UpVkuQKXbdIrrVLvseYWcz2/1fZOqgmiyoKoCZO2G?= =?us-ascii?Q?BLbMhD8ptZ5ZSgz26UEaABRVHL2EtmiNewCqn5SKnforjZ5n9imwZMGWYSXc?= =?us-ascii?Q?ollQs5Q+eGWVn6DqdxBDuXQG96d96EUAMJ0VGqgevgt+5Gjh9gwJet0/6XEm?= =?us-ascii?Q?ppa874ukAf3wIZQrXQaaaC+hd0hNTVl7gIPgMU7q4DSxa6+s8sEgP3rFVv9t?= =?us-ascii?Q?gx3IeaAJB9Ciuf2PSq2DC4C3LMpRCNSrWFwXhKl35sGs2A0GhqzjvQDYzx/t?= =?us-ascii?Q?AYbCmHRyVAp8YQ2vQr7j7AiXxXNdboLTSPiipyR6bnyD1TKjsZsT5MleTGUq?= =?us-ascii?Q?iNrlblJWtUOT43rnpr3ABuNqwBJlJwkDgCbbIqxsq3UAfItnATkv3pIHRbOY?= =?us-ascii?Q?7NYln78rwb8g3GFW0DzHCXM4pR26KL/VDSxOnlhMYmNCxcC6I5TqECpcsgVi?= =?us-ascii?Q?//8IFnqrarCJ5PsnwRxYBywYzSWyk9W0mg9NSe5D/On+oHj7P4EtBdYjIEKD?= =?us-ascii?Q?E+WwWWj1DxVolYVViopmZblf67Utc0ZhGjYrrMTkztwHzPuu/GAnvxpUthER?= =?us-ascii?Q?K5ClLxWVNaWwICBXraQd9s3jy+envIoyfW8KNs76MJm/cl1j2g76P98wXcim?= =?us-ascii?Q?12An+I6vuEHc/z1VaFQT3MGgYB/kj5EnD1EMiPiiOD5pIXcOzjrxlgZW6JxT?= =?us-ascii?Q?8lQUfIb878QQxaiCTVJgMBZhES0Bur4+pd65EnLgGs8YeiNELWg5yg5uyF6b?= =?us-ascii?Q?fVHE73lYuMiiNKDmKTskXcgQofsfmaSkbBEiOrgO4vRqT+j7CEvRm1wzm4XO?= =?us-ascii?Q?2/mwd7pHTpsE4g3FsxXY57Ej1fvk9C3tNcMMnS2SiKo3duuxCg2oTxRSw3CN?= =?us-ascii?Q?lgug7qIaAO5F/vq5+et4lHfZ8EoBD5wd5pcZ7B2sgeH2r6E5nkG9AQYke30b?= =?us-ascii?Q?OJteQxqQZpP1XsRJ5n4NfoLqjfOXpN7z6TzcIeAscs5y0Wiqws7Nuq+prIfT?= =?us-ascii?Q?Cofsy4OJ2kmnXLxqnWj8mvZcdMnuKrX40QXXI7RC+4cN58vr/DgFvedqcSzy?= =?us-ascii?Q?ZzMVULPKihIqnA/yRmBA/wTy8KF0GL8xsbvcyA5jqHmGe3NYGRUKk1d92cIi?= =?us-ascii?Q?qluYo0Fwig5k0gqXSU66ErUERlNntNSQszoKXbbNifIReHs92Y3SxO2EqSjF?= =?us-ascii?Q?bW8EyXTknz6QeQFrCJGUy41omF9gVlrMa5cv8PhHE0yuXhaNCBGCWPEmXFHG?= =?us-ascii?Q?oKrenWPheksYx2aL2AlqsImqFPZLYGbh3lyv?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(7416014)(36860700013)(376014)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:11.4272 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2dfaae86-30c9-4ae9-e064-08dddf174088 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C7.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB7068 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add helper functions, register read, register write functions and update platform data structures for supporting High Performance Architecture (HPA) PCIe controllers from Cadence. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- .../controller/cadence/pcie-cadence-plat.c | 4 - drivers/pci/controller/cadence/pcie-cadence.h | 111 ++++++++++++++++-- 2 files changed, 103 insertions(+), 12 deletions(-) diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index ebd5c3afdfcd..b067a3296dd3 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -22,10 +22,6 @@ struct cdns_plat_pcie { struct cdns_pcie *pcie; }; =20 -struct cdns_plat_pcie_of_data { - bool is_rc; -}; - static const struct of_device_id cdns_plat_pcie_of_match[]; =20 static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pcie, u64 cpu_addr) diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index ddfc44f8d3ef..1174cf597bb0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -26,6 +26,20 @@ struct cdns_pcie_rp_ib_bar { }; =20 struct cdns_pcie; +struct cdns_pcie_rc; + +enum cdns_pcie_reg_bank { + REG_BANK_RP, + REG_BANK_IP_REG, + REG_BANK_IP_CFG_CTRL_REG, + REG_BANK_AXI_MASTER_COMMON, + REG_BANK_AXI_MASTER, + REG_BANK_AXI_SLAVE, + REG_BANK_AXI_HLS, + REG_BANK_AXI_RAS, + REG_BANK_AXI_DTI, + REG_BANKS_MAX, +}; =20 struct cdns_pcie_ops { int (*start_link)(struct cdns_pcie *pcie); @@ -34,6 +48,30 @@ struct cdns_pcie_ops { u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 +/** + * struct cdns_plat_pcie_of_data - Register bank offset for a platform + * @is_rc: controller is a RC + * @ip_reg_bank_offset: ip register bank start offset + * @ip_cfg_ctrl_reg_offset: ip config control register start offset + * @axi_mstr_common_offset: AXI master common register start offset + * @axi_slave_offset: AXI slave start offset + * @axi_master_offset: AXI master start offset + * @axi_hls_offset: AXI HLS offset start + * @axi_ras_offset: AXI RAS offset + * @axi_dti_offset: AXI DTI offset + */ +struct cdns_plat_pcie_of_data { + u32 is_rc:1; + u32 ip_reg_bank_offset; + u32 ip_cfg_ctrl_reg_offset; + u32 axi_mstr_common_offset; + u32 axi_slave_offset; + u32 axi_master_offset; + u32 axi_hls_offset; + u32 axi_ras_offset; + u32 axi_dti_offset; +}; + /** * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base @@ -45,16 +83,18 @@ struct cdns_pcie_ops { * @link: list of pointers to corresponding device link representations * @ops: Platform-specific ops to control various inputs from Cadence PCIe * wrapper + * @cdns_pcie_reg_offsets: Register bank offsets for different SoC */ struct cdns_pcie { - void __iomem *reg_base; - struct resource *mem_res; - struct device *dev; - bool is_rc; - int phy_count; - struct phy **phy; - struct device_link **link; - const struct cdns_pcie_ops *ops; + void __iomem *reg_base; + struct resource *mem_res; + struct device *dev; + bool is_rc; + int phy_count; + struct phy **phy; + struct device_link **link; + const struct cdns_pcie_ops *ops; + const struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets; }; =20 /** @@ -132,6 +172,40 @@ struct cdns_pcie_ep { unsigned int quirk_disable_flr:1; }; =20 +static inline u32 cdns_reg_bank_to_off(struct cdns_pcie *pcie, enum cdns_p= cie_reg_bank bank) +{ + u32 offset =3D 0x0; + + switch (bank) { + case REG_BANK_IP_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_reg_bank_offset; + break; + case REG_BANK_IP_CFG_CTRL_REG: + offset =3D pcie->cdns_pcie_reg_offsets->ip_cfg_ctrl_reg_offset; + break; + case REG_BANK_AXI_MASTER_COMMON: + offset =3D pcie->cdns_pcie_reg_offsets->axi_mstr_common_offset; + break; + case REG_BANK_AXI_MASTER: + offset =3D pcie->cdns_pcie_reg_offsets->axi_master_offset; + break; + case REG_BANK_AXI_SLAVE: + offset =3D pcie->cdns_pcie_reg_offsets->axi_slave_offset; + break; + case REG_BANK_AXI_HLS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_hls_offset; + break; + case REG_BANK_AXI_RAS: + offset =3D pcie->cdns_pcie_reg_offsets->axi_ras_offset; + break; + case REG_BANK_AXI_DTI: + offset =3D pcie->cdns_pcie_reg_offsets->axi_dti_offset; + break; + default: + break; + }; + return offset; +} =20 /* Register access */ static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 v= alue) @@ -144,6 +218,27 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pc= ie, u32 reg) return readl(pcie->reg_base + reg); } =20 +static inline void cdns_pcie_hpa_writel(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg, + u32 value) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + writel(value, pcie->reg_base + reg); +} + +static inline u32 cdns_pcie_hpa_readl(struct cdns_pcie *pcie, + enum cdns_pcie_reg_bank bank, + u32 reg) +{ + u32 offset =3D cdns_reg_bank_to_off(pcie, bank); + + reg +=3D offset; + return readl(pcie->reg_base + reg); +} + static inline u32 cdns_pcie_read_sz(void __iomem *addr, int size) { void __iomem *aligned_addr =3D PTR_ALIGN_DOWN(addr, 0x4); --=20 2.49.0 From nobody Sat Oct 4 06:35:23 2025 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022085.outbound.protection.outlook.com [40.107.75.85]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3DB232C313; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 9E59841604E9; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 05/15] PCI: cadence: Move PCIe EP common functions to a separate file Date: Tue, 19 Aug 2025 19:52:29 +0800 Message-ID: <20250819115239.4170604-6-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E7:EE_|TYZPR06MB6697:EE_ X-MS-Office365-Filtering-Correlation-Id: 743ee4cd-3ab0-430f-a7aa-08dddf173fcd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|82310400026|376014|1800799024|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?yUz8POsrxqHM10P6ikd1PHXcmgY0GjPz51pkMDkbNAax9dcjUfnkh1mHOWbP?= =?us-ascii?Q?Xy8XRBvVCepL1I4aMXYU7r3aOb44LXgDwkzoSE+m/csx5HWMTuAi0TH0ZjGU?= =?us-ascii?Q?LVEDxc8cwn2HiFQNiuVLzS1TIcF6Gf2z7aYb+EOW1MYeAolTNBES7b7HhHBQ?= =?us-ascii?Q?R5Hnb8BaslPxhe+IvykbtEKPpEf1F3KJpiA0veYHg+qfMLbY8sqYWrrwfdww?= =?us-ascii?Q?27MEz4ynMA8IGqr5LTiWB2kqZLVpprymY6CDrs59x99fdgjdX1cXitzIj2Fa?= =?us-ascii?Q?lFs76g1SrlLuVA3us+IBtDpzBhVjcR4iy0l36OX3Ngzyf4/jEzJnuFWghQlp?= =?us-ascii?Q?Z/WCLw/Ga4tzlDQpEO4tqfOS+rVIK2dNB+V2ZvPo3Z8LBXzyEvt2WnaKRm/3?= =?us-ascii?Q?rrxQmYyBTF8msHsVRBUaWWpXRmWDgEMLisfs4gZ/X2RxI8mdoh712c6+ojZh?= =?us-ascii?Q?9qkd9NMwTreoip78eihVRb80+NZESTN7OEw82ng7QiSZob5CGOqQXs+0bLvY?= =?us-ascii?Q?MrdRZ0VH6G7K02YVBrKUHnKlBqELXNKIa2ghk5rq/ZE/IM+UrUDI0ZeIwFV/?= =?us-ascii?Q?HljJV0SEqHstI0Sz7gUwaieJxcS4QlVnVXRaFa6hgwN4kaDYxPJbFSU/l/M6?= =?us-ascii?Q?RzwrLA7/m7xwdYC0ckV5Xr3tp79Kk8U0SeuQWuXffHaVRY52/Da3OvW8sNZY?= =?us-ascii?Q?Q2cF4pl9sCvkNuV0N5pL6EzM+Iq9F54w0eqBvHpxlnHBvd7SeRITEyvOMl4S?= =?us-ascii?Q?hTbO1fLqcnhpvW8tGM+oVBs96RaQN/LC5ZooS6Jo2hro4TYpi9bi1n1LKNpC?= =?us-ascii?Q?kyOn1Ebzlprw50ePxA1cwqPV1teXQ1DKG0c1syXidhoBEu8s77F/oHbi14am?= =?us-ascii?Q?xozI8Y4SJ+Kr3Kvy8Mphkwo3mcio6w/3ADWRq+UgtpIYZEPgP9/dOw3G9ZHL?= =?us-ascii?Q?Y5w+roOSXZRkKXd0oS1EG3PQRSF0WzPMPdjz/RtfZeB6f8P61A+UaYDP+wKC?= =?us-ascii?Q?3SXVeSiraCVir/ukDz3jY/he0QMvnSdqxPDj4+7J9i7H26unBOid7GZlL6pr?= =?us-ascii?Q?tWn4o1MXKgs9yGOfBCrNuHcp5bi14EIha3F3OQV1i2JZnrvRf2WOlPnvwYVH?= =?us-ascii?Q?KPASmtdt79/miLpof+uqL/ovpa5WUbfHWj0w60LJLnvNc5nPW3ofA/byRkhH?= =?us-ascii?Q?ey8dTtY0wRAnl4S/akOjjhU922LmhXpLvExzLeR8Tr3w3F6FDqpXB/J5m4mH?= =?us-ascii?Q?FBHmvTlEka4JPRwuJWqYIN/U73350gVcpQbYYJr1hc0AcaPPJAUxL7pqndqg?= =?us-ascii?Q?E6tZC696CtBkXf1Aa3bcccdjdvE7MJ/sZp3WqmDtcJI9ZPk4UKthV6oiKwn6?= =?us-ascii?Q?UnwNw/WMfplBLwlUoo3+FuYzeRg0XwgCbrxnlrGtbG3kT4dgrkUAUNqotSSQ?= =?us-ascii?Q?ZXusiVyVNxZPZpEWNb2m45p21hSLweBaWeKN03Hzsk1+kwL2iKXrKNteANBM?= =?us-ascii?Q?ZNSlR4j+SOLtBRwYI/NooGEn/UsHWBz1ypns?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(82310400026)(376014)(1800799024)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:10.2316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 743ee4cd-3ab0-430f-a7aa-08dddf173fcd X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E7.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6697 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Move the Cadence PCIe controller EP common functions into a separate file. The common library functions are split from legacy PCIe EP controller functions. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../cadence/pcie-cadence-ep-common.c | 251 ++++++++++++++++++ .../cadence/pcie-cadence-ep-common.h | 36 +++ .../pci/controller/cadence/pcie-cadence-ep.c | 233 +--------------- 4 files changed, 289 insertions(+), 233 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-common.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-common.h diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 9bac5fb2f13d..80c1c4be7e80 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o -obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep.o +obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.c b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.c new file mode 100644 index 000000000000..2a3f01aacc46 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.c @@ -0,0 +1,251 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe endpoint controller driver common +// Author: Cyrille Pitchen + +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-ep-common.h" + +u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) +{ + u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + u32 first_vf_offset, stride; + + if (vfn =3D=3D 0) + return fn; + + first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); + stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); + fn =3D fn + first_vf_offset + ((vfn - 1) * stride); + + return fn; +} +EXPORT_SYMBOL_GPL(cdns_pcie_get_fn_from_vfn); + +int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_header *hdr) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; + struct cdns_pcie *pcie =3D &ep->pcie; + u32 reg; + + if (vfn > 1) { + dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); + return -EINVAL; + } else if (vfn =3D=3D 1) { + reg =3D cap + PCI_SRIOV_VF_DID; + cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); + return 0; + } + + cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, + hdr->subclass_code | hdr->baseclass_code << 8); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, + hdr->cache_line_size); + cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); + cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); + + /* + * Vendor ID can only be modified from function 0, all other functions + * use the same vendor ID as function 0. + */ + if (fn =3D=3D 0) { + /* Update the vendor IDs. */ + u32 id =3D CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | + CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); + + cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); + } + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_write_header); + +int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* + * Set the Multiple Message Capable bitfield into the Message Control + * register. + */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + flags =3D (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); + flags |=3D PCI_MSI_FLAGS_64BIT; + flags &=3D ~PCI_MSI_FLAGS_MASKBIT; + cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_set_msi); + +int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags, mme; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Validate that the MSI feature is actually enabled. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* + * Get the Multiple Message Enable bitfield from the Message Control + * register. + */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + + return mme; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_get_msi); + +int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); + + reg =3D cap + PCI_MSIX_FLAGS; + val =3D cdns_pcie_ep_fn_readw(pcie, func_no, reg); + if (!(val & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + val &=3D PCI_MSIX_FLAGS_QSIZE; + + return val; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_get_msix); + +int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, + u16 interrupts, enum pci_barno bir, + u32 offset) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 val, reg; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + reg =3D cap + PCI_MSIX_FLAGS; + val =3D cdns_pcie_ep_fn_readw(pcie, fn, reg); + val &=3D ~PCI_MSIX_FLAGS_QSIZE; + val |=3D interrupts; + cdns_pcie_ep_fn_writew(pcie, fn, reg, val); + + /* Set MSI-X BAR and offset */ + reg =3D cap + PCI_MSIX_TABLE; + val =3D offset | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + /* Set PBA BAR and offset. BAR must match MSI-X BAR */ + reg =3D cap + PCI_MSIX_PBA; + val =3D (offset + (interrupts * PCI_MSIX_ENTRY_SIZE)) | bir; + cdns_pcie_ep_fn_writel(pcie, fn, reg, val); + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_set_msix); + +int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + struct cdns_pcie *pcie =3D &ep->pcie; + u64 pci_addr, pci_addr_mask =3D 0xff; + u16 flags, mme, data, data_mask; + u8 msi_count; + int ret; + int i; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI feature has been enabled by the PCI host. */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + msi_count =3D 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written. */ + data_mask =3D msi_count - 1; + data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data =3D data & ~data_mask; + + /* Get the PCI address where to write the data into. */ + pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<=3D 32; + pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &=3D GENMASK_ULL(63, 2); + + for (i =3D 0; i < interrupt_num; i++) { + ret =3D epc->ops->map_addr(epc, fn, vfn, addr, + pci_addr & ~pci_addr_mask, + entry_size); + if (ret) + return ret; + addr =3D addr + entry_size; + } + + *msi_data =3D data; + *msi_addr_offset =3D pci_addr & pci_addr_mask; + + return 0; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_map_msi_irq); + +static const struct pci_epc_features cdns_pcie_epc_vf_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D true, + .align =3D 65536, +}; + +static const struct pci_epc_features cdns_pcie_epc_features =3D { + .linkup_notifier =3D false, + .msi_capable =3D true, + .msix_capable =3D true, + .align =3D 256, +}; + +const struct pci_epc_features* +cdns_pcie_ep_get_features(struct pci_epc *epc, u8 func_no, u8 vfunc_no) +{ + if (!vfunc_no) + return &cdns_pcie_epc_features; + + return &cdns_pcie_epc_vf_features; +} +EXPORT_SYMBOL_GPL(cdns_pcie_ep_get_features); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-common.h b/driv= ers/pci/controller/cadence/pcie-cadence-ep-common.h new file mode 100644 index 000000000000..9bc9f4b52427 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-common.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver +// Author: Cyrille Pitchen + +#ifndef _PCIE_CADENCE_EP_COMMON_H +#define _PCIE_CADENCE_EP_COMMON_H + +#include +#include +#include +#include +#include "../../pci.h" + +#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ +#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 +#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 + +u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn); +int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_header *hdr); +int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 mmc); +int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn); +int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc_no); +int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, + u16 interrupts, enum pci_barno bir, + u32 offset); +int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u8 interrupt_num, + u32 entry_size, u32 *msi_data, + u32 *msi_addr_offset); +const struct pci_epc_features *cdns_pcie_ep_get_features(struct pci_epc *e= pc, + u8 func_no, + u8 vfunc_no); + +#endif /* _PCIE_CADENCE_EP_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c b/drivers/pci= /controller/cadence/pcie-cadence-ep.c index 77c5a19b2ab1..747d83ed2ad3 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-ep.c +++ b/drivers/pci/controller/cadence/pcie-cadence-ep.c @@ -13,68 +13,7 @@ #include =20 #include "pcie-cadence.h" -#include "../../pci.h" - -#define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */ -#define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1 -#define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3 - -static u8 cdns_pcie_get_fn_from_vfn(struct cdns_pcie *pcie, u8 fn, u8 vfn) -{ - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; - u32 first_vf_offset, stride; - - if (vfn =3D=3D 0) - return fn; - - first_vf_offset =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_OF= FSET); - stride =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_SRIOV_VF_STRIDE); - fn =3D fn + first_vf_offset + ((vfn - 1) * stride); - - return fn; -} - -static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn, - struct pci_epf_header *hdr) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_SRIOV_CAP_OFFSET; - struct cdns_pcie *pcie =3D &ep->pcie; - u32 reg; - - if (vfn > 1) { - dev_err(&epc->dev, "Only Virtual Function #1 has deviceID\n"); - return -EINVAL; - } else if (vfn =3D=3D 1) { - reg =3D cap + PCI_SRIOV_VF_DID; - cdns_pcie_ep_fn_writew(pcie, fn, reg, hdr->deviceid); - return 0; - } - - cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code); - cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE, - hdr->subclass_code | hdr->baseclass_code << 8); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE, - hdr->cache_line_size); - cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id); - cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin); - - /* - * Vendor ID can only be modified from function 0, all other functions - * use the same vendor ID as function 0. - */ - if (fn =3D=3D 0) { - /* Update the vendor IDs. */ - u32 id =3D CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) | - CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id); - - cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id); - } - - return 0; -} +#include "pcie-cadence-ep-common.h" =20 static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, struct pci_epf_bar *epf_bar) @@ -222,100 +161,6 @@ static void cdns_pcie_ep_unmap_addr(struct pci_epc *e= pc, u8 fn, u8 vfn, clear_bit(r, &ep->ob_region_map); } =20 -static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn, u8 nr_= irqs) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u8 mmc =3D order_base_2(nr_irqs); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - u16 flags; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* - * Set the Multiple Message Capable bitfield into the Message Control - * register. - */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - flags =3D (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1); - flags |=3D PCI_MSI_FLAGS_64BIT; - flags &=3D ~PCI_MSI_FLAGS_MASKBIT; - cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags); - - return 0; -} - -static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - u16 flags, mme; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* Validate that the MSI feature is actually enabled. */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - if (!(flags & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - - /* - * Get the Multiple Message Enable bitfield from the Message Control - * register. - */ - mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); - - return 1 << mme; -} - -static int cdns_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no, u8 vfunc= _no) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; - u32 val, reg; - - func_no =3D cdns_pcie_get_fn_from_vfn(pcie, func_no, vfunc_no); - - reg =3D cap + PCI_MSIX_FLAGS; - val =3D cdns_pcie_ep_fn_readw(pcie, func_no, reg); - if (!(val & PCI_MSIX_FLAGS_ENABLE)) - return -EINVAL; - - val &=3D PCI_MSIX_FLAGS_QSIZE; - - return val + 1; -} - -static int cdns_pcie_ep_set_msix(struct pci_epc *epc, u8 fn, u8 vfn, - u16 nr_irqs, enum pci_barno bir, u32 offset) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - struct cdns_pcie *pcie =3D &ep->pcie; - u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; - u32 val, reg; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - reg =3D cap + PCI_MSIX_FLAGS; - val =3D cdns_pcie_ep_fn_readw(pcie, fn, reg); - val &=3D ~PCI_MSIX_FLAGS_QSIZE; - val |=3D nr_irqs - 1; /* encoded as N-1 */ - cdns_pcie_ep_fn_writew(pcie, fn, reg, val); - - /* Set MSI-X BAR and offset */ - reg =3D cap + PCI_MSIX_TABLE; - val =3D offset | bir; - cdns_pcie_ep_fn_writel(pcie, fn, reg, val); - - /* Set PBA BAR and offset. BAR must match MSI-X BAR */ - reg =3D cap + PCI_MSIX_PBA; - val =3D (offset + (nr_irqs * PCI_MSIX_ENTRY_SIZE)) | bir; - cdns_pcie_ep_fn_writel(pcie, fn, reg, val); - - return 0; -} - static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u8 in= tx, bool is_asserted) { @@ -426,59 +271,6 @@ static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_= ep *ep, u8 fn, u8 vfn, return 0; } =20 -static int cdns_pcie_ep_map_msi_irq(struct pci_epc *epc, u8 fn, u8 vfn, - phys_addr_t addr, u8 interrupt_num, - u32 entry_size, u32 *msi_data, - u32 *msi_addr_offset) -{ - struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); - u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; - struct cdns_pcie *pcie =3D &ep->pcie; - u64 pci_addr, pci_addr_mask =3D 0xff; - u16 flags, mme, data, data_mask; - u8 msi_count; - int ret; - int i; - - fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); - - /* Check whether the MSI feature has been enabled by the PCI host. */ - flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); - if (!(flags & PCI_MSI_FLAGS_ENABLE)) - return -EINVAL; - - /* Get the number of enabled MSIs */ - mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); - msi_count =3D 1 << mme; - if (!interrupt_num || interrupt_num > msi_count) - return -EINVAL; - - /* Compute the data value to be written. */ - data_mask =3D msi_count - 1; - data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); - data =3D data & ~data_mask; - - /* Get the PCI address where to write the data into. */ - pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); - pci_addr <<=3D 32; - pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); - pci_addr &=3D GENMASK_ULL(63, 2); - - for (i =3D 0; i < interrupt_num; i++) { - ret =3D cdns_pcie_ep_map_addr(epc, fn, vfn, addr, - pci_addr & ~pci_addr_mask, - entry_size); - if (ret) - return ret; - addr =3D addr + entry_size; - } - - *msi_data =3D data; - *msi_addr_offset =3D pci_addr & pci_addr_mask; - - return 0; -} - static int cdns_pcie_ep_send_msix_irq(struct cdns_pcie_ep *ep, u8 fn, u8 v= fn, u16 interrupt_num) { @@ -607,29 +399,6 @@ static int cdns_pcie_ep_start(struct pci_epc *epc) return 0; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id A440141604EA; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 06/15] PCI: cadence: Move PCIe RP common functions to a separate file Date: Tue, 19 Aug 2025 19:52:30 +0800 Message-ID: <20250819115239.4170604-7-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG2PEPF000B66CD:EE_|SE1PPFA7A817EB8:EE_ X-MS-Office365-Filtering-Correlation-Id: 963a0740-63be-4800-b723-08dddf174065 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|1800799024|376014|82310400026|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?HhHJnhnlUpEshYhp8hOSAkMG2yNHSVtlOAYdHkWe4Sx4LgRplEbG4A+uN6Xo?= =?us-ascii?Q?VDFXo7d2gcyb6qitcZaXhTS3rhyYpSSmSpXHtIchL9NzXr1aA0wli6lKMOju?= =?us-ascii?Q?VNjj0xjL+JCGGjIYL9rr4buUeooxqj8YFYaX89QmD9uECPonS89x8S8nz6dv?= =?us-ascii?Q?dQdGlGmyj8wbNq26c7G/nN8zIj7R634ISDerOdZbHogEOnxnHujOcRQqqaT1?= =?us-ascii?Q?3vF8Jk7iC/z8pfZ9sf0mQAIpACRefbnt5Aum1zEZkAgaYsVITjxIEuJ6yksQ?= =?us-ascii?Q?9t2x7yfQE+j71B2jJmepW3kNcpqsowqymEyo0URY5ggz/UKg3Y8p3QHxAqOR?= =?us-ascii?Q?nAKgDvG9LfkSTvqQ7PcjqnhbQiDMVh30SooMptufge5oIdeL7TDnFIASud+q?= =?us-ascii?Q?ld3SY+B2sF6txO8cv9D4KNfbg+S/1CH+GESl0a47UCvHtEYDBFnLZ8RM3bmp?= =?us-ascii?Q?Qegimo8xyYycxeo8I14Tvi6nJuxo5etk8gFolv4VzjcuMaRqHktAxwJkptWY?= =?us-ascii?Q?fq3Zc+GPopAkhcW8Y1KQt3LTUJHijd+e4tRUmfTPlYle5IxVcd3zj6np4QiP?= =?us-ascii?Q?07ywq/VT27M1/+WcK2UTEVHfMXOveBqb8xaPYGAjosJjmWM07LX22J5Q+/QL?= =?us-ascii?Q?ywahYQKy70UbrELjJE3BhQfBVNVO5NtHuFB7O8A/rkcw1FcWZdLtFgFqZ2eK?= =?us-ascii?Q?xb/CVqKMNC5sOC03Shi761E2XRLgYASpVwvpBoZWlNUdB8AwFRqzB2gcqdOn?= =?us-ascii?Q?GTGR/E+vDdNJZuF2+OHf4vvt+gN4/8VmAUt/fjjBDcnOjPI0lrYFjgLZ5n23?= =?us-ascii?Q?M8m43Y81kQ5098L27vBvWOMdUX15LdG9mZMbA6h4+6YLGiGam7dQBaaqHCoC?= =?us-ascii?Q?PyRWy4mUw1Q8a5RQVsaT7PdR8nsbpeXnmwUCg7iTWLNwGLb+nsQHuP2Ze46A?= =?us-ascii?Q?qTt0pArOkm5WV8E1b4jnJ91aNpjtYhS0pMMbURPKcxtII/AInEoS2czLK92c?= =?us-ascii?Q?mXbekeIag3RdBtkyZv8CkwhNWAvx7CyBTyJjxAL6bH8lu1ucs8vhLyypSbX4?= =?us-ascii?Q?lP3LSm79+hdSJNFuR2gdZbHodce4fCkb0uV64kUSytAdSkQgWP2WJQXYKw/K?= =?us-ascii?Q?RZp6sqCmYJSC5yUG0BrzCI6Zmb6GhOpy0CTcJzuEQNQ+NeTVArmCEKTZW4sS?= =?us-ascii?Q?i1Ds0pXqIedMt+O2ZWBi1VirzJ5vbPWmM6QswP8OUt9WT1BXPiQPox1aL1Em?= =?us-ascii?Q?WexOV4ieXp8H7BhGznZVcubRKcmu58maQc4QHL6Q81ANcxpZyQAJqVo+tbuY?= =?us-ascii?Q?odExkm+2TeNvJGWTYPwjco3epWe4tNrMIT9TQ2JMUdEwq5BzG/wFBFWFGMNu?= =?us-ascii?Q?QM0q+ct3TwjW3JKvW2jqpAYIGVeEPjtP8TBO6w/Pv2UztaVR2BvmFvMbqwZG?= =?us-ascii?Q?k22Cd81k0G3EXsqOiVgK9MDUkG+4h7l9+r2eMFwq2hUM+agvpz1bR34ZUWoR?= =?us-ascii?Q?EncZsEmj7u6jKVzLvwasIGDBvUhdoa5D5gnh?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(1800799024)(376014)(82310400026)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:11.2382 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 963a0740-63be-4800-b723-08dddf174065 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG2PEPF000B66CD.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE1PPFA7A817EB8 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Move the Cadence PCIe controller RP common functions into a separate file. The common library functions are split from legacy PCIe RP controller functions to a separate file. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../cadence/pcie-cadence-host-common.c | 179 ++++++++++++++++++ .../cadence/pcie-cadence-host-common.h | 24 +++ .../controller/cadence/pcie-cadence-host.c | 156 +-------------- 4 files changed, 205 insertions(+), 156 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-common= .h diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index 80c1c4be7e80..e45f72388bbb 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o -obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host.o +obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-common.o pcie-caden= ce-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.c new file mode 100644 index 000000000000..d34f8c7c49f0 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define LINK_RETRAIN_TIMEOUT HZ + +u64 bar_max_size[] =3D { + [RP_BAR0] =3D _ULL(128 * SZ_2G), + [RP_BAR1] =3D SZ_2G, + [RP_NO_BAR] =3D _BITULL(63), +}; +EXPORT_SYMBOL_GPL(bar_max_size); + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) +{ + u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + unsigned long end_jiffies; + u16 lnk_stat; + + /* Wait for link training to complete. Exit after timeout. */ + end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; + do { + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + break; + usleep_range(0, 1000); + } while (time_before(jiffies, end_jiffies)); + + if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) + return 0; + + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_training_complete); + +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_wait_for_link); + +int cdns_pcie_retrain(struct cdns_pcie *pcie) +{ + u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; + u16 lnk_stat, lnk_ctl; + int ret =3D 0; + + /* + * Set retrain bit if current speed is 2.5 GB/s, + * but the PCIe root port support is > 2.5 GB/s. + */ + + lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + + PCI_EXP_LNKCAP)); + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) + return ret; + + lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { + lnk_ctl =3D cdns_pcie_rp_readw(pcie, + pcie_cap_off + PCI_EXP_LNKCTL); + lnk_ctl |=3D PCI_EXP_LNKCTL_RL; + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, + lnk_ctl); + + ret =3D cdns_pcie_host_training_complete(pcie); + if (ret) + return ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + } + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_retrain); + +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_host_wait_for_link(pcie); + + /* + * Retrain link for Gen2 training defect + * if quirk flag is set. + */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_start_link); + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size <=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] < bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_find_min_bar); + +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) +{ + enum cdns_pcie_rp_bar bar, sel_bar; + + sel_bar =3D RP_BAR_UNDEFINED; + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { + if (!rc->avail_ib_bar[bar]) + continue; + + if (size >=3D bar_max_size[bar]) { + if (sel_bar =3D=3D RP_BAR_UNDEFINED) { + sel_bar =3D bar; + continue; + } + + if (bar_max_size[bar] > bar_max_size[sel_bar]) + sel_bar =3D bar; + } + } + + return sel_bar; +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_find_max_bar); + +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b) +{ + struct resource_entry *entry1, *entry2; + + entry1 =3D container_of(a, struct resource_entry, node); + entry2 =3D container_of(b, struct resource_entry, node); + + return resource_size(entry2->res) - resource_size(entry1->res); +} +EXPORT_SYMBOL_GPL(cdns_pcie_host_dma_ranges_cmp); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.h b/dr= ivers/pci/controller/cadence/pcie-cadence-host-common.h new file mode 100644 index 000000000000..7eaa853fdb5f --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +// Copyright (c) 2017 Cadence +// Cadence PCIe Endpoint controller driver + +#ifndef _PCIE_CADENCE_HOST_COMMON_H +#define _PCIE_CADENCE_HOST_COMMON_H + +#include +#include + +extern u64 bar_max_size[]; + +int cdns_pcie_host_training_complete(struct cdns_pcie *pcie); +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_retrain(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size); +enum cdns_pcie_rp_bar +cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size); +int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_head *a, + const struct list_head *b); + +#endif /* _PCIE_CADENCE_HOST_COMMON_H */ diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/p= ci/controller/cadence/pcie-cadence-host.c index 59a4631de79f..bfdd0f200cfb 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-host.c +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c @@ -12,14 +12,7 @@ #include =20 #include "pcie-cadence.h" - -#define LINK_RETRAIN_TIMEOUT HZ - -static u64 bar_max_size[] =3D { - [RP_BAR0] =3D _ULL(128 * SZ_2G), - [RP_BAR1] =3D SZ_2G, - [RP_NO_BAR] =3D _BITULL(63), -}; +#include "pcie-cadence-host-common.h" =20 static u8 bar_aperture_mask[] =3D { [RP_BAR0] =3D 0x1F, @@ -81,77 +74,6 @@ static struct pci_ops cdns_pcie_host_ops =3D { .write =3D pci_generic_config_write, }; =20 -static int cdns_pcie_host_training_complete(struct cdns_pcie *pcie) -{ - u32 pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - unsigned long end_jiffies; - u16 lnk_stat; - - /* Wait for link training to complete. Exit after timeout. */ - end_jiffies =3D jiffies + LINK_RETRAIN_TIMEOUT; - do { - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - break; - usleep_range(0, 1000); - } while (time_before(jiffies, end_jiffies)); - - if (!(lnk_stat & PCI_EXP_LNKSTA_LT)) - return 0; - - return -ETIMEDOUT; -} - -static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) -{ - struct device *dev =3D pcie->dev; - int retries; - - /* Check if the link is up or not */ - for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { - if (cdns_pcie_link_up(pcie)) { - dev_info(dev, "Link up\n"); - return 0; - } - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); - } - - return -ETIMEDOUT; -} - -static int cdns_pcie_retrain(struct cdns_pcie *pcie) -{ - u32 lnk_cap_sls, pcie_cap_off =3D CDNS_PCIE_RP_CAP_OFFSET; - u16 lnk_stat, lnk_ctl; - int ret =3D 0; - - /* - * Set retrain bit if current speed is 2.5 GB/s, - * but the PCIe root port support is > 2.5 GB/s. - */ - - lnk_cap_sls =3D cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + - PCI_EXP_LNKCAP)); - if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <=3D PCI_EXP_LNKCAP_SLS_2_5GB) - return ret; - - lnk_stat =3D cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); - if ((lnk_stat & PCI_EXP_LNKSTA_CLS) =3D=3D PCI_EXP_LNKSTA_CLS_2_5GB) { - lnk_ctl =3D cdns_pcie_rp_readw(pcie, - pcie_cap_off + PCI_EXP_LNKCTL); - lnk_ctl |=3D PCI_EXP_LNKCTL_RL; - cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, - lnk_ctl); - - ret =3D cdns_pcie_host_training_complete(pcie); - if (ret) - return ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - } - return ret; -} - static void cdns_pcie_host_disable_ptm_response(struct cdns_pcie *pcie) { u32 val; @@ -168,23 +90,6 @@ static void cdns_pcie_host_enable_ptm_response(struct c= dns_pcie *pcie) cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL= _PTMRSEN); } =20 -static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc) -{ - struct cdns_pcie *pcie =3D &rc->pcie; - int ret; - - ret =3D cdns_pcie_host_wait_for_link(pcie); - - /* - * Retrain link for Gen2 training defect - * if quirk flag is set. - */ - if (!ret && rc->quirk_retrain_flag) - ret =3D cdns_pcie_retrain(pcie); - - return ret; -} - static void cdns_pcie_host_deinit_root_port(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; @@ -290,54 +195,6 @@ static int cdns_pcie_host_bar_ib_config(struct cdns_pc= ie_rc *rc, return 0; } =20 -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_min_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size <=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] < bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - -static enum cdns_pcie_rp_bar -cdns_pcie_host_find_max_bar(struct cdns_pcie_rc *rc, u64 size) -{ - enum cdns_pcie_rp_bar bar, sel_bar; - - sel_bar =3D RP_BAR_UNDEFINED; - for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) { - if (!rc->avail_ib_bar[bar]) - continue; - - if (size >=3D bar_max_size[bar]) { - if (sel_bar =3D=3D RP_BAR_UNDEFINED) { - sel_bar =3D bar; - continue; - } - - if (bar_max_size[bar] > bar_max_size[sel_bar]) - sel_bar =3D bar; - } - } - - return sel_bar; -} - static int cdns_pcie_host_bar_config(struct cdns_pcie_rc *rc, struct resource_entry *entry) { @@ -410,17 +267,6 @@ static int cdns_pcie_host_bar_config(struct cdns_pcie_= rc *rc, return 0; } =20 -static int cdns_pcie_host_dma_ranges_cmp(void *priv, const struct list_hea= d *a, - const struct list_head *b) -{ - struct resource_entry *entry1, *entry2; - - entry1 =3D container_of(a, struct resource_entry, node); - entry2 =3D container_of(b, struct resource_entry, node); - - return resource_size(entry2->res) - resource_size(entry1->res); -} - static void cdns_pcie_host_unmap_dma_ranges(struct cdns_pcie_rc *rc) { struct cdns_pcie *pcie =3D &rc->pcie; --=20 2.49.0 From nobody Sat Oct 4 06:35:23 2025 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022083.outbound.protection.outlook.com [40.107.75.83]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A48C732C33D; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id A844541604EB; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 07/15] PCI: cadence: Move PCIe controller common functions as a separate file Date: Tue, 19 Aug 2025 19:52:31 +0800 Message-ID: <20250819115239.4170604-8-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB89:EE_|KL1PR06MB7085:EE_ X-MS-Office365-Filtering-Correlation-Id: ee36fc53-3297-4cda-16fb-08dddf174001 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|7416014|82310400026|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?MY31c29aJfOYjEK+7sk5pD+liWD8/MvFQbLD7a97t2SYBykAD9TJRxn95bFf?= =?us-ascii?Q?+7yTZnNe6Qxngct1n52KFoCrEU7W+UY5XRIGq8AcnG03V73rmV3VJBOhu72K?= =?us-ascii?Q?tptCy3MrwmihjttFKfBK3KM3GDroDrU5vXwKGnQ3ejl//lsUjsH6/pcMl+MW?= =?us-ascii?Q?MLlNOvcAfy2paG5hcFuW526x5tV3xksSEoxyK0gRbUMqud6AMtKK9hpe+gLn?= =?us-ascii?Q?P2sjK9AoEE5V/3ryvrr8xonfeC2XZRg/x2xL7IOOMbHlhVKLXtCE3e5B+6lH?= =?us-ascii?Q?ltsQRLzJBaM7Yth3sEYsWWDMgwH1WYZkXEQzw6xBhPj/E0NOPch/gg8wiUZi?= =?us-ascii?Q?T7P3m4EGLTc8kh+y2KCeJcK2uM6gaezmIl9nLXnUdpWQLrfk/fwt6Koq+dGa?= =?us-ascii?Q?HQ0waab9nZmXW9CdDSIwQDse/FX8LFBSCl4pzpmHJWrInXV19AP1uhYwRopr?= =?us-ascii?Q?OMjPW35cfyij0zU+xjuBJenrMknEXJxtvFpdkDYTHfXlwZN9Ka0+hNyyVdAI?= =?us-ascii?Q?33l8/OIX9UM2NvI45Gu5ckjSvknpzbz8IMdqJD/ih6aIeTCwLRz5Am9K8pBi?= =?us-ascii?Q?yU25yZqKFRG+UEAxjMtsHb4TFsOaBU0BpUTT/ARNSWbmTa+3uM5Fx/6ejT71?= =?us-ascii?Q?z4rLqBDLpvSpkIqHXpnYlhaB4guM0QAcrPBiB2tTT8MR+ymp5liKNyp7CDRB?= =?us-ascii?Q?qcycCUjGZNLNk58xu0lhj6b6i/0FhqE/vRCY2lCl1/8hQG2KJ+HqWrbvcXgt?= =?us-ascii?Q?IdSPmcpBShPEKDptb19mHoGUzgOwRb//K8ZfuW+Rk39Du5LhdxTLG2MQVyj3?= =?us-ascii?Q?UxmfyEEzACyB+mJ9gHIpyvcjUS05gq4O4ELxhjOWDlge6MMnt4LQbUovVr8k?= =?us-ascii?Q?xbUy3vsTh1ua8B5o2eP1v4VmEGwvTjsWH/Mqp9FkY9MV6q3YK++DTkgb7UU8?= =?us-ascii?Q?M7CMBS0++xtnSOOx2rC1eb3jE06Tv7EHhQjoLtiQmnpFmJzyfRdQcswM7ObO?= =?us-ascii?Q?iG/AskJs7FtGnwJlneMqftqsTEt87gPdf4B3rMqmMcBk9H6ePmWwBvzZmA3p?= =?us-ascii?Q?/1ZzG9nHVFzknrjO++Jd3AB7XErJxGRDKwhO22p5VoD6XpiAXLtkIZAceuKC?= =?us-ascii?Q?Jmgva7z6fXGKq5XZec1+eFtIjTYgHeOWBRBHWLhddfPR2e9Ve0T+EEq1PhfI?= =?us-ascii?Q?HbPanhXukGulLxVsUVYTeaYKr0gXdJhmOz0xumH5WYF30620Fx2bfN2a9Mf0?= =?us-ascii?Q?i6013M61l8cdZvcjLlvb1zQlWZhN4sWNhAOM/+ny+mPhAjpp5M3+D/1Db59/?= =?us-ascii?Q?9RG8QhbERFcok6hplRdgbGQB6ByoquLHWU8ly/bfbXfGJ0VlAiF1WEar86rW?= =?us-ascii?Q?xqxMsIVwYph2PjId7/M9oeo9v8B+KXUIuQf3aKrXJYzRObMCXG1TMbTl9570?= =?us-ascii?Q?VZ92WNvh7F0pqFVsXApjh0g43+FD32G4tUhNILwbSyyj+1CnEk9uU/85y/sv?= =?us-ascii?Q?HN/F5jTB9YTQvdcZfyXg7Nf8aGEZzjmLvx+v?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(82310400026)(36860700013)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:10.5250 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ee36fc53-3297-4cda-16fb-08dddf174001 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB89.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR06MB7085 Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Move the functions for platform common tasks to a separate file. The common library functions and functions specific to platform are now in different files. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 2 +- .../controller/cadence/pcie-cadence-common.c | 141 ++++++++++++++++++ drivers/pci/controller/cadence/pcie-cadence.c | 129 ---------------- 3 files changed, 142 insertions(+), 130 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-common.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index e45f72388bbb..b104562fb86a 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence.o +obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-common.o pcie-caden= ce-host.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-common.c b/drivers= /pci/controller/cadence/pcie-cadence-common.c new file mode 100644 index 000000000000..e14d53d64bf1 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-common.c @@ -0,0 +1,141 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver. +// Author: Cyrille Pitchen + +#include +#include + +#include "pcie-cadence.h" + +void cdns_pcie_disable_phy(struct cdns_pcie *pcie) +{ + int i =3D pcie->phy_count; + + while (i--) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } +} +EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); + +int cdns_pcie_enable_phy(struct cdns_pcie *pcie) +{ + int ret; + int i; + + for (i =3D 0; i < pcie->phy_count; i++) { + ret =3D phy_init(pcie->phy[i]); + if (ret < 0) + goto err_phy; + + ret =3D phy_power_on(pcie->phy[i]); + if (ret < 0) { + phy_exit(pcie->phy[i]); + goto err_phy; + } + } + + return 0; + +err_phy: + while (--i >=3D 0) { + phy_power_off(pcie->phy[i]); + phy_exit(pcie->phy[i]); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); + +int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) +{ + struct device_node *np =3D dev->of_node; + int phy_count; + struct phy **phy; + struct device_link **link; + int i; + int ret; + const char *name; + + phy_count =3D of_property_count_strings(np, "phy-names"); + if (phy_count < 1) { + dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); + pcie->phy_count =3D 0; + return 0; + } + + phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); + if (!link) + return -ENOMEM; + + for (i =3D 0; i < phy_count; i++) { + of_property_read_string_index(np, "phy-names", i, &name); + phy[i] =3D devm_phy_get(dev, name); + if (IS_ERR(phy[i])) { + ret =3D PTR_ERR(phy[i]); + goto err_phy; + } + link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); + if (!link[i]) { + devm_phy_put(dev, phy[i]); + ret =3D -EINVAL; + goto err_phy; + } + } + + pcie->phy_count =3D phy_count; + pcie->phy =3D phy; + pcie->link =3D link; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) + goto err_phy; + + return 0; + +err_phy: + while (--i >=3D 0) { + device_link_del(link[i]); + devm_phy_put(dev, phy[i]); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); + +static int cdns_pcie_suspend_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + + cdns_pcie_disable_phy(pcie); + + return 0; +} + +static int cdns_pcie_resume_noirq(struct device *dev) +{ + struct cdns_pcie *pcie =3D dev_get_drvdata(dev); + int ret; + + ret =3D cdns_pcie_enable_phy(pcie); + if (ret) { + dev_err(dev, "failed to enable PHY\n"); + return ret; + } + + return 0; +} + +const struct dev_pm_ops cdns_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(cdns_pcie_suspend_noirq, + cdns_pcie_resume_noirq) +}; +EXPORT_SYMBOL_GPL(cdns_pcie_pm_ops); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 5603f214f4c7..51c9bc4eb174 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -152,135 +152,6 @@ void cdns_pcie_reset_outbound_region(struct cdns_pcie= *pcie, u32 r) } EXPORT_SYMBOL_GPL(cdns_pcie_reset_outbound_region); =20 -void cdns_pcie_disable_phy(struct cdns_pcie *pcie) -{ - int i =3D pcie->phy_count; - - while (i--) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } -} -EXPORT_SYMBOL_GPL(cdns_pcie_disable_phy); - -int cdns_pcie_enable_phy(struct cdns_pcie *pcie) -{ - int ret; - int i; - - for (i =3D 0; i < pcie->phy_count; i++) { - ret =3D phy_init(pcie->phy[i]); - if (ret < 0) - goto err_phy; - - ret =3D phy_power_on(pcie->phy[i]); - if (ret < 0) { - phy_exit(pcie->phy[i]); - goto err_phy; - } - } - - return 0; - -err_phy: - while (--i >=3D 0) { - phy_power_off(pcie->phy[i]); - phy_exit(pcie->phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_enable_phy); - -int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie) -{ - struct device_node *np =3D dev->of_node; - int phy_count; - struct phy **phy; - struct device_link **link; - int i; - int ret; - const char *name; - - phy_count =3D of_property_count_strings(np, "phy-names"); - if (phy_count < 1) { - dev_info(dev, "no \"phy-names\" property found; PHY will not be initiali= zed\n"); - pcie->phy_count =3D 0; - return 0; - } - - phy =3D devm_kcalloc(dev, phy_count, sizeof(*phy), GFP_KERNEL); - if (!phy) - return -ENOMEM; - - link =3D devm_kcalloc(dev, phy_count, sizeof(*link), GFP_KERNEL); - if (!link) - return -ENOMEM; - - for (i =3D 0; i < phy_count; i++) { - of_property_read_string_index(np, "phy-names", i, &name); - phy[i] =3D devm_phy_get(dev, name); - if (IS_ERR(phy[i])) { - ret =3D PTR_ERR(phy[i]); - goto err_phy; - } - link[i] =3D device_link_add(dev, &phy[i]->dev, DL_FLAG_STATELESS); - if (!link[i]) { - devm_phy_put(dev, phy[i]); - ret =3D -EINVAL; - goto err_phy; - } - } - - pcie->phy_count =3D phy_count; - pcie->phy =3D phy; - pcie->link =3D link; - - ret =3D cdns_pcie_enable_phy(pcie); - if (ret) - goto err_phy; - - return 0; - -err_phy: - while (--i >=3D 0) { - device_link_del(link[i]); - devm_phy_put(dev, phy[i]); - } - - return ret; -} -EXPORT_SYMBOL_GPL(cdns_pcie_init_phy); - -static int cdns_pcie_suspend_noirq(struct device *dev) -{ - struct cdns_pcie *pcie =3D dev_get_drvdata(dev); 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id AC34B41604EF; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 08/15] PCI: cadence: Add support for High Perf Architecture (HPA) controller Date: Tue, 19 Aug 2025 19:52:32 +0800 Message-ID: <20250819115239.4170604-9-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB83:EE_|TY2PPFAC281535F:EE_ X-MS-Office365-Filtering-Correlation-Id: a4cf7a0b-4ee8-4c49-1563-08dddf173ffd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|1800799024|82310400026|376014|36860700013|7053199007; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DTPL4PSUQsrA5Efb/vxmOVWUXviAe1CDHltm7OWtHYJFh8mox9gWMV6tsF3k?= =?us-ascii?Q?ygGYYkrfI3MSKg0U/L/EJ3lxdQ0e5MjRn3Il1GBygc63wc7a0sNaa8wHPU7O?= =?us-ascii?Q?lKbzoS4T6340JDFfoRC3sb3fGLLjZc3aifo0Pf9JWiGq2kIDYX0wZtw8wrcg?= =?us-ascii?Q?kCuLDL7CPLmavBz0MN/hmTQYjBpecBH+XOwrCyBc+fS2XfUp4eAEwa87hBr1?= =?us-ascii?Q?jnuP8eSfT+sprn+7gdDureo8StP6imUwgBvnJxMEU3wpgVqFywERtUQcWZn3?= =?us-ascii?Q?kE3Mepgy0wLtjCSNh4q7QW2pAjmncuuoelj70txCZDyKu8wYu25HHKPbJ9+Q?= =?us-ascii?Q?XhKHo1wX51LImgZcoxrf7qxOuGf3vw5mpbeQnSeMTq6tixbxzgMPGnlNIhNn?= =?us-ascii?Q?XtPVk7b2T1Jdz2ZpErHAnaZd3VS2KACQzNeTSGJFY68Qf3FcthpLlbaysXd1?= =?us-ascii?Q?AgbIH19DEe74adQopRUxyEOIoObY4ykq9sObke1QzZq2ucu+JMPXVKeopP+n?= =?us-ascii?Q?6xO7sWXUJveJpuWedOXJTFaHK8K9aJt+l2onUn33OW0x6i1kFnBxAaX83bb2?= =?us-ascii?Q?8JzWysZWSa1+0y1ib7KQxALXZl0406Wcbp7OCxhbJm3OzVoJY9VuQAGhQ0Zm?= =?us-ascii?Q?Xx5p76ClpxANTDHc5mOZBGk/2OH2H0/s+ppW1Mz1Q4uUzkc/+lLl1WaFmqMr?= =?us-ascii?Q?qtvYZdbPH9sFbUyec6DSTfpFy9EHVAOv0jVuJVTDZ2ab7Df9erNiGpv1HXCx?= =?us-ascii?Q?ELmvILv+Cn3sn5wLH71Iill+BZZYu11caC1hEKpPlmMuxLJON6h1FhnSUb58?= =?us-ascii?Q?XQ2OM6lIsSOn3j0jXfwimp6MeGi5TBLorqeZTrNL5pzfMRzVOyQ/yYXCLuGq?= =?us-ascii?Q?sqm7xSb/+EXsUasJQYsUqhfgdBQk3Rfklbv0zmhRIjGgOH5dNhxAGsaSvadW?= =?us-ascii?Q?so2foVzDBtbzG2Dy5sx5bC6CIVR2szYr1YvH575PvbaVOttkFGBKl8YRBBo6?= =?us-ascii?Q?Ef7Tm6rYZ3XMs30Apd+1/7aOEyRpwZYNHKONSPWNDz/v6Nv1tU+Qew0NXhxS?= =?us-ascii?Q?GZJU0pJXNGtT+C0NBqJnEw4QCPcMgMMiYp/M5ud00D5CzLfIrGBPf4/IYB1V?= =?us-ascii?Q?5ybgz5jLu7IN51+p7Yq7qSVfWLk1ZNz2JcXQI66I52VT3ufPiDeHcgiRESfj?= =?us-ascii?Q?c2LlaHGAAWd1k0UclceG+YR/ZASDB2eod3rraYsyiWRB/MbKb4667dgAJ1XQ?= =?us-ascii?Q?fdCkoLelc53GQUEIWtnZxHLYP0vhWIPvMS41IEWgzQRAv5iNRpFEzweFjbsk?= =?us-ascii?Q?+VO/wszZnCK6u46/K5ziKziB1lG+jzCr81aIa/WH/ru1Ix7ZQqGbL6KjdexL?= =?us-ascii?Q?0iUbKK6MzBmXoHgianf1MmpjAdFE6EKzt6cS3OxtvSzc80v7Gyb1M4sTlqkK?= =?us-ascii?Q?4TF97hI2VhdJqUSid5gWY0AkildXeVW6zYLvsWMZsVWOVR/QCtmHsEriXJwO?= =?us-ascii?Q?TKqKp7szf+JFVomEUDeL4g4OXdDW8DlFRyzt?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(1800799024)(82310400026)(376014)(36860700013)(7053199007);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:10.5120 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4cf7a0b-4ee8-4c49-1563-08dddf173ffd X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB83.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TY2PPFAC281535F Content-Type: text/plain; charset="utf-8" From: Manikandan K Pillai Add support for Cadence PCIe RP and EP configuration for High Performance Architecture (HPA) controllers. Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/Makefile | 10 +- .../controller/cadence/pcie-cadence-ep-hpa.c | 528 ++++++++++++++++ .../cadence/pcie-cadence-host-hpa.c | 585 ++++++++++++++++++ .../pci/controller/cadence/pcie-cadence-hpa.c | 204 ++++++ drivers/pci/controller/cadence/pcie-cadence.c | 11 + drivers/pci/controller/cadence/pcie-cadence.h | 74 ++- 6 files changed, 1403 insertions(+), 9 deletions(-) create mode 100644 drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-host-hpa.c create mode 100644 drivers/pci/controller/cadence/pcie-cadence-hpa.c diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index b104562fb86a..de4ddae7aca4 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -1,6 +1,10 @@ # SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_PCIE_CADENCE) +=3D pcie-cadence-common.o pcie-cadence.o -obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-common.o pcie-caden= ce-host.o -obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-common.o pcie-cadence-e= p.o +pcie-cadence-mod-y :=3D pcie-cadence-hpa.o pcie-cadence-common.o pcie-cade= nce.o +pcie-cadence-host-mod-y :=3D pcie-cadence-host-common.o pcie-cadence-host.= o pcie-cadence-host-hpa.o +pcie-cadence-ep-mod-y :=3D pcie-cadence-ep-common.o pcie-cadence-ep.o pcie= -cadence-ep-hpa.o + +obj-$(CONFIG_PCIE_CADENCE) =3D pcie-cadence-mod.o +obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-mod.o +obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-mod.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c b/drivers= /pci/controller/cadence/pcie-cadence-ep-hpa.c new file mode 100644 index 000000000000..a5366ecec34f --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-ep-hpa.c @@ -0,0 +1,528 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe endpoint controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-ep-common.h" + +static int cdns_pcie_hpa_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr, u64 pci_addr, size_t size) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 r; + + r =3D find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG); + if (r >=3D ep->max_regions - 1) { + dev_err(&epc->dev, "no free outbound region\n"); + return -EINVAL; + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, r, false, addr, pci_addr, = size); + + set_bit(r, &ep->ob_region_map); + ep->ob_addr[r] =3D addr; + + return 0; +} + +static void cdns_pcie_hpa_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn, + phys_addr_t addr) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + u32 r; + + for (r =3D 0; r < ep->max_regions - 1; r++) + if (ep->ob_addr[r] =3D=3D addr) + break; + + if (r =3D=3D ep->max_regions - 1) + return; + + cdns_pcie_hpa_reset_outbound_region(pcie, r); + + ep->ob_addr[r] =3D 0; + clear_bit(r, &ep->ob_region_map); +} + +static void cdns_pcie_hpa_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn, u= 8 intx, + bool assert) +{ + struct cdns_pcie *pcie =3D &ep->pcie; + unsigned long flags; + u32 offset; + u16 status; + u8 msg_code; + + intx &=3D 3; + + /* Set the outbound region if needed */ + if (unlikely(ep->irq_pci_addr !=3D CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY || + ep->irq_pci_fn !=3D fn)) { + /* First region was reserved for IRQ writes */ + cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, 0, fn, 0, ep->irq= _phys_addr); + ep->irq_pci_addr =3D CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY; + ep->irq_pci_fn =3D fn; + } + + if (assert) { + ep->irq_pending |=3D BIT(intx); + msg_code =3D PCIE_MSG_CODE_ASSERT_INTA + intx; + } else { + ep->irq_pending &=3D ~BIT(intx); + msg_code =3D PCIE_MSG_CODE_DEASSERT_INTA + intx; + } + + spin_lock_irqsave(&ep->lock, flags); + status =3D cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS); + if (((status & PCI_STATUS_INTERRUPT) !=3D 0) ^ (ep->irq_pending !=3D 0)) { + status ^=3D PCI_STATUS_INTERRUPT; + cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status); + } + spin_unlock_irqrestore(&ep->lock, flags); + + offset =3D CDNS_PCIE_NORMAL_MSG_ROUTING(PCIE_MSG_TYPE_R_RC) | + CDNS_PCIE_NORMAL_MSG_CODE(msg_code); + writel(0, ep->irq_cpu_addr + offset); +} + +static int cdns_pcie_hpa_ep_raise_intx_irq(struct cdns_pcie_ep *ep, u8 fn,= u8 vfn, + u8 intx) +{ + u16 cmd; + + cmd =3D cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND); + if (cmd & PCI_COMMAND_INTX_DISABLE) + return -EINVAL; + + cdns_pcie_hpa_ep_assert_intx(ep, fn, intx, true); + + /* The mdelay() value was taken from dra7xx_pcie_raise_intx_irq() */ + mdelay(1); + cdns_pcie_hpa_ep_assert_intx(ep, fn, intx, false); + return 0; +} + +static int cdns_pcie_hpa_ep_raise_msi_irq(struct cdns_pcie_ep *ep, u8 fn, = u8 vfn, + u8 interrupt_num) +{ + struct cdns_pcie *pcie =3D &ep->pcie; + u32 cap =3D CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET; + u16 flags, mme, data, data_mask; + u8 msi_count; + u64 pci_addr, pci_addr_mask =3D 0xff; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI feature has been enabled by the PCI host */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS); + if (!(flags & PCI_MSI_FLAGS_ENABLE)) + return -EINVAL; + + /* Get the number of enabled MSIs */ + mme =3D FIELD_GET(PCI_MSI_FLAGS_QSIZE, flags); + msi_count =3D 1 << mme; + if (!interrupt_num || interrupt_num > msi_count) + return -EINVAL; + + /* Compute the data value to be written */ + data_mask =3D msi_count - 1; + data =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64); + data =3D (data & ~data_mask) | ((interrupt_num - 1) & data_mask); + + /* Get the PCI address where to write the data into */ + pci_addr =3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI); + pci_addr <<=3D 32; + pci_addr |=3D cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO); + pci_addr &=3D GENMASK_ULL(63, 2); + + /* Set the outbound region if needed */ + if (unlikely(ep->irq_pci_addr !=3D (pci_addr & ~pci_addr_mask) || + ep->irq_pci_fn !=3D fn)) { + /* First region was reserved for IRQ writes */ + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, 0, + false, + ep->irq_phys_addr, + pci_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr =3D (pci_addr & ~pci_addr_mask); + ep->irq_pci_fn =3D fn; + } + writel(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask)); + + return 0; +} + +static int cdns_pcie_hpa_ep_raise_msix_irq(struct cdns_pcie_ep *ep, u8 fn,= u8 vfn, + u16 interrupt_num) +{ + u32 cap =3D CDNS_PCIE_EP_FUNC_MSIX_CAP_OFFSET; + u32 tbl_offset, msg_data, reg; + struct cdns_pcie *pcie =3D &ep->pcie; + struct pci_epf_msix_tbl *msix_tbl; + struct cdns_pcie_epf *epf; + u64 pci_addr_mask =3D 0xff; + u64 msg_addr; + u16 flags; + u8 bir; + + epf =3D &ep->epf[fn]; + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + + /* Check whether the MSI-X feature has been enabled by the PCI host */ + flags =3D cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSIX_FLAGS); + if (!(flags & PCI_MSIX_FLAGS_ENABLE)) + return -EINVAL; + + reg =3D cap + PCI_MSIX_TABLE; + tbl_offset =3D cdns_pcie_ep_fn_readl(pcie, fn, reg); + bir =3D FIELD_GET(PCI_MSIX_TABLE_BIR, tbl_offset); + tbl_offset &=3D PCI_MSIX_TABLE_OFFSET; + + msix_tbl =3D epf->epf_bar[bir]->addr + tbl_offset; + msg_addr =3D msix_tbl[(interrupt_num - 1)].msg_addr; + msg_data =3D msix_tbl[(interrupt_num - 1)].msg_data; + + /* Set the outbound region if needed */ + if (ep->irq_pci_addr !=3D (msg_addr & ~pci_addr_mask) || + ep->irq_pci_fn !=3D fn) { + /* First region was reserved for IRQ writes */ + cdns_pcie_hpa_set_outbound_region(pcie, 0, fn, 0, + false, + ep->irq_phys_addr, + msg_addr & ~pci_addr_mask, + pci_addr_mask + 1); + ep->irq_pci_addr =3D (msg_addr & ~pci_addr_mask); + ep->irq_pci_fn =3D fn; + } + writel(msg_data, ep->irq_cpu_addr + (msg_addr & pci_addr_mask)); + + return 0; +} + +static int cdns_pcie_hpa_ep_raise_irq(struct pci_epc *epc, u8 fn, u8 vfn, + unsigned int type, u16 interrupt_num) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + struct device *dev =3D pcie->dev; + + switch (type) { + case PCI_IRQ_INTX: + if (vfn > 0) { + dev_err(dev, "Cannot raise INTX interrupts for VF\n"); + return -EINVAL; + } + return cdns_pcie_hpa_ep_raise_intx_irq(ep, fn, vfn, 0); + + case PCI_IRQ_MSI: + return cdns_pcie_hpa_ep_raise_msi_irq(ep, fn, vfn, interrupt_num); + + case PCI_IRQ_MSIX: + return cdns_pcie_hpa_ep_raise_msix_irq(ep, fn, vfn, interrupt_num); + + default: + break; + } + + return -EINVAL; +} + +static int cdns_pcie_hpa_ep_start(struct pci_epc *epc) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie *pcie =3D &ep->pcie; + struct device *dev =3D pcie->dev; + int max_epfs =3D sizeof(epc->function_num_map) * 8; + int ret, epf, last_fn; + u32 reg, value; + + /* + * BIT(0) is hardwired to 1, hence function 0 is always enabled + * and can't be disabled anyway + */ + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_LM_EP_FUNC_CFG, epc->function_num_map); + + /* + * Next function field in ARI_CAP_AND_CTR register for last function + * should be 0 and clear Next Function Number field for the last + * function used + */ + last_fn =3D find_last_bit(&epc->function_num_map, BITS_PER_LONG); + reg =3D CDNS_PCIE_CORE_PF_I_ARI_CAP_AND_CTRL(last_fn); + value =3D cdns_pcie_readl(pcie, reg); + value &=3D ~CDNS_PCIE_ARI_CAP_NFN_MASK; + cdns_pcie_writel(pcie, reg, value); + + if (ep->quirk_disable_flr) { + for (epf =3D 0; epf < max_epfs; epf++) { + if (!(epc->function_num_map & BIT(epf))) + continue; + + value =3D cdns_pcie_ep_fn_readl(pcie, epf, + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP); + value &=3D ~PCI_EXP_DEVCAP_FLR; + cdns_pcie_ep_fn_writel(pcie, epf, + CDNS_PCIE_EP_FUNC_DEV_CAP_OFFSET + + PCI_EXP_DEVCAP, value); + } + } + + ret =3D cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + return 0; +} + +static int cdns_pcie_hpa_ep_set_bar(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_bar *epf_bar) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie_epf *epf =3D &ep->epf[fn]; + struct cdns_pcie *pcie =3D &ep->pcie; + dma_addr_t bar_phys =3D epf_bar->phys_addr; + enum pci_barno bar =3D epf_bar->barno; + int flags =3D epf_bar->flags; + u32 addr0, addr1, reg, cfg, b, aperture, ctrl; + u64 sz; + + /* BAR size is 2^(aperture + 7) */ + sz =3D max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE); + + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values + */ + sz =3D 1ULL << fls64(sz - 1); + + /* 128B -> 0, 256B -> 1, 512B -> 2, ... */ + aperture =3D ilog2(sz) - 7; + + if ((flags & PCI_BASE_ADDRESS_SPACE) =3D=3D PCI_BASE_ADDRESS_SPACE_IO) { + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS; + } else { + bool is_prefetch =3D !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH); + bool is_64bits =3D !!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64); + + if (is_64bits && (bar & 1)) + return -EINVAL; + + if (is_64bits && is_prefetch) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS; + else if (is_prefetch) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS; + else if (is_64bits) + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS; + else + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS; + } + + addr0 =3D lower_32_bits(bar_phys); + addr1 =3D upper_32_bits(bar_phys); + + if (vfn =3D=3D 1) + reg =3D CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn); + else + reg =3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn); + b =3D (bar < BAR_4) ? bar : bar - BAR_4; + + if (vfn =3D=3D 0 || vfn =3D=3D 1) { + cfg =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, reg); + cfg &=3D ~(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |=3D (CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl)); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, reg, cfg); + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), addr1); + + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + epf->epf_bar[bar] =3D epf_bar; + + return 0; +} + +static void cdns_pcie_hpa_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn, + struct pci_epf_bar *epf_bar) +{ + struct cdns_pcie_ep *ep =3D epc_get_drvdata(epc); + struct cdns_pcie_epf *epf =3D &ep->epf[fn]; + struct cdns_pcie *pcie =3D &ep->pcie; + enum pci_barno bar =3D epf_bar->barno; + u32 reg, cfg, b, ctrl; + + if (vfn =3D=3D 1) + reg =3D CDNS_PCIE_HPA_LM_EP_VFUNC_BAR_CFG(bar, fn); + else + reg =3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG(bar, fn); + b =3D (bar < BAR_4) ? bar : bar - BAR_4; + + if (vfn =3D=3D 0 || vfn =3D=3D 1) { + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; + cfg =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, reg); + cfg &=3D ~(CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) | + CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b)); + cfg |=3D CDNS_PCIE_HPA_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, reg, cfg); + } + + fn =3D cdns_pcie_get_fn_from_vfn(pcie, fn, vfn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER_COMMON, + CDNS_PCIE_HPA_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0); + + if (vfn > 0) + epf =3D &epf->epf[vfn - 1]; + epf->epf_bar[bar] =3D NULL; +} + +static const struct pci_epc_ops cdns_pcie_hpa_epc_ops =3D { + .write_header =3D cdns_pcie_ep_write_header, + .set_bar =3D cdns_pcie_hpa_ep_set_bar, + .clear_bar =3D cdns_pcie_hpa_ep_clear_bar, + .map_addr =3D cdns_pcie_hpa_ep_map_addr, + .unmap_addr =3D cdns_pcie_hpa_ep_unmap_addr, + .set_msi =3D cdns_pcie_ep_set_msi, + .get_msi =3D cdns_pcie_ep_get_msi, + .set_msix =3D cdns_pcie_ep_set_msix, + .get_msix =3D cdns_pcie_ep_get_msix, + .raise_irq =3D cdns_pcie_hpa_ep_raise_irq, + .map_msi_irq =3D cdns_pcie_ep_map_msi_irq, + .start =3D cdns_pcie_hpa_ep_start, + .get_features =3D cdns_pcie_ep_get_features, +}; + +int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) +{ + struct device *dev =3D ep->pcie.dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct device_node *np =3D dev->of_node; + struct cdns_pcie *pcie =3D &ep->pcie; + struct cdns_pcie_epf *epf; + struct resource *res; + struct pci_epc *epc; + int ret; + int i; + + pcie->is_rc =3D false; + + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); + if (!res) { + dev_err(dev, "missing \"mem\"\n"); + return -EINVAL; + } + pcie->mem_res =3D res; + + ep->max_regions =3D CDNS_PCIE_MAX_OB; + of_property_read_u32(np, "cdns,max-outbound-regions", &ep->max_regions); + + ep->ob_addr =3D devm_kcalloc(dev, + ep->max_regions, sizeof(*ep->ob_addr), + GFP_KERNEL); + if (!ep->ob_addr) + return -ENOMEM; + + epc =3D devm_pci_epc_create(dev, &cdns_pcie_hpa_epc_ops); + if (IS_ERR(epc)) { + dev_err(dev, "failed to create epc device\n"); + return PTR_ERR(epc); + } + + epc_set_drvdata(epc, ep); + + if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0) + epc->max_functions =3D 1; + + ep->epf =3D devm_kcalloc(dev, epc->max_functions, sizeof(*ep->epf), + GFP_KERNEL); + if (!ep->epf) + return -ENOMEM; + + epc->max_vfs =3D devm_kcalloc(dev, epc->max_functions, + sizeof(*epc->max_vfs), GFP_KERNEL); + if (!epc->max_vfs) + return -ENOMEM; + + ret =3D of_property_read_u8_array(np, "max-virtual-functions", + epc->max_vfs, epc->max_functions); + if (ret =3D=3D 0) { + for (i =3D 0; i < epc->max_functions; i++) { + epf =3D &ep->epf[i]; + if (epc->max_vfs[i] =3D=3D 0) + continue; + epf->epf =3D devm_kcalloc(dev, epc->max_vfs[i], + sizeof(*ep->epf), GFP_KERNEL); + if (!epf->epf) + return -ENOMEM; + } + } + + ret =3D pci_epc_mem_init(epc, pcie->mem_res->start, + resource_size(pcie->mem_res), PAGE_SIZE); + if (ret < 0) { + dev_err(dev, "failed to initialize the memory space\n"); + return ret; + } + + ep->irq_cpu_addr =3D pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr, + SZ_128K); + if (!ep->irq_cpu_addr) { + dev_err(dev, "failed to reserve memory space for MSI\n"); + ret =3D -ENOMEM; + goto free_epc_mem; + } + ep->irq_pci_addr =3D CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE; + /* Reserve region 0 for IRQs */ + set_bit(0, &ep->ob_region_map); + + if (ep->quirk_detect_quiet_flag) + cdns_pcie_hpa_detect_quiet_min_delay_set(&ep->pcie); + + spin_lock_init(&ep->lock); + + pci_epc_init_notify(epc); + + return 0; + + free_epc_mem: + pci_epc_mem_exit(epc); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_ep_setup); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c b/drive= rs/pci/controller/cadence/pcie-cadence-host-hpa.c new file mode 100644 index 000000000000..b2e570f2c047 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-host-hpa.c @@ -0,0 +1,585 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe host controller driver. +// Author: Manikandan K Pillai + +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +static u8 bar_aperture_mask[] =3D { + [RP_BAR0] =3D 0x1F, + [RP_BAR1] =3D 0xF, +}; + +void __iomem *cdns_pci_hpa_map_bus(struct pci_bus *bus, unsigned int devfn, + int where) +{ + struct pci_host_bridge *bridge =3D pci_find_host_bridge(bus); + struct cdns_pcie_rc *rc =3D pci_host_bridge_priv(bridge); + struct cdns_pcie *pcie =3D &rc->pcie; + unsigned int busn =3D bus->number; + u32 addr0, desc0, desc1, ctrl0; + u32 regval; + + if (pci_is_root_bus(bus)) { + /* + * Only the root port (devfn =3D=3D 0) is connected to this bus. + * All other PCI devices are behind some bridge hence on another + * bus. + */ + if (devfn) + return NULL; + + return pcie->reg_base + (where & 0xfff); + } + + /* Clear AXI link-down status */ + regval =3D cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT= _LINKDOWN); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_AT_LINKDOWN, + (regval & ~GENMASK(0, 0))); + + desc0 =3D 0; + desc1 =3D 0; + ctrl0 =3D 0; + + /* Update Output registers for AXI region 0 */ + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(12) | + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) | + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_BUS(busn); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), addr0); + + desc1 =3D cdns_pcie_hpa_readl(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0)); + desc1 &=3D ~CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN_MASK; + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + + if (busn =3D=3D bridge->busnr + 1) + desc0 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE0; + else + desc0 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_CONF_TYPE1; + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), ctrl0); + + return rc->cfg_base + (where & 0xfff); +} + +int cdns_pcie_hpa_host_wait_for_link(struct cdns_pcie *pcie) +{ + struct device *dev =3D pcie->dev; + int retries; + + /* Check if the link is up or not */ + for (retries =3D 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { + if (cdns_pcie_hpa_link_up(pcie)) { + dev_info(dev, "Link up\n"); + return 0; + } + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); + } + return -ETIMEDOUT; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_wait_for_link); + +int cdns_pcie_hpa_host_start_link(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + int ret; + + ret =3D cdns_pcie_hpa_host_wait_for_link(pcie); + + /* Retrain link for Gen2 training defect if quirk flag is set */ + if (!ret && rc->quirk_retrain_flag) + ret =3D cdns_pcie_retrain(pcie); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_start_link); + +static struct pci_ops cdns_pcie_hpa_host_ops =3D { + .map_bus =3D cdns_pci_hpa_map_bus, + .read =3D pci_generic_config_read, + .write =3D pci_generic_config_write, +}; + +static void cdns_pcie_hpa_host_enable_ptm_response(struct cdns_pcie *pcie) +{ + u32 val; + + val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_C= TRL); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_LM_PTM_CTRL, + val | CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN); +} + +static int cdns_pcie_hpa_host_bar_ib_config(struct cdns_pcie_rc *rc, + enum cdns_pcie_rp_bar bar, + u64 cpu_addr, u64 size, + unsigned long flags) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + u32 addr0, addr1, aperture, value; + + if (!rc->avail_ib_bar[bar]) + return -EBUSY; + + rc->avail_ib_bar[bar] =3D false; + + aperture =3D ilog2(size); + addr0 =3D CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0_NBITS(aperture) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, + CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR0(bar), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_MASTER, + CDNS_PCIE_HPA_AT_IB_RP_BAR_ADDR1(bar), addr1); + + if (bar =3D=3D RP_NO_BAR) + return 0; + + value =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_H= PA_LM_RC_BAR_CFG); + value &=3D ~(HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) | + HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) | + HPA_LM_RC_BAR_CFG_APERTURE(bar, bar_aperture_mask[bar] + 2)); + if (size + cpu_addr >=3D SZ_4G) { + if (!(flags & IORESOURCE_PREFETCH)) + value |=3D HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar); + value |=3D HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar); + } else { + if (!(flags & IORESOURCE_PREFETCH)) + value |=3D HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar); + value |=3D HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar); + } + + value |=3D HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, CDNS_PCIE_HPA_LM_RC_= BAR_CFG, value); + + return 0; +} + +static int cdns_pcie_hpa_host_bar_config(struct cdns_pcie_rc *rc, + struct resource_entry *entry) +{ + u64 cpu_addr, pci_addr, size, winsize; + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + enum cdns_pcie_rp_bar bar; + unsigned long flags; + int ret; + + cpu_addr =3D entry->res->start; + pci_addr =3D entry->res->start - entry->offset; + flags =3D entry->res->flags; + size =3D resource_size(entry->res); + + if (entry->offset) { + dev_err(dev, "PCI addr: %llx must be equal to CPU addr: %llx\n", + pci_addr, cpu_addr); + return -EINVAL; + } + + while (size > 0) { + /* + * Try to find a minimum BAR whose size is greater than + * or equal to the remaining resource_entry size. This will + * fail if the size of each of the available BARs is less than + * the remaining resource_entry size. + * + * If a minimum BAR is found, IB ATU will be configured and + * exited. + */ + bar =3D cdns_pcie_host_find_min_bar(rc, size); + if (bar !=3D RP_BAR_UNDEFINED) { + ret =3D cdns_pcie_hpa_host_bar_ib_config(rc, bar, cpu_addr, + size, flags); + if (ret) + dev_err(dev, "IB BAR: %d config failed\n", bar); + return ret; + } + + /* + * If the control reaches here, it would mean the remaining + * resource_entry size cannot be fitted in a single BAR. So we + * find a maximum BAR whose size is less than or equal to the + * remaining resource_entry size and split the resource entry + * so that part of resource entry is fitted inside the maximum + * BAR. The remaining size would be fitted during the next + * iteration of the loop. + * + * If a maximum BAR is not found, there is no way we can fit + * this resource_entry, so we error out. + */ + bar =3D cdns_pcie_host_find_max_bar(rc, size); + if (bar =3D=3D RP_BAR_UNDEFINED) { + dev_err(dev, "No free BAR to map cpu_addr %llx\n", + cpu_addr); + return -EINVAL; + } + + winsize =3D bar_max_size[bar]; + ret =3D cdns_pcie_hpa_host_bar_ib_config(rc, bar, cpu_addr, winsize, fla= gs); + if (ret) { + dev_err(dev, "IB BAR: %d config failed\n", bar); + return ret; + } + + size -=3D winsize; + cpu_addr +=3D winsize; + } + + return 0; +} + +static int cdns_pcie_hpa_host_map_dma_ranges(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D pcie->dev; + struct device_node *np =3D dev->of_node; + struct pci_host_bridge *bridge; + struct resource_entry *entry; + u32 no_bar_nbits =3D 32; + int err; + + bridge =3D pci_host_bridge_from_priv(rc); + if (!bridge) + return -ENOMEM; + + if (list_empty(&bridge->dma_ranges)) { + of_property_read_u32(np, "cdns,no-bar-match-nbits", + &no_bar_nbits); + err =3D cdns_pcie_hpa_host_bar_ib_config(rc, RP_NO_BAR, 0x0, + (u64)1 << no_bar_nbits, 0); + if (err) + dev_err(dev, "IB BAR: %d config failed\n", RP_NO_BAR); + return err; + } + + list_sort(NULL, &bridge->dma_ranges, cdns_pcie_host_dma_ranges_cmp); + + resource_list_for_each_entry(entry, &bridge->dma_ranges) { + err =3D cdns_pcie_hpa_host_bar_config(rc, entry); + if (err) { + dev_err(dev, "Fail to configure IB using dma-ranges\n"); + return err; + } + } + + return 0; +} + +static int cdns_pcie_hpa_host_init_root_port(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + u32 value, ctrl; + + /* + * Set the root complex BAR configuration register: + * - disable both BAR0 and BAR1 + * - enable Prefetchable Memory Base and Limit registers in type 1 + * config space (64 bits) + * - enable IO Base and Limit registers in type 1 config + * space (32 bits) + */ + + ctrl =3D CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED; + value =3D CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR0_CTRL(ctrl) | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_BAR1_CTRL(ctrl) | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_ENABLE | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_PREFETCH_MEM_64BITS | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_ENABLE | + CDNS_PCIE_HPA_LM_RC_BAR_CFG_IO_32BITS; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_CFG_CTRL_REG, + CDNS_PCIE_HPA_LM_RC_BAR_CFG, value); + + if (rc->vendor_id !=3D 0xffff) + cdns_pcie_hpa_rp_writew(pcie, PCI_VENDOR_ID, rc->vendor_id); + + if (rc->device_id !=3D 0xffff) + cdns_pcie_hpa_rp_writew(pcie, PCI_DEVICE_ID, rc->device_id); + + cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_REVISION, 0); + cdns_pcie_hpa_rp_writeb(pcie, PCI_CLASS_PROG, 0); + cdns_pcie_hpa_rp_writew(pcie, PCI_CLASS_DEVICE, PCI_CLASS_BRIDGE_PCI); + + return 0; +} + +static void cdns_pcie_hpa_create_region_for_ecam(struct cdns_pcie_rc *rc) +{ + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource *cfg_res =3D rc->cfg_res; + struct cdns_pcie *pcie =3D &rc->pcie; + u32 value, root_port_req_id_reg, pcie_bus_number_reg; + u32 ecam_addr_0, region_size_0, request_id_0; + int busnr =3D 0, secbus =3D 0, subbus =3D 0; + struct resource_entry *entry; + resource_size_t size; + u32 axi_address_low; + int nbits; + u64 sz; + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) { + busnr =3D entry->res->start; + secbus =3D (busnr < 0xff) ? (busnr + 1) : 0xff; + subbus =3D entry->res->end; + } + size =3D resource_size(cfg_res); + sz =3D 1ULL << fls64(size - 1); + nbits =3D ilog2(sz); + if (nbits < 8) + nbits =3D 8; + + root_port_req_id_reg =3D ((busnr & 0xff) << 8); + pcie_bus_number_reg =3D ((subbus & 0xff) << 16) | ((secbus & 0xff) << 8) | + (busnr & 0xff); + ecam_addr_0 =3D cfg_res->start; + region_size_0 =3D nbits - 1; + request_id_0 =3D ((busnr & 0xff) << 8); + +#define CDNS_PCIE_HPA_TAG_MANAGEMENT (0x0) + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_TAG_MANAGEMENT, 0x200000); + + /* Taking slave err as OKAY */ +#define CDNS_PCIE_HPA_SLAVE_RESP (0x100) + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, CDNS_PCIE_HPA_SLAVE_RESP, + 0x0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_SLAVE_RESP + 0x4, 0x0); + + /* Program the register "i_root_port_req_id_reg" with RP's BDF */ +#define I_ROOT_PORT_REQ_ID_REG (0x141c) + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, I_ROOT_PORT_REQ_ID_REG, + root_port_req_id_reg); + + /** + * Program the register "i_pcie_bus_numbers" with Primary(RP's bus number= ), + * secondary and subordinate bus numbers + */ +#define I_PCIE_BUS_NUMBERS (CDNS_PCIE_HPA_RP_BASE + 0x18) + cdns_pcie_hpa_writel(pcie, REG_BANK_RP, I_PCIE_BUS_NUMBERS, + pcie_bus_number_reg); + + /* Program the register "lm_hal_sbsa_ctrl[0]" to enable the sbsa */ +#define LM_HAL_SBSA_CTRL (0x1170) + value =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, LM_HAL_SBSA_CTRL); + value |=3D BIT(0); + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, LM_HAL_SBSA_CTRL, value); + + /* Program region[0] for ECAM */ + axi_address_low =3D (ecam_addr_0 & 0xfff00000) | region_size_0; + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), + axi_address_low); + + /* rc0-high-axi-address */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), 0x0); + /* Type-1 CFG */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(0), 0x05000000); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), + (request_id_0 << 16)); + + /* All AXI bits pass through PCIe */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(0), 0x1b); + /* PCIe address-high */ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(0), 0x06000000); +} + +static void cdns_pcie_hpa_create_region_for_cfg(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource *cfg_res =3D rc->cfg_res; + struct resource_entry *entry; + u64 cpu_addr =3D cfg_res->start; + u32 addr0, addr1, desc1; + int busnr =3D 0; + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr =3D entry->res->start; + + /* + * Reserve region 0 for PCI configure space accesses: + * OB_REGION_PCI_ADDR0 and OB_REGION_DESC0 are updated dynamically by + * cdns_pci_map_bus(), other region registers are set here once for all + */ + addr1 =3D 0; + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(0), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(0), desc1); + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(12) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(0), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(0), addr1); +} + +static int cdns_pcie_hpa_host_init_address_translation(struct cdns_pcie_rc= *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(rc); + struct resource_entry *entry; + int r =3D 0, busnr =3D 0; + + if (rc->ecam_support_flag) + cdns_pcie_hpa_create_region_for_ecam(rc); + else + cdns_pcie_hpa_create_region_for_cfg(rc); + + entry =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (entry) + busnr =3D entry->res->start; + + r++; + if (pcie->msg_res) + cdns_pcie_hpa_set_outbound_region_for_normal_msg(pcie, busnr, 0, r, + pcie->msg_res->start); + + r++; + resource_list_for_each_entry(entry, &bridge->windows) { + struct resource *res =3D entry->res; + u64 pci_addr =3D res->start - entry->offset; + + if (resource_type(res) =3D=3D IORESOURCE_IO) + cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, + true, + pci_pio_to_address(res->start), + pci_addr, + resource_size(res)); + else + cdns_pcie_hpa_set_outbound_region(pcie, busnr, 0, r, + false, + res->start, + pci_addr, + resource_size(res)); + + r++; + } + + if (rc->no_inbound_flag) + return 0; + else + return cdns_pcie_hpa_host_map_dma_ranges(rc); +} + +int cdns_pcie_hpa_host_init(struct cdns_pcie_rc *rc) +{ + int err; + + err =3D cdns_pcie_hpa_host_init_root_port(rc); + if (err) + return err; + + return cdns_pcie_hpa_host_init_address_translation(rc); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_init); + +int cdns_pcie_hpa_host_link_setup(struct cdns_pcie_rc *rc) +{ + struct cdns_pcie *pcie =3D &rc->pcie; + struct device *dev =3D rc->pcie.dev; + int ret; + + if (rc->quirk_detect_quiet_flag) + cdns_pcie_hpa_detect_quiet_min_delay_set(&rc->pcie); + + cdns_pcie_hpa_host_enable_ptm_response(pcie); + + ret =3D cdns_pcie_start_link(pcie); + if (ret) { + dev_err(dev, "Failed to start link\n"); + return ret; + } + + ret =3D cdns_pcie_hpa_host_start_link(rc); + if (ret) + dev_dbg(dev, "PCIe link never came up\n"); + + return ret; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_link_setup); + +int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) +{ + struct device *dev =3D rc->pcie.dev; + struct platform_device *pdev =3D to_platform_device(dev); + struct pci_host_bridge *bridge; + enum cdns_pcie_rp_bar bar; + struct cdns_pcie *pcie; + struct resource *res; + int ret; + + bridge =3D pci_host_bridge_from_priv(rc); + if (!bridge) + return -ENOMEM; + + pcie =3D &rc->pcie; + pcie->is_rc =3D true; + + if (!pcie->reg_base) { + pcie->reg_base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(pcie->reg_base)) { + dev_err(dev, "missing \"reg\"\n"); + return PTR_ERR(pcie->reg_base); + } + } + + /* ECAM config space is remapped at glue layer */ + if (!rc->cfg_base) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + rc->cfg_base =3D devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(rc->cfg_base)) + return PTR_ERR(rc->cfg_base); + rc->cfg_res =3D res; + } + + ret =3D cdns_pcie_hpa_host_link_setup(rc); + if (ret) + return ret; + + for (bar =3D RP_BAR0; bar <=3D RP_NO_BAR; bar++) + rc->avail_ib_bar[bar] =3D true; + + ret =3D cdns_pcie_hpa_host_init(rc); + if (ret) + return ret; + + if (!bridge->ops) + bridge->ops =3D &cdns_pcie_hpa_host_ops; + + return pci_host_probe(bridge); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_host_setup); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence-hpa.c b/drivers/pc= i/controller/cadence/pcie-cadence-hpa.c new file mode 100644 index 000000000000..f8c0de4b7881 --- /dev/null +++ b/drivers/pci/controller/cadence/pcie-cadence-hpa.c @@ -0,0 +1,204 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2017 Cadence +// Cadence PCIe controller driver +// Author: Manikandan K Pillai + +#include +#include + +#include "pcie-cadence.h" + +bool cdns_pcie_hpa_link_up(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_DBG_STS_REG0); + if (pl_reg_val & GENMASK(0, 0)) + return true; + return false; +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_link_up); + +int cdns_pcie_hpa_start_link(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_LAYER_CFG0); + pl_reg_val |=3D CDNS_PCIE_HPA_LINK_TRNG_EN_MASK; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_LAYER_CFG0,= pl_reg_val); + return 0; +} + +void cdns_pcie_hpa_stop_link(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_P= HY_LAYER_CFG0); + pl_reg_val &=3D ~CDNS_PCIE_HPA_LINK_TRNG_EN_MASK; + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, CDNS_PCIE_HPA_PHY_LAYER_CFG0,= pl_reg_val); +} + +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie) +{ + u32 delay =3D 0x3; + u32 ltssm_control_cap; + + /* Set the LTSSM Detect Quiet state min. delay to 2ms */ + ltssm_control_cap =3D cdns_pcie_hpa_readl(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_LAYER_CFG0); + ltssm_control_cap =3D ((ltssm_control_cap & + ~CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY_MASK) | + CDNS_PCIE_HPA_DETECT_QUIET_MIN_DELAY(delay)); + + cdns_pcie_hpa_writel(pcie, REG_BANK_IP_REG, + CDNS_PCIE_HPA_PHY_LAYER_CFG0, ltssm_control_cap); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_detect_quiet_min_delay_set); + +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u= 8 fn, + u32 r, bool is_io, + u64 cpu_addr, u64 pci_addr, size_t size) +{ + /* + * roundup_pow_of_two() returns an unsigned long, which is not suited + * for 64bit values + */ + u64 sz =3D 1ULL << fls64(size - 1); + int nbits =3D ilog2(sz); + u32 addr0, addr1, desc0, desc1, ctrl0; + + if (nbits < 8) + nbits =3D 8; + + /* Set the PCI address */ + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0_NBITS(nbits) | + (lower_32_bits(pci_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(pci_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), addr1); + + /* Set the PCIe header descriptor */ + if (is_io) + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_IO; + else + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_MEM; + desc1 =3D 0; + ctrl0 =3D 0; + + /* + * Whether Bit [26] is set or not inside DESC0 register of the outbound + * PCIe descriptor, the PCI function number must be set into + * Bits [31:24] of DESC1 anyway. + * + * In Root Complex mode, the function number is always 0 but in Endpoint + * mode, the PCIe controller may support more than one function. This + * function number needs to be set properly into the outbound PCIe + * descriptor. + * + * Besides, setting Bit [26] is mandatory when in Root Complex mode: + * then the driver must provide the bus, resp. device, number in + * Bits [31:24] of DESC1, resp. Bits[23:16] of DESC0. Like the function + * number, the device number is always 0 in Root Complex mode. + * + * However when in Endpoint mode, we can clear Bit [26] of DESC0, hence + * the PCIe controller will use the captured values for the bus and + * device numbers. + */ + if (pcie->is_rc) { + /* The device and function numbers are always 0 */ + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | + CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + } else { + /* + * Use captured values for bus and device numbers but still + * need to set the function number + */ + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); + } + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region); + +void cdns_pcie_hpa_set_outbound_region_for_normal_msg(struct cdns_pcie *pc= ie, + u8 busnr, u8 fn, + u32 r, u64 cpu_addr) +{ + u32 addr0, addr1, desc0, desc1, ctrl0; + + desc0 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC0_TYPE_NORMAL_MSG; + desc1 =3D 0; + ctrl0 =3D 0; + + /* See cdns_pcie_set_outbound_region() comments above */ + if (pcie->is_rc) { + desc1 =3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_BUS(busnr) | + CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(0); + ctrl0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_BUS | + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0_SUPPLY_DEV_FN; + } else { + desc1 |=3D CDNS_PCIE_HPA_AT_OB_REGION_DESC1_DEVFN(fn); + } + + addr0 =3D CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0_NBITS(17) | + (lower_32_bits(cpu_addr) & GENMASK(31, 8)); + addr1 =3D upper_32_bits(cpu_addr); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), desc0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), desc1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), addr0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), addr1); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CTRL0(r), ctrl0); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_set_outbound_region_for_normal_msg); + +void cdns_pcie_hpa_reset_outbound_region(struct cdns_pcie *pcie, u32 r) +{ + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_PCI_ADDR1(r), 0); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_DESC1(r), 0); + + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR0(r), 0); + cdns_pcie_hpa_writel(pcie, REG_BANK_AXI_SLAVE, + CDNS_PCIE_HPA_AT_OB_REGION_CPU_ADDR1(r), 0); +} +EXPORT_SYMBOL_GPL(cdns_pcie_hpa_reset_outbound_region); + +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Cadence PCIe controller driver"); +MODULE_AUTHOR("Manikandan K Pillai "); diff --git a/drivers/pci/controller/cadence/pcie-cadence.c b/drivers/pci/co= ntroller/cadence/pcie-cadence.c index 51c9bc4eb174..aaf921ea70e0 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.c +++ b/drivers/pci/controller/cadence/pcie-cadence.c @@ -9,6 +9,17 @@ =20 #include "pcie-cadence.h" =20 +bool cdns_pcie_linkup(struct cdns_pcie *pcie) +{ + u32 pl_reg_val; + + pl_reg_val =3D cdns_pcie_readl(pcie, CDNS_PCIE_LM_BASE); + if (pl_reg_val & GENMASK(0, 0)) + return true; + return false; +} +EXPORT_SYMBOL_GPL(cdns_pcie_linkup); + void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie) { u32 delay =3D 0x3; diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/co= ntroller/cadence/pcie-cadence.h index 1174cf597bb0..f2eb3f09b21a 100644 --- a/drivers/pci/controller/cadence/pcie-cadence.h +++ b/drivers/pci/controller/cadence/pcie-cadence.h @@ -7,6 +7,7 @@ #define _PCIE_CADENCE_H =20 #include +#include #include #include #include @@ -42,9 +43,9 @@ enum cdns_pcie_reg_bank { }; =20 struct cdns_pcie_ops { - int (*start_link)(struct cdns_pcie *pcie); - void (*stop_link)(struct cdns_pcie *pcie); - bool (*link_up)(struct cdns_pcie *pcie); + int (*start_link)(struct cdns_pcie *pcie); + void (*stop_link)(struct cdns_pcie *pcie); + bool (*link_up)(struct cdns_pcie *pcie); u64 (*cpu_addr_fixup)(struct cdns_pcie *pcie, u64 cpu_addr); }; =20 @@ -76,6 +77,7 @@ struct cdns_plat_pcie_of_data { * struct cdns_pcie - private data for Cadence PCIe controller drivers * @reg_base: IO mapped register base * @mem_res: start/end offsets in the physical system memory to map PCI ac= cesses + * @msg_res: Region for send message to map PCI accesses * @dev: PCIe controller * @is_rc: tell whether the PCIe controller mode is Root Complex or Endpoi= nt. * @phy_count: number of supported PHY devices @@ -88,6 +90,7 @@ struct cdns_plat_pcie_of_data { struct cdns_pcie { void __iomem *reg_base; struct resource *mem_res; + struct resource *msg_res; struct device *dev; bool is_rc; int phy_count; @@ -110,6 +113,7 @@ struct cdns_pcie { * available * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk + * @ecam_support_flag: Whether the ECAM flag is supported */ struct cdns_pcie_rc { struct cdns_pcie pcie; @@ -120,6 +124,8 @@ struct cdns_pcie_rc { bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; unsigned int quirk_retrain_flag:1; unsigned int quirk_detect_quiet_flag:1; + unsigned int ecam_support_flag:1; + unsigned int no_inbound_flag:1; }; =20 /** @@ -303,6 +309,29 @@ static inline u16 cdns_pcie_rp_readw(struct cdns_pcie = *pcie, u32 reg) return cdns_pcie_read_sz(addr, 0x2); } =20 +static inline void cdns_pcie_hpa_rp_writeb(struct cdns_pcie *pcie, + u32 reg, u8 value) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x1, value); +} + +static inline void cdns_pcie_hpa_rp_writew(struct cdns_pcie *pcie, + u32 reg, u16 value) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + cdns_pcie_write_sz(addr, 0x2, value); +} + +static inline u16 cdns_pcie_hpa_rp_readw(struct cdns_pcie *pcie, u32 reg) +{ + void __iomem *addr =3D pcie->reg_base + CDNS_PCIE_HPA_RP_BASE + reg; + + return cdns_pcie_read_sz(addr, 0x2); +} + /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) @@ -367,6 +396,7 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc); void cdns_pcie_host_disable(struct cdns_pcie_rc *rc); void __iomem *cdns_pci_map_bus(struct pci_bus *bus, unsigned int devfn, int where); +int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc); #else static inline int cdns_pcie_host_link_setup(struct cdns_pcie_rc *rc) { @@ -383,6 +413,11 @@ static inline int cdns_pcie_host_setup(struct cdns_pci= e_rc *rc) return 0; } =20 +static inline int cdns_pcie_hpa_host_setup(struct cdns_pcie_rc *rc) +{ + return 0; +} + static inline void cdns_pcie_host_disable(struct cdns_pcie_rc *rc) { } @@ -397,6 +432,7 @@ static inline void __iomem *cdns_pci_map_bus(struct pci= _bus *bus, unsigned int d #if IS_ENABLED(CONFIG_PCIE_CADENCE_EP) int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep); void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep); +int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep); #else static inline int cdns_pcie_ep_setup(struct cdns_pcie_ep *ep) { @@ -406,8 +442,16 @@ static inline int cdns_pcie_ep_setup(struct cdns_pcie_= ep *ep) static inline void cdns_pcie_ep_disable(struct cdns_pcie_ep *ep) { } -#endif =20 +static inline int cdns_pcie_hpa_ep_setup(struct cdns_pcie_ep *ep) +{ + return 0; +} + +#endif +bool cdns_pcie_linkup(struct cdns_pcie *pcie); +int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie); +int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc); void cdns_pcie_detect_quiet_min_delay_set(struct cdns_pcie *pcie); =20 void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u8 fn, @@ -420,8 +464,26 @@ void cdns_pcie_set_outbound_region_for_normal_msg(stru= ct cdns_pcie *pcie, =20 void cdns_pcie_reset_outbound_region(struct cdns_pcie *pcie, u32 r); void cdns_pcie_disable_phy(struct cdns_pcie *pcie); -int cdns_pcie_enable_phy(struct cdns_pcie *pcie); -int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); +int cdns_pcie_enable_phy(struct cdns_pcie *pcie); +int cdns_pcie_init_phy(struct device *dev, struct cdns_pcie *pcie); +void cdns_pcie_hpa_detect_quiet_min_delay_set(struct cdns_pcie *pcie); +void cdns_pcie_hpa_set_outbound_region(struct cdns_pcie *pcie, u8 busnr, u= 8 fn, + u32 r, bool is_io, + u64 cpu_addr, u64 pci_addr, size_t size); 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Signed-off-by: Manikandan K Pillai Co-developed-by: Hans Zhang Signed-off-by: Hans Zhang --- drivers/pci/controller/cadence/pcie-cadence-plat.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/pci/controller/cadence/pcie-cadence-plat.c b/drivers/p= ci/controller/cadence/pcie-cadence-plat.c index b067a3296dd3..927ab5b8477c 100644 --- a/drivers/pci/controller/cadence/pcie-cadence-plat.c +++ b/drivers/pci/controller/cadence/pcie-cadence-plat.c @@ -31,6 +31,7 @@ static u64 cdns_plat_cpu_addr_fixup(struct cdns_pcie *pci= e, u64 cpu_addr) =20 static const struct cdns_pcie_ops cdns_plat_ops =3D { .cpu_addr_fixup =3D cdns_plat_cpu_addr_fixup, + .link_up =3D cdns_pcie_linkup, }; =20 static int cdns_plat_pcie_probe(struct platform_device *pdev) @@ -68,6 +69,11 @@ static int cdns_plat_pcie_probe(struct platform_device *= pdev) rc =3D pci_host_bridge_priv(bridge); rc->pcie.dev =3D dev; rc->pcie.ops =3D &cdns_plat_ops; + rc->pcie.is_rc =3D data->is_rc; + + /* Store the register bank offsets pointer */ + rc->pcie.cdns_pcie_reg_offsets =3D data; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id CD9D941604F2; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 10/15] dt-bindings: PCI: Add CIX Sky1 PCIe Root Complex bindings Date: Tue, 19 Aug 2025 19:52:34 +0800 Message-ID: <20250819115239.4170604-11-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E1:EE_|TYZPR06MB5843:EE_ X-MS-Office365-Filtering-Correlation-Id: a1e0304d-308b-4f97-96ce-08dddf173fe7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|82310400026|7416014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?ZPnsBIEz5yXHM5wBj5hFsxzqHif32rRa9r1JWsEcrnaW93EFQylC8BvHX4YL?= =?us-ascii?Q?q0CFBwugd6akSFJEcitCoeOhjHf+4DNYk2NsQSGpoPnaVtH3uulb49C1ANJb?= =?us-ascii?Q?xJPaejnMpWhmvJGmtcs3h5U33HVACK1o76jSe+AaR6lQpF3sbWOSmDhD2CkL?= =?us-ascii?Q?xFOHFXv1WaKfryiv5JnxWqUWF2hLGr942M376T/T0gsI1ec18wI4oGCgbrsf?= =?us-ascii?Q?/1gOueqCLK2s5I4h0FcKUTIwr4odL7LFyO1BxxdVKUMqQ3aQTeL27WzKZEOm?= =?us-ascii?Q?W1SXsCQ08qxLN399bIJaRydZhsGqsOdHF2R9wE/rorjOSim3lMPaFYcsHEGy?= =?us-ascii?Q?1GKZcNTWjEWbCrV+BInRSMYhwXuEct6gWlSnAfDLNuQ9KCaUmCIoCkaanj8X?= =?us-ascii?Q?RG/FS0C6zPNlPmWxFJ+1K6gpo1iclYn9Bq+U2lzsnmIkKWExgRE6k96mtXlg?= =?us-ascii?Q?8xn0MXwYMxyMi7batGaQbUoAXkU6YMnWI2qeGEAl+ACirInMlf0ceeoqBWP9?= =?us-ascii?Q?OydAZmBg0Sg5AHellx4bjVTjTH4ilR0RCbGKphxIq49k8MpBA0giHowtOgwQ?= =?us-ascii?Q?/xaLeOzCgq7G0esZVKgVJl+zxKFavQBFDiUJigtqdupGTAOYXtAAo5OXtsnW?= =?us-ascii?Q?LwLCgoUTB58dYKORbqlBYIRs+BFF+pd3T6QR9tnS8dmT+SdIJ36EhdKUiTT4?= =?us-ascii?Q?BgI8i+BTVNcfKgZRBI927D/6NaxIu9WmFOMuNp32TQCRcOhj+AjSRgnZfhP2?= =?us-ascii?Q?DFAm941x6giqDBCD0ELXmoVnJ9INISDDVHd6TBkE551kO1cDH/L4zsdtUxvw?= =?us-ascii?Q?uxUnpcZEtmtP4y5LsxGwCe+2izciWBvCf+c3SrHCKAWpjgF/3XhZRLVB5aNG?= =?us-ascii?Q?5edE0O34ea1fQrRIThdcHfCZxbDvHVZkUqYmWvgC/lD6cOxovnAx9Os/5GHH?= =?us-ascii?Q?FF0o77GjABrE9wzmrZfiiSDZcj81vw3nS4R4C0ZtoK4y2Z968fOjQspID8EP?= =?us-ascii?Q?GcYixnk0gNCaUzhAL7+EgBex4oY0HAzxyAlJ9LRDtZ42lzzvaAH0rxOTQrsU?= =?us-ascii?Q?RgQRall0xtsfffrHDoyGetDaxX5+p0kojhPB/wdBx+MVac/NSkcVWGNW5/z7?= =?us-ascii?Q?MmPm9QIRDvbGVW8jtfejYILQS5RzOegvi84vxQB1nf6fOE8HKGnd093FBzWA?= =?us-ascii?Q?SJunq22K7ZhLrCxZ7lunPT/bxZVTetP0ZNVwK+0dXrHNJjHVnRnyCfaT1ePO?= =?us-ascii?Q?89N6cABoTL2L1fsx8weTArvo6VJPqasjc4E8eZ6jIVyzOJhnFfO7gPW7Upo/?= =?us-ascii?Q?T7MmNxaUM9/Kc6DuCgsvCsa50MPToda+Dcxqv49or0+eAlnB/6vQ+2HRvhZL?= =?us-ascii?Q?I98IF+IH1PPxyRSuKZiZdh1/OIAVo5+yij4IEwCShgKeFnT2nD3kwkSVoGTO?= =?us-ascii?Q?Ptv030ica9bPFD1zPOYGHuHshbxpcgZAmTzpZLdR/3kvhwVXOxhBqA=3D=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(82310400026)(7416014)(36860700013)(1800799024);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:10.4163 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a1e0304d-308b-4f97-96ce-08dddf173fe7 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E1.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB5843 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Document the bindings for CIX Sky1 PCIe Controller configured in root complex mode with five root port. Supports 4 INTx, MSI and MSI-x interrupts from the ARM GICv3 controller. Signed-off-by: Hans Zhang Reviewed-by: Krzysztof Kozlowski --- Changes for v8: - Fixed the error issue of DT binding. (Rob and Krzysztof) - The rcsu register is split into two parts: rcsu_strap and rcsu_status. --- .../bindings/pci/cix,sky1-pcie-host.yaml | 83 +++++++++++++++++++ 1 file changed, 83 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/cix,sky1-pcie-hos= t.yaml diff --git a/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml = b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml new file mode 100644 index 000000000000..b910a42e0843 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/cix,sky1-pcie-host.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/cix,sky1-pcie-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: CIX Sky1 PCIe Root Complex + +maintainers: + - Hans Zhang + +description: + PCIe root complex controller based on the Cadence PCIe core. + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +properties: + compatible: + const: cix,sky1-pcie-host + + reg: + items: + - description: PCIe controller registers. + - description: ECAM registers. + - description: Remote CIX System Unit strap registers. + - description: Remote CIX System Unit status registers. + - description: Region for sending messages registers. + + reg-names: + items: + - const: reg + - const: cfg + - const: rcsu_strap + - const: rcsu_status + - const: msg + + ranges: + maxItems: 3 + +required: + - compatible + - ranges + - bus-range + - device_type + - interrupt-map + - interrupt-map-mask + - msi-map + +unevaluatedProperties: false + +examples: + - | + #include + + soc { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@a010000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000300 0x00 0x100>, + <0x00 0x0a000400 0x00 0x100>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges =3D <0x01000000 0x00 0x60100000 0x00 0x60100000 0x00 0x= 00100000>, + <0x02000000 0x00 0x60200000 0x00 0x60200000 0x00 0x1f= e00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00= 000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL= _HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_H= IGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_H= IGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_H= IGH 0>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; 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This ID will be used by the CIX Sky1 PCIe host controller driver. Signed-off-by: Hans Zhang Acked-by: Manivannan Sadhasivam --- include/linux/pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h index 92ffc4373f6d..24b04d085920 100644 --- a/include/linux/pci_ids.h +++ b/include/linux/pci_ids.h @@ -2631,6 +2631,9 @@ =20 #define PCI_VENDOR_ID_CXL 0x1e98 =20 +#define PCI_VENDOR_ID_CIX 0x1f6c +#define PCI_DEVICE_ID_CIX_SKY1 0x0001 + #define PCI_VENDOR_ID_TEHUTI 0x1fc9 #define PCI_DEVICE_ID_TEHUTI_3009 0x3009 #define PCI_DEVICE_ID_TEHUTI_3010 0x3010 --=20 2.49.0 From nobody Sat Oct 4 06:35:23 2025 Received: from SEYPR02CU001.outbound.protection.outlook.com (mail-koreacentralazon11023108.outbound.protection.outlook.com [40.107.44.108]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A00D932C304; Tue, 19 Aug 2025 11:55:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=40.107.44.108 ARC-Seal: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755604518; cv=fail; b=tupzy6W3DOz2gavJcmDKymtTmKVD199scIdilMaLTKERk9MiP3S3j7MY+BirDfroNw9qkM0LZcP96NLJ8/YTEvIvH8FbWvVJ7WZL8c+avgp9yhlzMmAxAHalymffdPF3wRQ03pLNLFP+beKO3tdeAqZLA1jOl9LR4gCEEsXU5lg= ARC-Message-Signature: i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755604518; c=relaxed/simple; bh=I9n3OJhkKNg3PyE7QqnlRzkDpU7dM8IxaDrQgBrLcao=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RV712fox1phNDIAFBb5XMnujvN0/f5xIpK9SxTULHNj1rRg48vNqtKR/c+oC4PSMh7+l4AxSy6ZdRfGvLxg7UsBg8Q7cd8c/qxDAfCyyKgl4FEbg56Ww94PtIdN1uFdTDqu4yrxH4i//MnOW/cCypok8x0G0QAGbOxalu6QobzQ= ARC-Authentication-Results: i=2; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com; spf=pass smtp.mailfrom=cixtech.com; arc=fail smtp.client-ip=40.107.44.108 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=cixtech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cixtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=jxaVPd1696OrRhMrEcEM/0HEkOua+4H34Xo94lFLZkKBI4soUALRAoop3shikRhktPhkkl3SDKA3QM8wDqXfFY0050s0GEGNl/6WLWMIxWkDSHs6HqgzbgJxf5OQMyBy/nzfx2j+wp77ZsQle3kk8l3HjS8Sh6kIuceAMpvQyytbW0V8cr79TsJOdgv2LOtgPC0k2/94TquvIvD/SyXyWrCliaK7gPxl3NhztlpdIl0JGY9Rmy1FtCiGD66KCvxKYO9fzfNbx9RDhE6HqIju4v8DH0iYmmqUvlpuFT4iV2xghoNTehaIcDqINmVfmRoqqKVPnn1vG4CstLM3OGSifA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=NGKpRDPv9FYZKhjnMZytXKbMXDRsF2swP/T63r4R7ps=; b=gmojmDWDwUniHdknjA6Dnql2+Ggou2q3rQUk1hwGalKRN6R35JTinyOvZulJwemTq9wwmvEYt9tjSkArJdrtFymZsh4ntsI55i4ntUHvri5wfnUcteFEcYP5L2+8SlEnuiKjbk29/uHnU0YLvcoRTE9D/ZL3u7tCbZ5ZWgUawkhalNOK2A4+wuTziC7Kh5FwWAURq6AFXP0zlOlhvDRGvMiFYUryBr5nbTD5YrPGZekPMGPcsdECsBMj/hkPmd93SJbAfWDWkijAFvFVcoVnntCYVnwW2rzz0fSKPxi8qLGadnoDERgj0xa9w9XJ0os4xHB1eu3ATcJ9tRlrHsCaLw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=cadence.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from TY2PR06CA0047.apcprd06.prod.outlook.com (2603:1096:404:2e::35) by TYZPR06MB6513.apcprd06.prod.outlook.com (2603:1096:400:452::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9031.24; Tue, 19 Aug 2025 11:55:12 +0000 Received: from OSA0EPF000000C7.apcprd02.prod.outlook.com (2603:1096:404:2e:cafe::8a) by TY2PR06CA0047.outlook.office365.com (2603:1096:404:2e::35) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.20.9031.20 via Frontend Transport; Tue, 19 Aug 2025 11:55:12 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000C7.mail.protection.outlook.com (10.167.240.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9052.8 via Frontend Transport; Tue, 19 Aug 2025 11:55:10 +0000 Received: from hans.. (unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id EDA6D4160508; Tue, 19 Aug 2025 19:55:09 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 12/15] PCI: sky1: Add PCIe host support for CIX Sky1 Date: Tue, 19 Aug 2025 19:52:36 +0800 Message-ID: <20250819115239.4170604-13-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000C7:EE_|TYZPR06MB6513:EE_ X-MS-Office365-Filtering-Correlation-Id: 881a2e06-4c59-44c9-5b7b-08dddf174043 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?crleQZmEcbz0KqDRhcnqrZBAWg38sdTgZNdvq3Neckr6xR7tN2i6iUZ9teld?= =?us-ascii?Q?zhkVczwxRWsF8J3r/S1f+0hvAb8hsudGOwKvJHu2H0lXqSCAbNyIosAvXno7?= =?us-ascii?Q?+Iapz9/IA8xJIn19w3cb5Tzgl7DMkVIe8wldjtMzEbvAKK6kGvtAMLlz/yiJ?= =?us-ascii?Q?WvdsuAZztfZN4zKP91TFscnk3RoqpIWwsmwaYkP3vQeoNG/xYKiEs9aBKows?= =?us-ascii?Q?lLXApYaRhUu6qN5k94bejolDKB+IakBcSj/1gIAissFCXvStNFOAbaF6XApu?= =?us-ascii?Q?cjbRqxm9ZfvwhA1j7sO/jiXd47q+RlWTSM9+RYakKpaJO8wdRLmBYe9O383A?= =?us-ascii?Q?G9rPf8kKpaipkm5DJL2o3Hg1KvAkXRGWkCeg6AbkLjbuq43BHLGRToo3/JdO?= =?us-ascii?Q?1iv0BUKSk8cIGaW/PxM0cOzcnNAj5rvJgBQ0HlC6+D1G6OnV355bB+icV4e+?= =?us-ascii?Q?HDbU5IXVeYycDfonn9US0ygD9htV0oCghv+RsiMzpaCON+FD1stpDJalmbrb?= =?us-ascii?Q?QnLtW3JagymuADX6X5oNtccqLhdin5x8KAr1K2DZ8TEa4gnvjQRDmGl0TWqs?= =?us-ascii?Q?iJTZFQqubsN+756xg7SJQW+xHhir87/oxang2/GqF4L8YxIjUrTR9E0WpCOh?= =?us-ascii?Q?yZiWZvw4uIjrVpv/+MjDeIs7/bcuJjJY0I0LmTDgqg5lmfhLfes+Mrq8LjE8?= =?us-ascii?Q?19mzJV0QIj59p2s6f9rzlKmqeKKsJHfQkE4JOw3HVNcrgbVZAJ/KKXU5lNdJ?= =?us-ascii?Q?VyCU6jNkxxJvhsazsKh0JRMkYthGIpn/ugB2/2VHp3Yn4wm/y8+V5EGZM8aq?= =?us-ascii?Q?g371JmSYVE7TjbehkO9G0o3X3yJGC39hR3ayoPlb7wuxxKEkSnXBbgK0vWDx?= =?us-ascii?Q?volvgBVfKzZDcWe5VoEiwbI0lgBSjZj3u/VlHirj4PEhS1pFUc9a3Yv5XBpS?= =?us-ascii?Q?neZE/W0HC41lEzXD3+PFVoI9JsnCVgWFKvrTjbOl1bIxnDo7WcokRtISBBH7?= =?us-ascii?Q?vrq4cxUKlxpMQGrTdpEfbx9SvUAtJJOgea3On9SWS65HxJ19ulQ9fSVoYdUa?= =?us-ascii?Q?vuZNAeVl5+KPL9EESYR6gkGiosC7qMXyTD6btPu1FqB0V2jgZZ0A9DNSSRGX?= =?us-ascii?Q?yj4EfrC00Nzoc/CmNBd4F7wTSVm4Jx7OYBxtPuPFZgHpl3Yx4n0mp7z9Z69d?= =?us-ascii?Q?DWGLjjpdmKM9Xo1Ff879IJIG6ek6BJPDqYbxSzXzAAYKa2BRE7dNA/q0Hg3M?= =?us-ascii?Q?BeF9nz+HBhlAS4qLTKtoU8hRjCDlG467xiluxTFyKS+2nvGiCvuZQwfZqY69?= =?us-ascii?Q?F+rGnkVJcLzcQUEFOIEYN0dmg5VY6Q+Wib74ShanH0D3nsW0G3sngVP9i1y8?= =?us-ascii?Q?Fe5Q6bR2AV9inii7WMtNrc+jqQcAj34XIT5B6GtRm+ToIF7eafwUlgE4s4LG?= =?us-ascii?Q?W7IdIoY+el+j3tUDXeJDBShWJcK6x+njDiQ9jU2wB2FVGWQRr5Gk6y5wFupU?= =?us-ascii?Q?z3/3jZVlez34vnF3gYnFf688c323wjBZXFSG?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:10.9583 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 881a2e06-4c59-44c9-5b7b-08dddf174043 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C7.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB6513 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add driver for the CIX Sky1 SoC PCIe Gen4 16 GT/s controller based on the Cadence PCIe core. Supports MSI/MSI-x via GICv3, Single Virtual Channel, Single Function. Signed-off-by: Hans Zhang --- Changes for v8: - Optimization of CIX SKY1 Root Port driver. (Bjorn and Krzysztof) - Use devm_platform_ioremap_resource_byname. --- drivers/pci/controller/cadence/Kconfig | 15 ++ drivers/pci/controller/cadence/Makefile | 1 + drivers/pci/controller/cadence/pci-sky1.c | 232 ++++++++++++++++++++++ 3 files changed, 248 insertions(+) create mode 100644 drivers/pci/controller/cadence/pci-sky1.c diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controlle= r/cadence/Kconfig index 117677a23d68..26a248cdc78a 100644 --- a/drivers/pci/controller/cadence/Kconfig +++ b/drivers/pci/controller/cadence/Kconfig @@ -42,6 +42,21 @@ config PCIE_CADENCE_PLAT_EP endpoint mode. This PCIe controller may be embedded into many different vendors SoCs. =20 +config PCI_SKY1_HOST + tristate "CIX SKY1 PCIe controller (host mode)" + depends on OF + select PCIE_CADENCE_HOST + select PCI_ECAM + help + Say Y here if you want to support the CIX SKY1 PCIe platform + controller in host mode. CIX SKY1 PCIe controller uses Cadence + HPA (High Performance Architecture IP [Second generation of + Cadence PCIe IP]) + + This driver requires Cadence PCIe core infrastructure + (PCIE_CADENCE_HOST) and hardware platform adaptation layer + to function. + config PCI_J721E tristate select PCIE_CADENCE_HOST if PCI_J721E_HOST !=3D n diff --git a/drivers/pci/controller/cadence/Makefile b/drivers/pci/controll= er/cadence/Makefile index de4ddae7aca4..40d7c6e98b4d 100644 --- a/drivers/pci/controller/cadence/Makefile +++ b/drivers/pci/controller/cadence/Makefile @@ -8,3 +8,4 @@ obj-$(CONFIG_PCIE_CADENCE_HOST) +=3D pcie-cadence-host-mod.o obj-$(CONFIG_PCIE_CADENCE_EP) +=3D pcie-cadence-ep-mod.o obj-$(CONFIG_PCIE_CADENCE_PLAT) +=3D pcie-cadence-plat.o obj-$(CONFIG_PCI_J721E) +=3D pci-j721e.o +obj-$(CONFIG_PCI_SKY1_HOST) +=3D pci-sky1.o diff --git a/drivers/pci/controller/cadence/pci-sky1.c b/drivers/pci/contro= ller/cadence/pci-sky1.c new file mode 100644 index 000000000000..7dd3546275c5 --- /dev/null +++ b/drivers/pci/controller/cadence/pci-sky1.c @@ -0,0 +1,232 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe controller driver for CIX's sky1 SoCs + * + * Author: Hans Zhang + */ + +#include +#include +#include +#include +#include +#include +#include + +#include "pcie-cadence.h" +#include "pcie-cadence-host-common.h" + +#define STRAP_REG(n) ((n) * 0x04) +#define STATUS_REG(n) ((n) * 0x04) +#define LINK_TRAINING_ENABLE BIT(0) +#define LINK_COMPLETE BIT(0) + +#define SKY1_IP_REG_BANK 0x1000 +#define SKY1_IP_CFG_CTRL_REG_BANK 0x4c00 +#define SKY1_IP_AXI_MASTER_COMMON 0xf000 +#define SKY1_AXI_SLAVE 0x9000 +#define SKY1_AXI_MASTER 0xb000 +#define SKY1_AXI_HLS_REGISTERS 0xc000 +#define SKY1_AXI_RAS_REGISTERS 0xe000 +#define SKY1_DTI_REGISTERS 0xd000 + +#define IP_REG_I_DBG_STS_0 0x420 + +struct sky1_pcie { + struct cdns_pcie *cdns_pcie; + struct cdns_pcie_rc *cdns_pcie_rc; + + struct resource *cfg_res; + struct resource *msg_res; + struct pci_config_window *cfg; + void __iomem *strap_base; + void __iomem *status_base; + void __iomem *reg_base; + void __iomem *cfg_base; + void __iomem *msg_base; +}; + +static int sky1_pcie_resource_get(struct platform_device *pdev, + struct sky1_pcie *pcie) +{ + struct device *dev =3D &pdev->dev; + struct resource *res; + void __iomem *base; + + base =3D devm_platform_ioremap_resource_byname(pdev, "reg"); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "unable to find reg registers\n"); + pcie->reg_base =3D base; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + if (!res) + return dev_err_probe(dev, ENXIO, "unable to get cfg resource\n"); + pcie->cfg_res =3D res; + + base =3D devm_platform_ioremap_resource_byname(pdev, "rcsu_strap"); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "unable to find rcsu strap registers\n"); + pcie->strap_base =3D base; + + base =3D devm_platform_ioremap_resource_byname(pdev, "rcsu_status"); + if (IS_ERR(base)) + return dev_err_probe(dev, PTR_ERR(base), + "unable to find rcsu status registers\n"); + pcie->status_base =3D base; + + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "msg"); + if (!res) + return dev_err_probe(dev, ENXIO, "unable to get msg resource\n"); + pcie->msg_res =3D res; + pcie->msg_base =3D devm_ioremap_resource(dev, res); + if (IS_ERR(pcie->msg_base)) { + return dev_err_probe(dev, PTR_ERR(pcie->msg_base), + "unable to ioremap msg resource\n"); + } + + return 0; +} + +static int sky1_pcie_start_link(struct cdns_pcie *cdns_pcie) +{ + struct sky1_pcie *pcie =3D dev_get_drvdata(cdns_pcie->dev); + u32 val; + + val =3D readl(pcie->strap_base + STRAP_REG(1)); + val |=3D LINK_TRAINING_ENABLE; + writel(val, pcie->strap_base + STRAP_REG(1)); + + return 0; +} + +static void sky1_pcie_stop_link(struct cdns_pcie *cdns_pcie) +{ + struct sky1_pcie *pcie =3D dev_get_drvdata(cdns_pcie->dev); + u32 val; + + val =3D readl(pcie->strap_base + STRAP_REG(1)); + val &=3D ~LINK_TRAINING_ENABLE; + writel(val, pcie->strap_base + STRAP_REG(1)); +} + +static bool sky1_pcie_link_up(struct cdns_pcie *cdns_pcie) +{ + u32 val; + + val =3D cdns_pcie_hpa_readl(cdns_pcie, REG_BANK_IP_REG, + IP_REG_I_DBG_STS_0); + return val & LINK_COMPLETE; +} + +static const struct cdns_pcie_ops sky1_pcie_ops =3D { + .start_link =3D sky1_pcie_start_link, + .stop_link =3D sky1_pcie_stop_link, + .link_up =3D sky1_pcie_link_up, +}; + +static int sky1_pcie_probe(struct platform_device *pdev) +{ + struct cdns_plat_pcie_of_data *reg_off; + struct device *dev =3D &pdev->dev; + struct pci_host_bridge *bridge; + struct cdns_pcie *cdns_pcie; + struct resource_entry *bus; + struct cdns_pcie_rc *rc; + struct sky1_pcie *pcie; + int ret; + + pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*rc)); + if (!bridge) + return -ENOMEM; + + ret =3D sky1_pcie_resource_get(pdev, pcie); + if (ret < 0) + return -ENXIO; + + bus =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + pcie->cfg =3D pci_ecam_create(dev, pcie->cfg_res, bus->res, + &pci_generic_ecam_ops); + if (IS_ERR(pcie->cfg)) + return PTR_ERR(pcie->cfg); + + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + rc =3D pci_host_bridge_priv(bridge); + rc->ecam_support_flag =3D 1; + rc->cfg_base =3D pcie->cfg->win; + rc->cfg_res =3D &pcie->cfg->res; + + cdns_pcie =3D &rc->pcie; + cdns_pcie->dev =3D dev; + cdns_pcie->ops =3D &sky1_pcie_ops; + cdns_pcie->reg_base =3D pcie->reg_base; + cdns_pcie->msg_res =3D pcie->msg_res; + cdns_pcie->is_rc =3D 1; + + reg_off =3D devm_kzalloc(dev, sizeof(*reg_off), GFP_KERNEL); + if (!reg_off) + return -ENOMEM; + + reg_off->ip_reg_bank_offset =3D SKY1_IP_REG_BANK; + reg_off->ip_cfg_ctrl_reg_offset =3D SKY1_IP_CFG_CTRL_REG_BANK; + reg_off->axi_mstr_common_offset =3D SKY1_IP_AXI_MASTER_COMMON; + reg_off->axi_slave_offset =3D SKY1_AXI_SLAVE; + reg_off->axi_master_offset =3D SKY1_AXI_MASTER; + reg_off->axi_hls_offset =3D SKY1_AXI_HLS_REGISTERS; + reg_off->axi_ras_offset =3D SKY1_AXI_RAS_REGISTERS; + reg_off->axi_dti_offset =3D SKY1_DTI_REGISTERS; + cdns_pcie->cdns_pcie_reg_offsets =3D reg_off; + + pcie->cdns_pcie =3D cdns_pcie; + pcie->cdns_pcie_rc =3D rc; + pcie->cfg_base =3D rc->cfg_base; + bridge->sysdata =3D pcie->cfg; + + rc->vendor_id =3D PCI_VENDOR_ID_CIX; + rc->device_id =3D PCI_DEVICE_ID_CIX_SKY1; + rc->no_inbound_flag =3D 1; + + dev_set_drvdata(dev, pcie); + + ret =3D cdns_pcie_hpa_host_setup(rc); + if (ret < 0) { + pci_ecam_free(pcie->cfg); + return ret; + } + + return 0; +} + +static const struct of_device_id of_sky1_pcie_match[] =3D { + { .compatible =3D "cix,sky1-pcie-host", }, + {}, +}; + +static void sky1_pcie_remove(struct platform_device *pdev) +{ + struct sky1_pcie *pcie =3D platform_get_drvdata(pdev); + + pci_ecam_free(pcie->cfg); +} + +static struct platform_driver sky1_pcie_driver =3D { + .probe =3D sky1_pcie_probe, + .remove =3D sky1_pcie_remove, + .driver =3D { + .name =3D "sky1-pcie", + .of_match_table =3D of_sky1_pcie_match, + }, +}; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:12.2035 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 63851c91-907a-4a89-c16d-08dddf174100 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000C9.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB6207 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add myself as maintainer of Sky1 PCIe host driver Signed-off-by: Hans Zhang --- MAINTAINERS | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index daf520a13bdf..95c6acbbdda5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19251,6 +19251,13 @@ S: Orphan F: Documentation/devicetree/bindings/pci/cdns,* F: drivers/pci/controller/cadence/*cadence* =20 +PCI DRIVER FOR CIX Sky1 +M: Hans Zhang +L: linux-pci@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/pci/cix,sky1-pcie-*.yaml +F: drivers/pci/controller/cadence/*sky1* + PCI DRIVER FOR FREESCALE LAYERSCAPE M: Minghuan Lian M: Mingkai Hu --=20 2.49.0 From nobody Sat Oct 4 06:35:23 2025 Received: from OS8PR02CU002.outbound.protection.outlook.com (mail-japanwestazon11022073.outbound.protection.outlook.com [40.107.75.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74A5E32C32F; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 1BC2C416050B; Tue, 19 Aug 2025 19:55:10 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 14/15] arm64: dts: cix: Add PCIe Root Complex on sky1 Date: Tue, 19 Aug 2025 19:52:38 +0800 Message-ID: <20250819115239.4170604-15-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CB:EE_|PUZPR06MB5827:EE_ X-MS-Office365-Filtering-Correlation-Id: 62a0fa84-7d5f-49f4-2490-08dddf174073 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|376014|7416014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?MkZvi0q9R5IHtS3qBsl4dA2I2JXjqFTg3oerBmn98ZqHs+wAsG90We2THGGY?= =?us-ascii?Q?hX7LY/P8EwpCDVE8WAsbraAY1YsQKVVECuHaKLiGez1JYegJO63AelC7/gxa?= =?us-ascii?Q?vQKMpKyabYT3d7/ZxvxQOoich2VQWkrfCoaJVt2oS76xZZcgZLipZdXqiSRk?= =?us-ascii?Q?wFjmf1SXCESWb5ixr79baaZnkLecymR0rrYwi2DFvyy33EBIK37newEfPyMq?= =?us-ascii?Q?ralRUJKJiKvoYVMpIvHTSjWvypbhGoki2iqlURaSyVhE/7vjaRagtLOKo/vH?= =?us-ascii?Q?eYQm3iIYkfVv4RNakJeATYarXihwJPM+IST0NgbjaQyObQxeQxfIkMoaqn2m?= =?us-ascii?Q?9nt51txOMHVmDjJ2XHRPp1TGzMwQvWYYDR0C3hw/wxYgOxC6b2FErme8tdXo?= =?us-ascii?Q?di4FQNQ0zA197fHb3dcKgsMMg67LxhNM4COugKMKbg8bgKHlVeJ4Me4BsGbT?= =?us-ascii?Q?fqYWz+YXCh5+VFAblPoHuXI54EQQ8OayZNJu7/SiFr6gcynf2fkpq67znzPI?= =?us-ascii?Q?TmJNzUJeGBHdwn89uK4ZVJ+QNbGRbC0di8DyQhlqxhbRZfB57J1eGJW2WQBN?= =?us-ascii?Q?qzHwhuasCqdSb8vXAPM82wSndhVGzHocorrM56ldC4rhI6ZkyVTCZFOgGTHh?= =?us-ascii?Q?NnkeT4GsDU33xTFrG+S94xj34yKFre2jxxdA9ZpG+7hQQxP8pBwsj+U8l9of?= =?us-ascii?Q?lYK1D1SmuGVwHQyaN5ofiYfNWqj1RDeLojPGXLIHqF+FeZEM2WwG61xS+Gfz?= =?us-ascii?Q?CbR+fd140JoyOCYm0X2OLPSU5enOPxgow3v3iOn6QVNLHqlO/jz4EhVAmNm1?= =?us-ascii?Q?/EzoQAUfi9pm1qAjCLp8rgg5OY9/gPv3mipbArv3YY99j6LSV9z/+d/n7vyF?= =?us-ascii?Q?zyMbon0YLzCMZRYMMeYhAGPqxMEipZa6WnJkQsVavnDuxWMYiNC6GI893Q9w?= =?us-ascii?Q?dSd+GBAcgo3cnj0v4nty3V7bH0BFGdzNgmZqcWFTdbRdde+4vRbGC3H/KGtG?= =?us-ascii?Q?J07ryb5N65gyzHuoO7VJoMtEvvYrTUdeKkBjvjoytQr+58YyOGVdnmuD3IDv?= =?us-ascii?Q?PWhN+tqDzCfnuIF7msQQIxcYl1rDwklY4pU5iSV2yYaV8owSibInfi+kilf0?= =?us-ascii?Q?KN3GKdidT7aTtf5BD/RLUz7JMUCx/kwTQpHFzoUBVThCoxK20+JGZR9wJht8?= =?us-ascii?Q?XkZ/nfdjl2wFhobpKD81mJVCkLh/L7tTeeiqsm1bZkVsMcH/3lzzqwoJp63/?= =?us-ascii?Q?FlNchP4RfX2oT4ia1ZMnV1btLW1SwOro1BgtjiEUJ1bnG+mqIaLqykIDfC9b?= =?us-ascii?Q?pJwVlGQ17GwJYlssIrKSth/9WtLJbMNYlUTKRDHz6Z9sYQRA4qcgE9x3oKuy?= =?us-ascii?Q?VIUkPRVCuHzeepEdp+SEucaU8mVCuJkeOmmI2wGIA9oNjbYauz2eSb7m53J4?= =?us-ascii?Q?uaEummWpwnEXl/sRIhvxebEd3fQlJAHe+n/IMbEiWWzs5Fcok8TFW8zTKdXW?= =?us-ascii?Q?zIpjxvd4CYT9FB78ocmgCQcn5SRTBF7d3isf?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(376014)(7416014)(1800799024)(36860700013);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:11.2941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62a0fa84-7d5f-49f4-2490-08dddf174073 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CB.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PUZPR06MB5827 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add pcie_x*_rc node to support Sky1 PCIe driver based on the Cadence PCIe core. Supports Gen1/Gen2/Gen3/Gen4, 1/2/4/8 lane, MSI/MSI-x interrupts using the ARM GICv3. Signed-off-by: Hans Zhang --- Changes for v8: - The rcsu register is split into two parts: rcsu_strap and rcsu_status. --- arch/arm64/boot/dts/cix/sky1.dtsi | 126 ++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sk= y1.dtsi index 7dfe7677e649..26c325d8d934 100644 --- a/arch/arm64/boot/dts/cix/sky1.dtsi +++ b/arch/arm64/boot/dts/cix/sky1.dtsi @@ -288,6 +288,132 @@ mbox_ap2sfh: mailbox@80a0000 { cix,mbox-dir =3D "tx"; }; =20 + pcie_x8_rc: pcie@a010000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a010000 0x00 0x10000>, + <0x00 0x2c000000 0x00 0x4000000>, + <0x00 0x0a000300 0x00 0x100>, + <0x00 0x0a000400 0x00 0x100>, + <0x00 0x60000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges =3D <0x01000000 0x0 0x60100000 0x0 0x60100000 0x0 0x00100000>, + <0x02000000 0x0 0x60200000 0x0 0x60200000 0x0 0x1fe00000>, + <0x43000000 0x18 0x00000000 0x18 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0xc0 0xff>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0xc000 &gic_its 0xc000 0x4000>; + status =3D "disabled"; + }; + + pcie_x4_rc: pcie@a070000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a070000 0x00 0x10000>, + <0x00 0x29000000 0x00 0x3000000>, + <0x00 0x0a060300 0x00 0x40>, + <0x00 0x0a060400 0x00 0x40>, + <0x00 0x50000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges =3D <0x01000000 0x00 0x50100000 0x00 0x50100000 0x00 0x00100000>, + <0x02000000 0x00 0x50200000 0x00 0x50200000 0x00 0x0fe00000>, + <0x43000000 0x14 0x00000000 0x14 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x90 0xbf>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x9000 &gic_its 0x9000 0x3000>; + status =3D "disabled"; + }; + + pcie_x2_rc: pcie@a0c0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0c0000 0x00 0x10000>, + <0x00 0x26000000 0x00 0x3000000>, + <0x00 0x0a0600340 0x00 0x20>, + <0x00 0x0a0600440 0x00 0x20>, + <0x00 0x40000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges =3D <0x01000000 0x0 0x40100000 0x0 0x40100000 0x0 0x00100000>, + <0x02000000 0x0 0x40200000 0x0 0x40200000 0x0 0x0fe00000>, + <0x43000000 0x10 0x00000000 0x10 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x60 0x8f>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x6000 &gic_its 0x6000 0x3000>; + status =3D "disabled"; + }; + + pcie_x1_0_rc: pcie@a0d0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0d0000 0x00 0x10000>, + <0x00 0x20000000 0x00 0x3000000>, + <0x00 0x0a060360 0x00 0x20>, + <0x00 0x0a060460 0x00 0x20>, + <0x00 0x30000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges =3D <0x01000000 0x0 0x30100000 0x0 0x30100000 0x0 0x00100000>, + <0x02000000 0x0 0x30200000 0x0 0x30200000 0x0 0x07e00000>, + <0x43000000 0x08 0x00000000 0x08 0x00000000 0x04 0x00000000>; + #address-cells =3D <3>; + #size-cells =3D <2>; + bus-range =3D <0x00 0x2f>; + device_type =3D "pci"; + #interrupt-cells =3D <1>; + interrupt-map-mask =3D <0 0 0 0x7>; + interrupt-map =3D <0 0 0 1 &gic 0 0 GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 2 &gic 0 0 GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 3 &gic 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH 0>, + <0 0 0 4 &gic 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH 0>; + msi-map =3D <0x0000 &gic_its 0x0000 0x3000>; + status =3D "disabled"; + }; + + pcie_x1_1_rc: pcie@a0e0000 { + compatible =3D "cix,sky1-pcie-host"; + reg =3D <0x00 0x0a0e0000 0x00 0x10000>, + <0x00 0x23000000 0x00 0x3000000>, + <0x00 0x0a060380 0x00 0x20>, + <0x00 0x0a060480 0x00 0x20>, + <0x00 0x38000000 0x00 0x00100000>; + reg-names =3D "reg", "cfg", "rcsu_strap", "rcsu_status", "msg"; + ranges =3D <0x01000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000>, + <0x02000000 0x0 0x38200000 0x0 0x38200000 0x0 0x07e00000>, + <0x43000000 0x0C 0x00000000 0x0C 0x00000000 0x04 0x00000000>; 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(unknown [172.16.64.208]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 2C4254160511; Tue, 19 Aug 2025 19:55:10 +0800 (CST) From: hans.zhang@cixtech.com To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, mani@kernel.org, robh@kernel.org, kwilczynski@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: mpillai@cadence.com, fugang.duan@cixtech.com, guoyin.chen@cixtech.com, peter.chen@cixtech.com, cix-kernel-upstream@cixtech.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Hans Zhang Subject: [PATCH v8 15/15] arm64: dts: cix: Enable PCIe on the Orion O6 board Date: Tue, 19 Aug 2025 19:52:39 +0800 Message-ID: <20250819115239.4170604-16-hans.zhang@cixtech.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250819115239.4170604-1-hans.zhang@cixtech.com> References: <20250819115239.4170604-1-hans.zhang@cixtech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CD:EE_|SE1PPF215029121:EE_ X-MS-Office365-Filtering-Correlation-Id: aa4c37c8-9a3a-45d0-c76d-08dddf17406f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700013|82310400026|7416014|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?H5trd3/VlEKQh9yHqJV8jWxU7svDLpCxSAmBlG1WjHk2F6XWlKSUUettcdga?= =?us-ascii?Q?E/gLCqg3/7dSKMBtWs5vhAdOYfZWejC7HPpLZJiUoDDuW8+p40C/UmadLio/?= =?us-ascii?Q?AlKGGlQ+3dQc/DcMrTkbxEMw6mkH0+Su7LaakmFvexa2sHjoqdp8YMLHpuPI?= =?us-ascii?Q?3QCG8xDFbf/CXvfcxWBuZfCAYPksHbdYrp1+ph9Lk6MmfgT0L0yCz5bZeuWw?= =?us-ascii?Q?xoNRaG65H4FL4dt9XjB0cpgRd2G/ufLWGcAOu414rB1UGKK0z7VBlLn+hTZP?= =?us-ascii?Q?piSJJD7Ku53Ro/J4lalZf62RexE11F6kRzss+BUhPGOpRZ2KweML+hLBxWpZ?= =?us-ascii?Q?C+iUMQn25YtZyTouTLxk3ac56HS0BMxz6imPA6hxCMpzVDxGX2KQUQfxSj6B?= =?us-ascii?Q?DdImds571K7tBkagnXni1z16KAiexKz40fIv6m/S97X2tKoHNHiJMIrYMSC9?= =?us-ascii?Q?HFgGlJnE9wj/i6j9cTzz41+ZxWKfs44IJ1+59U1Pz4wfVBE46ovELzwJDqmP?= =?us-ascii?Q?Ry5MGm0bl7/FgyHIWa6euJitWafHOGw54VQtMy3/DrNZCPi5cNX6dz5wBBuQ?= =?us-ascii?Q?PKphF0Q7c/28hDY+Hphnmrh9XN/iA0UO69hFh2PzRGs+1kpxziErfh4xQUQa?= =?us-ascii?Q?UPgTdcqL/MJyTe4FRHNhfpS8c07oPW8chjtxx1y/Wg14d2IjA9NngNxV3RUM?= =?us-ascii?Q?HtOZMJwwNmzuKeBLvLL+G0ZpioAShnh3o847rLiQhLKoAp9n0jdJ8BlLOUVC?= =?us-ascii?Q?WXnuwK4zzblBWPj01KWBa8HAbuGYMetCV9Ollc59TXEg3a3LsuHCeD3PxXPR?= =?us-ascii?Q?Leb56UprcIm8SdPA/4z4CcFaR6SkoPVcGvviw81q5iJ4/rzxOg1jLuAnXMhc?= =?us-ascii?Q?QxGxrCXV322bQaylr42nmpc6+RKLObGIPqCUnJnisYQL0ZK0p9NpFyn/+jB3?= =?us-ascii?Q?6nUxHqjiuLZy+JuFKC9XWeCVcWR+0aUeb91NN691llltjEIDRSKPBLZDW9zT?= =?us-ascii?Q?Udid18m2xMI8epsP8OrmwXS96crD/qwCrgd9KGdUp2iCL3LEHkShgutqdJAy?= =?us-ascii?Q?aZ4mxg5B4rbFl8VhScJsVT3gbFVuBwhboVi+Vs0RkgtzYthf2txluoHhrGbl?= =?us-ascii?Q?nnhgAwVurhn2hhOlCZwZBNmKdL9DVx15NrHBphB5G1wBcIp9kScDTl1E/wkw?= =?us-ascii?Q?bP8eRg774L4fYqLFhnEi0C7PLlHJ0J/+gJ8mMOnBWR1DhyPRFIWY6qMk7/Fk?= =?us-ascii?Q?d4GHf3JFr6CsYAra8+MaSgnbZ+BxUOkGQ4lrLKDb91AFEPtRZB5O/kvnfkNv?= =?us-ascii?Q?hjyDL3k5ydkGQGvsXCCL72w9AqmApTfLEus3zRD47xwL2XIyuv2QWiS9iRME?= =?us-ascii?Q?iHEXhVIfAabDCacA4j5f4bsX4v/J9gqjegm2/6rec6VX7oFMUB+rbhTJGmLq?= =?us-ascii?Q?tN2UtBLy9SpaO/ETKTiVij4T6czwSCwbex0sb3eQWnq6ht8E32oF2w=3D=3D?= X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700013)(82310400026)(7416014)(376014);DIR:OUT;SFP:1102; X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Aug 2025 11:55:11.2703 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aa4c37c8-9a3a-45d0-c76d-08dddf17406f X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CD.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SE1PPF215029121 Content-Type: text/plain; charset="utf-8" From: Hans Zhang Add PCIe RC support on Orion O6 board. Signed-off-by: Hans Zhang --- Dear Krzysztof, Due to the fact that the GPIO, PINCTRL and other modules of our platform are not yet ready for upstream. Attributes that PCIe depends on, such as reset-= gpios and pinctrl*, have not been added for the time being. It will be added grad= ually in the future. The following are Arnd's previous comments. We can go to upsteam separately. https://lore.kernel.org/all/422deb4d-db29-48c1-b0c9-7915951df500@app.fastma= il.com/ --- arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dt= s/cix/sky1-orion-o6.dts index d74964d53c3b..be3ec4f5d11e 100644 --- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts +++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts @@ -34,6 +34,26 @@ linux,cma { =20 }; =20 +&pcie_x8_rc { + status =3D "okay"; +}; + +&pcie_x4_rc { + status =3D "okay"; +}; + +&pcie_x2_rc { + status =3D "okay"; +}; + +&pcie_x1_0_rc { + status =3D "okay"; +}; + +&pcie_x1_1_rc { + status =3D "okay"; +}; + &uart2 { status =3D "okay"; }; --=20 2.49.0