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[31.53.6.191]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45a1c61a66esm203895015e9.0.2025.08.19.01.40.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 01:40:24 -0700 (PDT) From: Biju X-Google-Original-From: Biju To: Geert Uytterhoeven , Linus Walleij Cc: Biju Das , linux-renesas-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar Mahadev Lad , Biju Das Subject: [PATCH] pinctrl: renesas: rzg2l: Add suspend/resume support for Schmitt control registers Date: Tue, 19 Aug 2025 09:40:20 +0100 Message-ID: <20250819084022.20512-1-biju.das.jz@bp.renesas.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Biju Das The Renesas RZ/G3E supports a power-saving mode where power to most of the SoC components is lost, including the PIN controller. Save and restore the Schmitt control register contents to ensure the functionality is preserved after a suspend/resume cycle. Signed-off-by: Biju Das Reviewed-by: Claudiu Beznea Reviewed-by: Geert Uytterhoeven Tested-by: Claudiu Beznea # on RZ/G3S --- This patch is on top of [1] [1] https://lore.kernel.org/all/20250817143024.165471-1-biju.das.jz@bp.rene= sas.com/ --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/rene= sas/pinctrl-rzg2l.c index 8422a5429ca3..8ba6d82f335f 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -321,6 +321,7 @@ struct rzg2l_pinctrl_pin_settings { * @iolh: IOLH registers cache * @pupd: PUPD registers cache * @ien: IEN registers cache + * @smt: SMT registers cache * @sd_ch: SD_CH registers cache * @eth_poc: ET_POC registers cache * @oen: Output Enable register cache @@ -334,6 +335,7 @@ struct rzg2l_pinctrl_reg_cache { u32 *iolh[2]; u32 *ien[2]; u32 *pupd[2]; + u32 *smt; u8 sd_ch[2]; u8 eth_poc[2]; u8 oen; @@ -2707,6 +2709,10 @@ static int rzg2l_pinctrl_reg_cache_alloc(struct rzg2= l_pinctrl *pctrl) if (!cache->pfc) return -ENOMEM; =20 + cache->smt =3D devm_kcalloc(pctrl->dev, nports, sizeof(*cache->smt), GFP_= KERNEL); + if (!cache->smt) + return -ENOMEM; + for (u8 i =3D 0; i < 2; i++) { u32 n_dedicated_pins =3D pctrl->data->n_dedicated_pins; =20 @@ -2968,7 +2974,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_= pinctrl *pctrl, bool suspen struct rzg2l_pinctrl_reg_cache *cache =3D pctrl->cache; =20 for (u32 port =3D 0; port < nports; port++) { - bool has_iolh, has_ien, has_pupd; + bool has_iolh, has_ien, has_pupd, has_smt; u32 off, caps; u8 pincnt; u64 cfg; @@ -2981,6 +2987,7 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_= pinctrl *pctrl, bool suspen has_iolh =3D !!(caps & (PIN_CFG_IOLH_A | PIN_CFG_IOLH_B | PIN_CFG_IOLH_C= )); has_ien =3D !!(caps & PIN_CFG_IEN); has_pupd =3D !!(caps & PIN_CFG_PUPD); + has_smt =3D !!(caps & PIN_CFG_SMT); =20 if (suspend) RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + PFC(off), cache->pfc[po= rt]); @@ -3019,6 +3026,9 @@ static void rzg2l_pinctrl_pm_setup_regs(struct rzg2l_= pinctrl *pctrl, bool suspen cache->ien[1][port]); } } + + if (has_smt) + RZG2L_PCTRL_REG_ACCESS32(suspend, pctrl->base + SMT(off), cache->smt[po= rt]); } } =20 --=20 2.43.0