From nobody Sat Oct 4 09:39:45 2025 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFEF729ACFC; Tue, 19 Aug 2025 02:00:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755568815; cv=none; b=Z5BRC2KnmIUlU0hgoSMeh3EKp70QJdQxjOASW2zNaTvkkgrOTwJvUiL1V91Pz/A/Mk8SwO6I12iEQxMTPKSaio24ZDF6mcSq6hoZhuUUoF7Ivq6csPIe62jMSEc/jTSMa3Ufa3FYrvpjHjbFsB10wy6WgLqpc985e1Q/2Q1ahNs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755568815; c=relaxed/simple; bh=qSFieO8Cel9KlPL3NAoUBzU1UL6uW8E4kaBvUL8HCj8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qKles9LVkZK8UxrpmmyGXGDs7y0yBhHVKMVvsPP/9FhJItfcEBQDBcpwrpGt03NdK+IUCX3VpJLpTSMTAEXFYlirJT2E4J+5Y9KlT0y49U6Hb0Hyr0tNyx9D2xnuyS1POUGbUWPvTSgAJRSIkkXv9aTACA7b1XtM70Teb47jRVw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=pUxVzD41; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="pUxVzD41" X-UUID: 3c736fae7ca011f08729452bf625a8b4-20250819 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=zTwFQbiahKuVur4FiMdEux7IBBiZSXrfDzUUPEN8Sro=; b=pUxVzD41SrRgfeAC77jFbuH2uDDsyjtVxG+pJ5WTxAaufpUxIfarXnd2IsVz4t6Jb7sin/YvOAtKqN9KBYOPPImPFJBZd2njl1/73Y3BACY3ZzZWEtk6xgq5PWLUx+D0wC44ct7gCme+ATud7Zn7jcbcqjmXHqz5xNiozYuKCw8=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.3,REQID:e9d0081d-b384-461b-a729-8b287e9d1aa2,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:f1326cf,CLOUDID:703311f4-66cd-4ff9-9728-6a6f64661009,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:-5,Content:0|15|50,EDM: -3,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0, AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 3c736fae7ca011f08729452bf625a8b4-20250819 Received: from mtkmbs14n1.mediatek.inc [(172.21.101.75)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 63197098; Tue, 19 Aug 2025 10:00:09 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.39; Tue, 19 Aug 2025 10:00:00 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.39 via Frontend Transport; Tue, 19 Aug 2025 10:00:00 +0800 From: Xiandong Wang To: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Houlong Wei CC: , , , , , , , , Xiandong Wang Subject: [PATCH v2 4/4] mailbox: mtk-cmdq: modify clk api for suspend/resume Date: Tue, 19 Aug 2025 09:59:41 +0800 Message-ID: <20250819015948.15450-5-xiandong.wang@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250819015948.15450-1-xiandong.wang@mediatek.com> References: <20250819015948.15450-1-xiandong.wang@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Since it is necessary to use clk_bulk_prepare_enable and clk_bulk_disable_unprepare instead of clk_bulk enable and clk_bulk_disable because, on 8189, the gce clk is mounted on the mminfra clk. When disabling and enabling, the parent clk must be enabled and disabled first to correctly switch the clk for gce usage. Modify the clk api for suspend and resume, modify the api for suspend and resume to disable/enable clk, so it can disable/enable module clk and parent clk successfully. Signed-off-by: Xiandong Wang --- drivers/mailbox/mtk-cmdq-mailbox.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-= mailbox.c index 543cd86b5bb0..590f0f6e51b0 100644 --- a/drivers/mailbox/mtk-cmdq-mailbox.c +++ b/drivers/mailbox/mtk-cmdq-mailbox.c @@ -161,14 +161,14 @@ static void cmdq_init(struct cmdq *cmdq) { int i; =20 - WARN_ON(clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks)); + WARN_ON(clk_bulk_prepare_enable(cmdq->pdata->gce_num, cmdq->clocks)); =20 cmdq_gctl_value_toggle(cmdq, true); =20 writel(CMDQ_THR_ACTIVE_SLOT_CYCLES, cmdq->base + CMDQ_THR_SLOT_CYCLES); for (i =3D 0; i <=3D CMDQ_MAX_EVENT; i++) writel(i, cmdq->base + CMDQ_SYNC_TOKEN_UPDATE); - clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); + clk_bulk_disable_unprepare(cmdq->pdata->gce_num, cmdq->clocks); } =20 static int cmdq_thread_reset(struct cmdq *cmdq, struct cmdq_thread *thread) @@ -332,7 +332,7 @@ static int cmdq_runtime_resume(struct device *dev) struct cmdq *cmdq =3D dev_get_drvdata(dev); int ret; =20 - ret =3D clk_bulk_enable(cmdq->pdata->gce_num, cmdq->clocks); + ret =3D clk_bulk_prepare_enable(cmdq->pdata->gce_num, cmdq->clocks); if (ret) return ret; =20 @@ -345,7 +345,7 @@ static int cmdq_runtime_suspend(struct device *dev) struct cmdq *cmdq =3D dev_get_drvdata(dev); =20 cmdq_gctl_value_toggle(cmdq, false); - clk_bulk_disable(cmdq->pdata->gce_num, cmdq->clocks); + clk_bulk_disable_unprepare(cmdq->pdata->gce_num, cmdq->clocks); return 0; } =20 @@ -384,12 +384,8 @@ static int cmdq_resume(struct device *dev) =20 static void cmdq_remove(struct platform_device *pdev) { - struct cmdq *cmdq =3D platform_get_drvdata(pdev); - if (!IS_ENABLED(CONFIG_PM)) cmdq_runtime_suspend(&pdev->dev); - - clk_bulk_unprepare(cmdq->pdata->gce_num, cmdq->clocks); } =20 static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data) @@ -708,8 +704,6 @@ static int cmdq_probe(struct platform_device *pdev) =20 platform_set_drvdata(pdev, cmdq); =20 - WARN_ON(clk_bulk_prepare(cmdq->pdata->gce_num, cmdq->clocks)); - cmdq_init(cmdq); =20 err =3D devm_request_irq(dev, cmdq->irq, cmdq_irq_handler, IRQF_SHARED, --=20 2.46.0