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Mon, 18 Aug 2025 18:31:42 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:01 +0800 Subject: [PATCH v15 07/13] drm/msm/dpu: handle pipes as array Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-7-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=18175; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=O2do4/Cgux1zUTNJ5Dlm5VV6D0+Z3W/xU4SgQ92ZmGo=; b=EwTyggZfihmlsIQRZeC5TRW1OpM6jvXeuK6xLjruPnCLLJWN9ig44Lvo+ujYUkLF0Qfami02a rL4YhNdMjGvARd6MCs1GptpHfBzQCwb+axHn21cuGuGYimchZtTdGFt X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= There are 2 pipes in a drm plane at most currently, while 4 pipes are required for quad-pipe case. Generalize the handling to pipe pair and ease handling to another pipe pair later. Store pipes in array with removing dedicated r_pipe. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 39 +++---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 181 +++++++++++++++++---------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +- 3 files changed, 121 insertions(+), 111 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index cd0ec3edfe2fa8132e114bc1544c389141d1c1ec..121bd0d304b308bcd7226784eda= 14d7c7f5a46f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -449,7 +449,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, struct dpu_plane_state *pstate =3D NULL; const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; - u32 lm_idx; + u32 lm_idx, i; bool bg_alpha_enable =3D false; DECLARE_BITMAP(active_fetch, SSPP_MAX); DECLARE_BITMAP(active_pipes, SSPP_MAX); @@ -472,22 +472,17 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_cr= tc *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - set_bit(pstate->pipe.sspp->idx, active_fetch); - set_bit(pstate->pipe.sspp->idx, active_pipes); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe, 0, stage_cfg); - - if (pstate->r_pipe.sspp) { - set_bit(pstate->r_pipe.sspp->idx, active_fetch); - set_bit(pstate->r_pipe.sspp->idx, active_pipes); + + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + set_bit(pstate->pipe[i].sspp->idx, active_fetch); + set_bit(pstate->pipe[i].sspp->idx, active_pipes); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, format, fb ? fb->modifier : 0, - &pstate->r_pipe, 1, stage_cfg); + &pstate->pipe[i], i, stage_cfg); } =20 /* blend config update */ @@ -1667,15 +1662,15 @@ static int _dpu_debugfs_status_show(struct seq_file= *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); - seq_printf(s, "\tsspp[0]:%s\n", - pstate->pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", - pstate->pipe.multirect_mode, pstate->pipe.multirect_index); - if (pstate->r_pipe.sspp) { - seq_printf(s, "\tsspp[1]:%s\n", - pstate->r_pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", - pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); + + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + seq_printf(s, "\tsspp[%d]:%s\n", + i, pstate->pipe[i].sspp->cap->name); + seq_printf(s, "\tmultirect[%d]: mode: %d index: %d\n", + i, pstate->pipe[i].multirect_mode, + pstate->pipe[i].multirect_index); } =20 seq_puts(s, "\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index d20233ccd8df612fb6eee15242669510cf883c26..56a0bb41424f2bd9f90173cb47f= 5ae792bbff498 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -620,6 +620,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdp= u, struct msm_drm_private *priv =3D plane->dev->dev_private; struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); u32 fill_color =3D (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); + int i; =20 DPU_DEBUG_PLANE(pdpu, "\n"); =20 @@ -633,12 +634,13 @@ static void _dpu_plane_color_fill(struct dpu_plane *p= dpu, return; =20 /* update sspp */ - _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_r= ect, - fill_color, fmt); - - if (pstate->r_pipe.sspp) - _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.= dst_rect, + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], + &pstate->pipe_cfg[i].dst_rect, fill_color, fmt); + } } =20 static int dpu_plane_prepare_fb(struct drm_plane *plane, @@ -820,8 +822,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; uint32_t max_linewidth; =20 @@ -846,6 +848,9 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, return -EINVAL; } =20 + /* move the assignment here, to ease handling to another pairs later */ + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; /* state->src is 16.16, src_rect is not */ drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); =20 @@ -961,10 +966,10 @@ static int dpu_plane_atomic_check_sspp(struct drm_pla= ne *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; int ret =3D 0; =20 ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, @@ -1019,15 +1024,15 @@ static int dpu_plane_try_multirect_shared(struct dp= u_plane_state *pstate, const struct msm_format *fmt, uint32_t max_linewidth) { - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe *prev_pipe =3D &prev_adjacent_pstate->pipe; - struct dpu_sw_pipe_cfg *prev_pipe_cfg =3D &prev_adjacent_pstate->pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe *prev_pipe =3D &prev_adjacent_pstate->pipe[0]; + struct dpu_sw_pipe_cfg *prev_pipe_cfg =3D &prev_adjacent_pstate->pipe_cfg= [0]; const struct msm_format *prev_fmt =3D msm_framebuffer_format(prev_adjacen= t_pstate->base.fb); u16 max_tile_height =3D 1; =20 - if (prev_adjacent_pstate->r_pipe.sspp !=3D NULL || + if (prev_adjacent_pstate->pipe[1].sspp !=3D NULL || prev_pipe->multirect_mode !=3D DPU_SSPP_MULTIRECT_NONE) return false; =20 @@ -1087,10 +1092,10 @@ static int dpu_plane_atomic_check(struct drm_plane = *plane, struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; const struct drm_crtc_state *crtc_state =3D NULL; uint32_t max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; =20 @@ -1134,7 +1139,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, drm_atomic_get_old_plane_state(state, plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane_state); struct drm_crtc_state *crtc_state; - int ret; + int ret, i; =20 if (IS_ERR(plane_state)) return PTR_ERR(plane_state); @@ -1152,8 +1157,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - pstate->pipe.sspp =3D NULL; - pstate->r_pipe.sspp =3D NULL; + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 return 0; } @@ -1191,6 +1196,7 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; + int i; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1199,13 +1205,14 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, pstate =3D to_dpu_plane_state(plane_state); prev_adjacent_pstate =3D prev_adjacent_plane_state ? to_dpu_plane_state(prev_adjacent_plane_state) : NULL; - pipe =3D &pstate->pipe; - r_pipe =3D &pstate->r_pipe; - pipe_cfg =3D &pstate->pipe_cfg; - r_pipe_cfg =3D &pstate->r_pipe_cfg; =20 - pipe->sspp =3D NULL; - r_pipe->sspp =3D NULL; + pipe =3D &pstate->pipe[0]; + r_pipe =3D &pstate->pipe[1]; + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; + + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 if (!plane_state->fb) return -EINVAL; @@ -1316,6 +1323,7 @@ void dpu_plane_flush(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; + int i; =20 if (!plane || !plane->state) { DPU_ERROR("invalid plane\n"); @@ -1336,8 +1344,8 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - dpu_plane_flush_csc(pdpu, &pstate->pipe); - dpu_plane_flush_csc(pdpu, &pstate->r_pipe); + for (i =3D 0; i < PIPES_PER_STAGE; i++) + dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 /* flag h/w flush complete */ @@ -1438,15 +1446,12 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; struct drm_crtc *crtc =3D state->crtc; struct drm_framebuffer *fb =3D state->fb; bool is_rt_pipe; const struct msm_format *fmt =3D msm_framebuffer_format(fb); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + int i; =20 pstate->pending =3D true; =20 @@ -1461,12 +1466,12 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, crtc->base.id, DRM_RECT_ARG(&state->dst), &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, - drm_mode_vrefresh(&crtc->mode), - &pstate->layout); - - if (r_pipe->sspp) { - dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, + /* move the assignment here, to ease handling to another pairs later */ + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], + &pstate->pipe_cfg[i], fmt, drm_mode_vrefresh(&crtc->mode), &pstate->layout); } @@ -1474,15 +1479,17 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, if (pstate->needs_qos_remap) pstate->needs_qos_remap =3D false; =20 - pstate->plane_fetch_bw =3D _dpu_plane_calc_bw(pdpu->catalog, fmt, - &crtc->mode, pipe_cfg); - - pstate->plane_clk =3D _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); - - if (r_pipe->sspp) { - pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc= ->mode, r_pipe_cfg); + pstate->plane_fetch_bw =3D 0; + pstate->plane_clk =3D 0; + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, + &crtc->mode, &pstate->pipe_cfg[i]); =20 - pstate->plane_clk =3D max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->= mode, r_pipe_cfg)); + pstate->plane_clk =3D max(pstate->plane_clk, + _dpu_plane_calc_clk(&crtc->mode, + &pstate->pipe_cfg[i])); } } =20 @@ -1490,17 +1497,31 @@ static void _dpu_plane_atomic_disable(struct drm_pl= ane *plane) { struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; + struct dpu_sw_pipe *pipe; + int i; =20 - trace_dpu_plane_disable(DRMID(plane), false, - pstate->pipe.multirect_mode); + for (i =3D 0; i < PIPES_PER_STAGE; i +=3D 1) { + pipe =3D &pstate->pipe[i]; + if (!pipe->sspp) + continue; =20 - if (r_pipe->sspp) { - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + trace_dpu_plane_disable(DRMID(plane), false, + pstate->pipe[i].multirect_mode); =20 - if (r_pipe->sspp->ops.setup_multirect) - r_pipe->sspp->ops.setup_multirect(r_pipe); + if (!pipe->sspp) + continue; + + if (i % PIPES_PER_STAGE =3D=3D 0) + continue; + + /* + * clear multirect for the right pipe so that the SSPP + * can be further reused in the solo mode + */ + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + if (pipe->sspp->ops.setup_multirect) + pipe->sspp->ops.setup_multirect(pipe); } =20 pstate->pending =3D true; @@ -1595,31 +1616,26 @@ static void dpu_plane_atomic_print_state(struct drm= _printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - const struct dpu_sw_pipe *pipe =3D &pstate->pipe; - const struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - const struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - const struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + const struct dpu_sw_pipe *pipe; + const struct dpu_sw_pipe_cfg *pipe_cfg; + int i; =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - if (pipe->sspp) { - drm_printf(p, "\tsspp[0]=3D%s\n", pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[0]=3D%s\n", + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe =3D &pstate->pipe[i]; + if (!pipe->sspp) + continue; + pipe_cfg =3D &pstate->pipe_cfg[i]; + drm_printf(p, "\tsspp[%d]=3D%s\n", i, pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[%d]=3D%s\n", i, dpu_get_multirect_mode(pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[0]=3D%s\n", + drm_printf(p, "\tmultirect_index[%d]=3D%s\n", i, dpu_get_multirect_index(pipe->multirect_index)); - drm_printf(p, "\tsrc[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->s= rc_rect)); - drm_printf(p, "\tdst[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->d= st_rect)); - } - - if (r_pipe->sspp) { - drm_printf(p, "\tsspp[1]=3D%s\n", r_pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[1]=3D%s\n", - dpu_get_multirect_mode(r_pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[1]=3D%s\n", - dpu_get_multirect_index(r_pipe->multirect_index)); - drm_printf(p, "\tsrc[1]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg-= >src_rect)); - drm_printf(p, "\tdst[1]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg-= >dst_rect)); + drm_printf(p, "\tsrc[%d]=3D" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[%d]=3D" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->dst_rect)); } } =20 @@ -1657,14 +1673,17 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane = *plane, bool enable) struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + int i; =20 if (!pdpu->is_rt_pipe) return; =20 pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); - if (pstate->r_pipe.sspp) - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index a3a6e9028333052cbaa92830c68e2315c664c239..007f044499b99ac9c2e4b58e98e= 6add013a986de 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -17,10 +17,8 @@ /** * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object - * @pipe: software pipe description - * @r_pipe: software pipe description of the second pipe - * @pipe_cfg: software pipe configuration - * @r_pipe_cfg: software pipe configuration for the second pipe + * @pipe: software pipe description array + * @pipe_cfg: software pipe configuration array * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -33,10 +31,8 @@ */ struct dpu_plane_state { struct drm_plane_state base; - struct dpu_sw_pipe pipe; - struct dpu_sw_pipe r_pipe; - struct dpu_sw_pipe_cfg pipe_cfg; - struct dpu_sw_pipe_cfg r_pipe_cfg; + struct dpu_sw_pipe pipe[PIPES_PER_STAGE]; + struct dpu_sw_pipe_cfg pipe_cfg[PIPES_PER_STAGE]; enum dpu_stage stage; bool needs_qos_remap; bool pending; --=20 2.34.1