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Mon, 18 Aug 2025 18:31:10 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:30:55 +0800 Subject: [PATCH v15 01/13] drm/msm: Do not validate SSPP when it is not ready Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-1-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=3970; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=kTeOmxXhQ+ch50lt+D0cO3o/E47sgOg8CG5Ss5YITlM=; b=KB+TS9xLpfwaJ20L1fl9jkfQGuhI01ifSAlgyQxfwui9tw3ZeUGxKruSD5bIdmyqmVNTFvPEG U0sZDLWpkeWBFv4EjlOFI+yAJ+wBEoLbHx0JCbH6fem6+NkA5wTJE5l X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Current code will validate current plane and previous plane to confirm they can share a SSPP with multi-rect mode. The SSPP is already allocated for previous plane, while current plane is not associated with any SSPP yet. Null pointer is referenced when validating the SSPP of current plane. Skip SSPP validation for current plane. Unable to handle kernel NULL pointer dereference at virtual address 0000000= 000000020 Mem abort info: ESR =3D 0x0000000096000004 EC =3D 0x25: DABT (current EL), IL =3D 32 bits SET =3D 0, FnV =3D 0 EA =3D 0, S1PTW =3D 0 FSC =3D 0x04: level 0 translation fault Data abort info: ISV =3D 0, ISS =3D 0x00000004, ISS2 =3D 0x00000000 CM =3D 0, WnR =3D 0, TnD =3D 0, TagAccess =3D 0 GCS =3D 0, Overlay =3D 0, DirtyBit =3D 0, Xs =3D 0 user pgtable: 4k pages, 48-bit VAs, pgdp=3D0000000888ac3000 [0000000000000020] pgd=3D0000000000000000, p4d=3D0000000000000000 Internal error: Oops: 0000000096000004 [#1] SMP Modules linked in: CPU: 4 UID: 0 PID: 1891 Comm: modetest Tainted: G S 6.15.0= -rc2-g3ee3f6e1202e #335 PREEMPT Tainted: [S]=3DCPU_OUT_OF_SPEC Hardware name: SM8650 EV1 rev1 4slam 2et (DT) pstate: 63400009 (nZCv daif +PAN -UAO +TCO +DIT -SSBS BTYPE=3D--) pc : dpu_plane_is_multirect_capable+0x68/0x90 lr : dpu_assign_plane_resources+0x288/0x410 sp : ffff800093dcb770 x29: ffff800093dcb770 x28: 0000000000002000 x27: ffff000817c6c000 x26: ffff000806b46368 x25: ffff0008013f6080 x24: ffff00080cbf4800 x23: ffff000810842680 x22: ffff0008013f1080 x21: ffff00080cc86080 x20: ffff000806b463b0 x19: ffff00080cbf5a00 x18: 00000000ffffffff x17: 707a5f657a696c61 x16: 0000000000000003 x15: 0000000000002200 x14: 00000000ffffffff x13: 00aaaaaa00aaaaaa x12: 0000000000000000 x11: ffff000817c6e2b8 x10: 0000000000000000 x9 : ffff80008106a950 x8 : ffff00080cbf48f4 x7 : 0000000000000000 x6 : 0000000000000000 x5 : 0000000000000000 x4 : 0000000000000438 x3 : 0000000000000438 x2 : ffff800082e245e0 x1 : 0000000000000008 x0 : 0000000000000000 Call trace: dpu_plane_is_multirect_capable+0x68/0x90 (P) dpu_crtc_atomic_check+0x5bc/0x650 drm_atomic_helper_check_planes+0x13c/0x220 drm_atomic_helper_check+0x58/0xb8 msm_atomic_check+0xd8/0xf0 drm_atomic_check_only+0x4a8/0x968 drm_atomic_commit+0x50/0xd8 drm_atomic_helper_update_plane+0x140/0x188 __setplane_atomic+0xfc/0x148 drm_mode_setplane+0x164/0x378 drm_ioctl_kernel+0xc0/0x140 drm_ioctl+0x20c/0x500 __arm64_sys_ioctl+0xbc/0xf8 invoke_syscall+0x50/0x120 el0_svc_common.constprop.0+0x48/0xf8 do_el0_svc+0x28/0x40 el0_svc+0x30/0xd0 el0t_64_sync_handler+0x144/0x168 el0t_64_sync+0x198/0x1a0 Code: b9402021 370fffc1 f9401441 3707ff81 (f94010a1) ---[ end trace 0000000000000000 ]--- Fixes: 3ed12a3664b36 ("drm/msm/dpu: allow sharing SSPP between planes") Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 01171c535a27c8983aab6450d6f7a4316ae9c4ee..d20233ccd8df612fb6eee152426= 69510cf883c26 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -922,6 +922,9 @@ static int dpu_plane_is_multirect_capable(struct dpu_hw= _sspp *sspp, if (MSM_FORMAT_IS_YUV(fmt)) return false; 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Mon, 18 Aug 2025 18:31:16 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.31.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:31:15 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:30:56 +0800 Subject: [PATCH v15 02/13] drm/msm/dpu: polish log for resource allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-2-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=2319; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=xSbmnUPPIXthlmIB0KVW45Mr6GQu0WXNqCZGA6y0yZ0=; b=TPHShK0eb/kc94OcL5srQlXFgh8cNETflmBhCcqX/LqO47k+aMecMT7R+mdU+DBvAU41VKW3R g3fgYyMrSAJCGTgfX4myvRhkkQwXXYvkI3EFbw9xIYQKRt/DkLP/AQO X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= It is more likely that resource allocation may fail in complex usage case, such as quad-pipe case, than existing usage cases. A resource type ID is printed on failure in the current implementation, but the raw ID number is not explicit enough to help easily understand which resource caused the failure, so add a table to match the type ID to an human readable resource name and use it in the error print. Signed-off-by: Jun Nie Reviewed-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 25382120cb1a4f2b68b0c6573371f75fb8d489ea..2c77c74fac0fda649da8ce19b7b= 3c6cb32b9535c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -865,6 +865,21 @@ void dpu_rm_release_all_sspp(struct dpu_global_state *= global_state, ARRAY_SIZE(global_state->sspp_to_crtc_id), crtc_id); } =20 +static char *dpu_hw_blk_type_name[] =3D { + [DPU_HW_BLK_TOP] =3D "TOP", + [DPU_HW_BLK_SSPP] =3D "SSPP", + [DPU_HW_BLK_LM] =3D "LM", + [DPU_HW_BLK_CTL] =3D "CTL", + [DPU_HW_BLK_PINGPONG] =3D "pingpong", + [DPU_HW_BLK_INTF] =3D "INTF", + [DPU_HW_BLK_WB] =3D "WB", + [DPU_HW_BLK_DSPP] =3D "DSPP", + [DPU_HW_BLK_MERGE_3D] =3D "merge_3d", + [DPU_HW_BLK_DSC] =3D "DSC", + [DPU_HW_BLK_CDM] =3D "CDM", + [DPU_HW_BLK_MAX] =3D "unknown", +}; + /** * dpu_rm_get_assigned_resources - Get hw resources of the given type that= are * assigned to this encoder @@ -946,13 +961,13 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm, } =20 if (num_blks =3D=3D blks_size) { - DPU_ERROR("More than %d resources assigned to crtc %d\n", - blks_size, crtc_id); + DPU_ERROR("More than %d %s assigned to crtc %d\n", + blks_size, dpu_hw_blk_type_name[type], crtc_id); break; } if (!hw_blks[i]) { - DPU_ERROR("Allocated resource %d unavailable to assign to crtc %d\n", - type, crtc_id); + DPU_ERROR("%s unavailable to assign to crtc %d\n", + dpu_hw_blk_type_name[type], crtc_id); break; } blks[num_blks++] =3D hw_blks[i]; --=20 2.34.1 From nobody Sun Sep 7 04:26:32 2025 Received: from mail-pj1-f50.google.com (mail-pj1-f50.google.com [209.85.216.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 27E6E1EF09B for ; Tue, 19 Aug 2025 01:31:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Mon, 18 Aug 2025 18:31:21 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:31:20 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:30:57 +0800 Subject: [PATCH v15 03/13] drm/msm/dpu: decide right side per last bit Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-3-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=1985; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=KP97mkf4mFx6Hynpv+UvTtqAjJLhCHcsa39rmhW+j40=; b=YoZ5FtiM7UZD4XTi6fivtdVzU+G2ybZj+qrFjggUBlCvL1Krk5X0FNM4ec81wpW7LAShhi1N+ DMHZL59GWxPCXAwtIhih5Ir2QOQcxPAWn45fJTn5T9iZCg6Ml0flHyO X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, only one pair of mixers is supported, so a non-zero counter value is sufficient to identify the correct mixer within that pair. However, future implementations may involve multiple mixer pairs. With the current implementation, all mixers within the second pair would be incorrectly selected as right mixer. To correctly select the mixer within a pair, test the least significant bit of the counter. If the least significant bit is not set, select the mixer as left one; otherwise, select the mixer as right one for all pairs. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index d4b545448d74657aafc96e9042c7756654b4f0e7..9a40492e5aa961f7180ba4ac6c8= 6e06fcccef8c2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -377,11 +377,10 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc= _mixer *mixer, static void _dpu_crtc_program_lm_output_roi(struct drm_crtc *crtc) { struct dpu_crtc_state *crtc_state; - int lm_idx, lm_horiz_position; + int lm_idx; =20 crtc_state =3D to_dpu_crtc_state(crtc->state); =20 - lm_horiz_position =3D 0; for (lm_idx =3D 0; lm_idx < crtc_state->num_mixers; lm_idx++) { const struct drm_rect *lm_roi =3D &crtc_state->lm_bounds[lm_idx]; struct dpu_hw_mixer *hw_lm =3D crtc_state->mixers[lm_idx].hw_lm; @@ -392,7 +391,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_= crtc *crtc) =20 cfg.out_width =3D drm_rect_width(lm_roi); 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Mon, 18 Aug 2025 18:31:26 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:30:58 +0800 Subject: [PATCH v15 04/13] drm/msm/dpu: fix mixer number counter on allocation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-4-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=1366; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=OO2Z7mIWJju/0AAWi0QFQrEeFkD+xuMhO5TmIsG9bFo=; b=Dl0sF5pWfn9RHyOh3X9+toV9iaBEjSAor1oRajKpwW6z4obYTT7oFvWdRGeYf+oUPpjzPNx3z 5LYiatLWoMBDaahzNyoUttMSMXwjmvTD6Zw4bE8Ia//fq2rbkAB5S9B X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Current code only supports usage cases with one pair of mixers at most. To support quad-pipe usage case, two pairs of mixers need to be reserved. The lm_count for all pairs is cleared if a peer allocation fails in current implementation. Reset the current lm_count to an even number instead of completely clearing it. This prevents all pairs from being cleared in cases where multiple LM pairs are needed. Signed-off-by: Jun Nie Reviewed-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/d= isp/dpu1/dpu_rm.c index 2c77c74fac0fda649da8ce19b7b3c6cb32b9535c..3f344322b7f214d0050986e675b= 32522f8eb0ba7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -374,7 +374,11 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm, if (!rm->mixer_blks[i]) continue; =20 - lm_count =3D 0; + /* + * Reset lm_count to an even index. This will drop the previous + * primary mixer if failed to find its peer. + */ + lm_count &=3D ~1; lm_idx[lm_count] =3D i; =20 if (!_dpu_rm_check_lm_and_get_connected_blks(rm, global_state, --=20 2.34.1 From nobody Sun Sep 7 04:26:32 2025 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A56B11F4606 for ; Tue, 19 Aug 2025 01:31:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.180 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755567095; cv=none; b=eU6MhcfckfmiFdkVcsWASKCNa8oBwJGAvWZBwhwTOjXHaqOGt8lsCD36f2sxL9ylkUMJoNnKoKOkjS9+RBPI4w+Qq437GwDl5W3uTWdxlRVeg5IdOE9ojDkvxtbGwB+zLcfR5xGZ+YMKvaG8jiaRP9hzm9MLYNPdxcO9uFfphGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755567095; c=relaxed/simple; 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Mon, 18 Aug 2025 18:31:32 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.31.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:31:32 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:30:59 +0800 Subject: [PATCH v15 05/13] drm/msm/dpu: bind correct pingpong for quad pipe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-5-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=1809; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=flbnou7XSx1ETCmAxdlZnvB3+bqdNxru9LUU48yIE7A=; b=tjVmr1icovhUDDSu+7xCILY21LeUOkpXcuU8bCCTs9359a8eqqh7Ucze0DQ59Ne0RsSEPBbFS W+ASKuucYSxDL8++f36loqo0PdDJ1JBQt26jhvadshdJAR+5eZCiEmL X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= There are 2 interfaces and 4 pingpong in quad pipe. Map the 2nd interface to 3rd PP instead of the 2nd PP. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index b476d3c97ac9b6b4c5ca2963aa4a5805d57c8d7e..2d88d9129ec787df6dac70e6f44= 88ab77c6aeeed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1158,7 +1158,7 @@ static void dpu_encoder_virt_atomic_mode_set(struct d= rm_encoder *drm_enc, struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC]; struct dpu_hw_blk *hw_cwb[MAX_CHANNELS_PER_ENC]; - int num_ctl, num_pp, num_dsc; + int num_ctl, num_pp, num_dsc, num_pp_per_intf; int num_cwb =3D 0; bool is_cwb_encoder; unsigned int dsc_mask =3D 0; @@ -1237,10 +1237,16 @@ static void dpu_encoder_virt_atomic_mode_set(struct= drm_encoder *drm_enc, dpu_enc->cur_master->hw_cdm =3D hw_cdm ? to_dpu_hw_cdm(hw_cdm) : NULL; } =20 + /* + * There may be 4 PP and 2 INTF for quad pipe case, so INTF is not + * mapped to PP 1:1. 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Mon, 18 Aug 2025 18:31:37 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:31:37 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:00 +0800 Subject: [PATCH v15 06/13] drm/msm/dpu: Add pipe as trace argument Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-6-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=2487; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=3U0bowJZD1UHEussz5PlKOBS3bAoQPdxBHy2P4TuJ5A=; b=QtXuzwdPZXPmSH7jcPO4RtVcjz3yHVBf6AK3KIZ9C03aGoPvZkYSeCO2CbNMJ9VuLR+PViSuS Xc1xCvUeCj6ALX+hkQm5o2z9ZVblfBguniBArs7KtUIcawlRZiYVb+1 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Add pipe as trace argument in trace_dpu_crtc_setup_mixer() to ease converting pipe into pipe array later. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 9a40492e5aa961f7180ba4ac6c86e06fcccef8c2..cd0ec3edfe2fa8132e114bc1544= c389141d1c1ec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -419,7 +419,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc = *crtc, =20 trace_dpu_crtc_setup_mixer(DRMID(crtc), DRMID(plane), state, to_dpu_plane_state(state), stage_idx, - format->pixel_format, + format->pixel_format, pipe, modifier); =20 DRM_DEBUG_ATOMIC("crtc %d stage:%d - plane %d sspp %d fb %d multirect_idx= %d\n", diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_trace.h index 5307cbc2007c5044c5b897c53b44a8e356f1ad0f..cb24ad2a6d8d386bbc97b173854= c410220725a0d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -651,9 +651,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, TP_PROTO(uint32_t crtc_id, uint32_t plane_id, struct drm_plane_state *state, struct dpu_plane_state *pstate, uint32_t stage_idx, uint32_t pixel_format, - uint64_t modifier), + struct dpu_sw_pipe *pipe, uint64_t modifier), TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, - pixel_format, modifier), + pixel_format, pipe, modifier), TP_STRUCT__entry( __field( uint32_t, crtc_id ) __field( uint32_t, plane_id ) @@ -676,9 +676,9 @@ TRACE_EVENT(dpu_crtc_setup_mixer, __entry->dst_rect =3D drm_plane_state_dest(state); __entry->stage_idx =3D stage_idx; __entry->stage =3D pstate->stage; - __entry->sspp =3D pstate->pipe.sspp->idx; - __entry->multirect_idx =3D pstate->pipe.multirect_index; - __entry->multirect_mode =3D pstate->pipe.multirect_mode; + __entry->sspp =3D pipe->sspp->idx; + __entry->multirect_idx =3D pipe->multirect_index; + __entry->multirect_mode =3D pipe->multirect_mode; __entry->pixel_format =3D pixel_format; __entry->modifier =3D modifier; ), --=20 2.34.1 From nobody Sun Sep 7 04:26:32 2025 Received: from mail-pj1-f52.google.com (mail-pj1-f52.google.com [209.85.216.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 26123222568 for ; Tue, 19 Aug 2025 01:31:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.216.52 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755567106; cv=none; b=WQifI8XBhOiRo13Fl+/KBd+leiX2eeKc8sr2Ws5/9R41kagHognaOP9C9gMR8Ld8tZBZS0H+snNWQVt/SeI9kpk8kMh6pZAypTfIU2NRHEHXbOHjkUPC6mlLMSoV9eW2Q1dtSLNfnNcdL85e7CDNScs2U6jEMWRgvCUJbGctdWU= ARC-Message-Signature: i=1; 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Mon, 18 Aug 2025 18:31:43 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:31:42 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:01 +0800 Subject: [PATCH v15 07/13] drm/msm/dpu: handle pipes as array Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-7-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=18175; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=O2do4/Cgux1zUTNJ5Dlm5VV6D0+Z3W/xU4SgQ92ZmGo=; b=EwTyggZfihmlsIQRZeC5TRW1OpM6jvXeuK6xLjruPnCLLJWN9ig44Lvo+ujYUkLF0Qfami02a rL4YhNdMjGvARd6MCs1GptpHfBzQCwb+axHn21cuGuGYimchZtTdGFt X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= There are 2 pipes in a drm plane at most currently, while 4 pipes are required for quad-pipe case. Generalize the handling to pipe pair and ease handling to another pipe pair later. Store pipes in array with removing dedicated r_pipe. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 39 +++---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 181 +++++++++++++++++---------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 12 +- 3 files changed, 121 insertions(+), 111 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index cd0ec3edfe2fa8132e114bc1544c389141d1c1ec..121bd0d304b308bcd7226784eda= 14d7c7f5a46f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -449,7 +449,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, struct dpu_plane_state *pstate =3D NULL; const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; - u32 lm_idx; + u32 lm_idx, i; bool bg_alpha_enable =3D false; DECLARE_BITMAP(active_fetch, SSPP_MAX); DECLARE_BITMAP(active_pipes, SSPP_MAX); @@ -472,22 +472,17 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_cr= tc *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - set_bit(pstate->pipe.sspp->idx, active_fetch); - set_bit(pstate->pipe.sspp->idx, active_pipes); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe, 0, stage_cfg); - - if (pstate->r_pipe.sspp) { - set_bit(pstate->r_pipe.sspp->idx, active_fetch); - set_bit(pstate->r_pipe.sspp->idx, active_pipes); + + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + set_bit(pstate->pipe[i].sspp->idx, active_fetch); + set_bit(pstate->pipe[i].sspp->idx, active_pipes); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, format, fb ? fb->modifier : 0, - &pstate->r_pipe, 1, stage_cfg); + &pstate->pipe[i], i, stage_cfg); } =20 /* blend config update */ @@ -1667,15 +1662,15 @@ static int _dpu_debugfs_status_show(struct seq_file= *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); - seq_printf(s, "\tsspp[0]:%s\n", - pstate->pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[0]: mode: %d index: %d\n", - pstate->pipe.multirect_mode, pstate->pipe.multirect_index); - if (pstate->r_pipe.sspp) { - seq_printf(s, "\tsspp[1]:%s\n", - pstate->r_pipe.sspp->cap->name); - seq_printf(s, "\tmultirect[1]: mode: %d index: %d\n", - pstate->r_pipe.multirect_mode, pstate->r_pipe.multirect_index); + + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + seq_printf(s, "\tsspp[%d]:%s\n", + i, pstate->pipe[i].sspp->cap->name); + seq_printf(s, "\tmultirect[%d]: mode: %d index: %d\n", + i, pstate->pipe[i].multirect_mode, + pstate->pipe[i].multirect_index); } =20 seq_puts(s, "\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index d20233ccd8df612fb6eee15242669510cf883c26..56a0bb41424f2bd9f90173cb47f= 5ae792bbff498 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -620,6 +620,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdp= u, struct msm_drm_private *priv =3D plane->dev->dev_private; struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); u32 fill_color =3D (color & 0xFFFFFF) | ((alpha & 0xFF) << 24); + int i; =20 DPU_DEBUG_PLANE(pdpu, "\n"); =20 @@ -633,12 +634,13 @@ static void _dpu_plane_color_fill(struct dpu_plane *p= dpu, return; =20 /* update sspp */ - _dpu_plane_color_fill_pipe(pstate, &pstate->pipe, &pstate->pipe_cfg.dst_r= ect, - fill_color, fmt); - - if (pstate->r_pipe.sspp) - _dpu_plane_color_fill_pipe(pstate, &pstate->r_pipe, &pstate->r_pipe_cfg.= dst_rect, + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], + &pstate->pipe_cfg[i].dst_rect, fill_color, fmt); + } } =20 static int dpu_plane_prepare_fb(struct drm_plane *plane, @@ -820,8 +822,8 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, struct dpu_kms *kms =3D _dpu_plane_get_kms(&pdpu->base); u64 max_mdp_clk_rate =3D kms->perf.max_core_clk_rate; struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe_cfg *pipe_cfg; + struct dpu_sw_pipe_cfg *r_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; uint32_t max_linewidth; =20 @@ -846,6 +848,9 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pla= ne *plane, return -EINVAL; } =20 + /* move the assignment here, to ease handling to another pairs later */ + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; /* state->src is 16.16, src_rect is not */ drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); =20 @@ -961,10 +966,10 @@ static int dpu_plane_atomic_check_sspp(struct drm_pla= ne *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; int ret =3D 0; =20 ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, @@ -1019,15 +1024,15 @@ static int dpu_plane_try_multirect_shared(struct dp= u_plane_state *pstate, const struct msm_format *fmt, uint32_t max_linewidth) { - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe *prev_pipe =3D &prev_adjacent_pstate->pipe; - struct dpu_sw_pipe_cfg *prev_pipe_cfg =3D &prev_adjacent_pstate->pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe *prev_pipe =3D &prev_adjacent_pstate->pipe[0]; + struct dpu_sw_pipe_cfg *prev_pipe_cfg =3D &prev_adjacent_pstate->pipe_cfg= [0]; const struct msm_format *prev_fmt =3D msm_framebuffer_format(prev_adjacen= t_pstate->base.fb); u16 max_tile_height =3D 1; =20 - if (prev_adjacent_pstate->r_pipe.sspp !=3D NULL || + if (prev_adjacent_pstate->pipe[1].sspp !=3D NULL || prev_pipe->multirect_mode !=3D DPU_SSPP_MULTIRECT_NONE) return false; =20 @@ -1087,10 +1092,10 @@ static int dpu_plane_atomic_check(struct drm_plane = *plane, struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; + struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; + struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; const struct drm_crtc_state *crtc_state =3D NULL; uint32_t max_linewidth =3D dpu_kms->catalog->caps->max_linewidth; =20 @@ -1134,7 +1139,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, drm_atomic_get_old_plane_state(state, plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane_state); struct drm_crtc_state *crtc_state; - int ret; + int ret, i; =20 if (IS_ERR(plane_state)) return PTR_ERR(plane_state); @@ -1152,8 +1157,8 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - pstate->pipe.sspp =3D NULL; - pstate->r_pipe.sspp =3D NULL; + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 return 0; } @@ -1191,6 +1196,7 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; + int i; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1199,13 +1205,14 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, pstate =3D to_dpu_plane_state(plane_state); prev_adjacent_pstate =3D prev_adjacent_plane_state ? to_dpu_plane_state(prev_adjacent_plane_state) : NULL; - pipe =3D &pstate->pipe; - r_pipe =3D &pstate->r_pipe; - pipe_cfg =3D &pstate->pipe_cfg; - r_pipe_cfg =3D &pstate->r_pipe_cfg; =20 - pipe->sspp =3D NULL; - r_pipe->sspp =3D NULL; + pipe =3D &pstate->pipe[0]; + r_pipe =3D &pstate->pipe[1]; + pipe_cfg =3D &pstate->pipe_cfg[0]; + r_pipe_cfg =3D &pstate->pipe_cfg[1]; + + for (i =3D 0; i < PIPES_PER_STAGE; i++) + pstate->pipe[i].sspp =3D NULL; =20 if (!plane_state->fb) return -EINVAL; @@ -1316,6 +1323,7 @@ void dpu_plane_flush(struct drm_plane *plane) { struct dpu_plane *pdpu; struct dpu_plane_state *pstate; + int i; =20 if (!plane || !plane->state) { DPU_ERROR("invalid plane\n"); @@ -1336,8 +1344,8 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - dpu_plane_flush_csc(pdpu, &pstate->pipe); - dpu_plane_flush_csc(pdpu, &pstate->r_pipe); + for (i =3D 0; i < PIPES_PER_STAGE; i++) + dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 /* flag h/w flush complete */ @@ -1438,15 +1446,12 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe; - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; struct drm_crtc *crtc =3D state->crtc; struct drm_framebuffer *fb =3D state->fb; bool is_rt_pipe; const struct msm_format *fmt =3D msm_framebuffer_format(fb); - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + int i; =20 pstate->pending =3D true; =20 @@ -1461,12 +1466,12 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, crtc->base.id, DRM_RECT_ARG(&state->dst), &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 - dpu_plane_sspp_update_pipe(plane, pipe, pipe_cfg, fmt, - drm_mode_vrefresh(&crtc->mode), - &pstate->layout); - - if (r_pipe->sspp) { - dpu_plane_sspp_update_pipe(plane, r_pipe, r_pipe_cfg, fmt, + /* move the assignment here, to ease handling to another pairs later */ + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], + &pstate->pipe_cfg[i], fmt, drm_mode_vrefresh(&crtc->mode), &pstate->layout); } @@ -1474,15 +1479,17 @@ static void dpu_plane_sspp_atomic_update(struct drm= _plane *plane, if (pstate->needs_qos_remap) pstate->needs_qos_remap =3D false; =20 - pstate->plane_fetch_bw =3D _dpu_plane_calc_bw(pdpu->catalog, fmt, - &crtc->mode, pipe_cfg); - - pstate->plane_clk =3D _dpu_plane_calc_clk(&crtc->mode, pipe_cfg); - - if (r_pipe->sspp) { - pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, &crtc= ->mode, r_pipe_cfg); + pstate->plane_fetch_bw =3D 0; + pstate->plane_clk =3D 0; + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, + &crtc->mode, &pstate->pipe_cfg[i]); =20 - pstate->plane_clk =3D max(pstate->plane_clk, _dpu_plane_calc_clk(&crtc->= mode, r_pipe_cfg)); + pstate->plane_clk =3D max(pstate->plane_clk, + _dpu_plane_calc_clk(&crtc->mode, + &pstate->pipe_cfg[i])); } } =20 @@ -1490,17 +1497,31 @@ static void _dpu_plane_atomic_disable(struct drm_pl= ane *plane) { struct drm_plane_state *state =3D plane->state; struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; + struct dpu_sw_pipe *pipe; + int i; =20 - trace_dpu_plane_disable(DRMID(plane), false, - pstate->pipe.multirect_mode); + for (i =3D 0; i < PIPES_PER_STAGE; i +=3D 1) { + pipe =3D &pstate->pipe[i]; + if (!pipe->sspp) + continue; =20 - if (r_pipe->sspp) { - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + trace_dpu_plane_disable(DRMID(plane), false, + pstate->pipe[i].multirect_mode); =20 - if (r_pipe->sspp->ops.setup_multirect) - r_pipe->sspp->ops.setup_multirect(r_pipe); + if (!pipe->sspp) + continue; + + if (i % PIPES_PER_STAGE =3D=3D 0) + continue; + + /* + * clear multirect for the right pipe so that the SSPP + * can be further reused in the solo mode + */ + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + if (pipe->sspp->ops.setup_multirect) + pipe->sspp->ops.setup_multirect(pipe); } =20 pstate->pending =3D true; @@ -1595,31 +1616,26 @@ static void dpu_plane_atomic_print_state(struct drm= _printer *p, const struct drm_plane_state *state) { const struct dpu_plane_state *pstate =3D to_dpu_plane_state(state); - const struct dpu_sw_pipe *pipe =3D &pstate->pipe; - const struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg; - const struct dpu_sw_pipe *r_pipe =3D &pstate->r_pipe; - const struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->r_pipe_cfg; + const struct dpu_sw_pipe *pipe; + const struct dpu_sw_pipe_cfg *pipe_cfg; + int i; =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - if (pipe->sspp) { - drm_printf(p, "\tsspp[0]=3D%s\n", pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[0]=3D%s\n", + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe =3D &pstate->pipe[i]; + if (!pipe->sspp) + continue; + pipe_cfg =3D &pstate->pipe_cfg[i]; + drm_printf(p, "\tsspp[%d]=3D%s\n", i, pipe->sspp->cap->name); + drm_printf(p, "\tmultirect_mode[%d]=3D%s\n", i, dpu_get_multirect_mode(pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[0]=3D%s\n", + drm_printf(p, "\tmultirect_index[%d]=3D%s\n", i, dpu_get_multirect_index(pipe->multirect_index)); - drm_printf(p, "\tsrc[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->s= rc_rect)); - drm_printf(p, "\tdst[0]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&pipe_cfg->d= st_rect)); - } - - if (r_pipe->sspp) { - drm_printf(p, "\tsspp[1]=3D%s\n", r_pipe->sspp->cap->name); - drm_printf(p, "\tmultirect_mode[1]=3D%s\n", - dpu_get_multirect_mode(r_pipe->multirect_mode)); - drm_printf(p, "\tmultirect_index[1]=3D%s\n", - dpu_get_multirect_index(r_pipe->multirect_index)); - drm_printf(p, "\tsrc[1]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg-= >src_rect)); - drm_printf(p, "\tdst[1]=3D" DRM_RECT_FMT "\n", DRM_RECT_ARG(&r_pipe_cfg-= >dst_rect)); + drm_printf(p, "\tsrc[%d]=3D" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->src_rect)); + drm_printf(p, "\tdst[%d]=3D" DRM_RECT_FMT "\n", i, + DRM_RECT_ARG(&pipe_cfg->dst_rect)); } } =20 @@ -1657,14 +1673,17 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane = *plane, bool enable) struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(plane->state); struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + int i; =20 if (!pdpu->is_rt_pipe) return; =20 pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); - if (pstate->r_pipe.sspp) - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + if (!pstate->pipe[i].sspp) + continue; + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); + } pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index a3a6e9028333052cbaa92830c68e2315c664c239..007f044499b99ac9c2e4b58e98e= 6add013a986de 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -17,10 +17,8 @@ /** * struct dpu_plane_state: Define dpu extension of drm plane state object * @base: base drm plane state object - * @pipe: software pipe description - * @r_pipe: software pipe description of the second pipe - * @pipe_cfg: software pipe configuration - * @r_pipe_cfg: software pipe configuration for the second pipe + * @pipe: software pipe description array + * @pipe_cfg: software pipe configuration array * @stage: assigned by crtc blender * @needs_qos_remap: qos remap settings need to be updated * @multirect_index: index of the rectangle of SSPP @@ -33,10 +31,8 @@ */ struct dpu_plane_state { struct drm_plane_state base; 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Mon, 18 Aug 2025 18:31:48 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.31.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:31:47 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:02 +0800 Subject: [PATCH v15 08/13] drm/msm/dpu: split PIPES_PER_STAGE definition per plane and mixer Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-8-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=6393; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=DH8FWPS4RF5XJeZ9fwwCAQI3ONxzEi0X3SXwlBoQsOQ=; b=Uk17cB/vS9tmb+yQ6t/kf+rEVrvYBs1MTtG3Lqtps/Qs9qt/9wLcPX41ydFLPsGbM9OOhhx/f 765Sf4jwagbCsEvGJLxN6AwTz2T2AM51TqLfMxJjYS0/lcDaGBrYO6L X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= The stage contains configuration for a mixer pair. Currently the plane supports just one stage and 2 pipes. Quad-pipe support will require handling 2 stages and 4 pipes at the same time. In preparation for that add a separate define, PIPES_PER_PLANE, to denote number of pipes that can be used by the plane. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 7 +++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 18 +++++++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 4 ++-- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 121bd0d304b308bcd7226784eda14d7c7f5a46f4..30fbd7565b82c6b6b13dc3ec0f4= c91328a8e94c9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -472,8 +472,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; set_bit(pstate->pipe[i].sspp->idx, active_fetch); @@ -1305,7 +1304,7 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *= crtc, struct drm_crtc_state return ret; } =20 -#define MAX_CHANNELS_PER_CRTC 2 +#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE #define MAX_HDISPLAY_SPLIT 1080 =20 static struct msm_display_topology dpu_crtc_get_topology( @@ -1663,7 +1662,7 @@ static int _dpu_debugfs_status_show(struct seq_file *= s, void *data) state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; seq_printf(s, "\tsspp[%d]:%s\n", diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 175639c8bfbb9bbd02ed35f1780bcbd869f08c36..9f75b497aa0c939296207d58dde= 32028d0a76a6d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,6 +34,7 @@ #define DPU_MAX_PLANES 4 #endif =20 +#define PIPES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #ifndef DPU_MAX_DE_CURVES #define DPU_MAX_DE_CURVES 3 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 56a0bb41424f2bd9f90173cb47f5ae792bbff498..d3db843d324efcda5477a7eac73= a8872a55e95e5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -634,7 +634,7 @@ static void _dpu_plane_color_fill(struct dpu_plane *pdp= u, return; =20 /* update sspp */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; _dpu_plane_color_fill_pipe(pstate, &pstate->pipe[i], @@ -1157,7 +1157,7 @@ static int dpu_plane_virtual_atomic_check(struct drm_= plane *plane, * resources are freed by dpu_crtc_assign_plane_resources(), * but clean them here. */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 return 0; @@ -1211,7 +1211,7 @@ static int dpu_plane_virtual_assign_resources(struct = drm_crtc *crtc, pipe_cfg =3D &pstate->pipe_cfg[0]; r_pipe_cfg =3D &pstate->pipe_cfg[1]; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 if (!plane_state->fb) @@ -1344,7 +1344,7 @@ void dpu_plane_flush(struct drm_plane *plane) /* force 100% alpha */ _dpu_plane_color_fill(pdpu, pdpu->color_fill, 0xFF); else { - for (i =3D 0; i < PIPES_PER_STAGE; i++) + for (i =3D 0; i < PIPES_PER_PLANE; i++) dpu_plane_flush_csc(pdpu, &pstate->pipe[i]); } =20 @@ -1467,7 +1467,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_p= lane *plane, &fmt->pixel_format, MSM_FORMAT_IS_UBWC(fmt)); =20 /* move the assignment here, to ease handling to another pairs later */ - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; dpu_plane_sspp_update_pipe(plane, &pstate->pipe[i], @@ -1481,7 +1481,7 @@ static void dpu_plane_sspp_atomic_update(struct drm_p= lane *plane, =20 pstate->plane_fetch_bw =3D 0; pstate->plane_clk =3D 0; - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; pstate->plane_fetch_bw +=3D _dpu_plane_calc_bw(pdpu->catalog, fmt, @@ -1500,7 +1500,7 @@ static void _dpu_plane_atomic_disable(struct drm_plan= e *plane) struct dpu_sw_pipe *pipe; int i; =20 - for (i =3D 0; i < PIPES_PER_STAGE; i +=3D 1) { + for (i =3D 0; i < PIPES_PER_PLANE; i +=3D 1) { pipe =3D &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1622,7 +1622,7 @@ static void dpu_plane_atomic_print_state(struct drm_p= rinter *p, =20 drm_printf(p, "\tstage=3D%d\n", pstate->stage); =20 - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { pipe =3D &pstate->pipe[i]; if (!pipe->sspp) continue; @@ -1679,7 +1679,7 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *p= lane, bool enable) return; =20 pm_runtime_get_sync(&dpu_kms->pdev->dev); - for (i =3D 0; i < PIPES_PER_STAGE; i++) { + for (i =3D 0; i < PIPES_PER_PLANE; i++) { if (!pstate->pipe[i].sspp) continue; _dpu_plane_set_qos_ctrl(plane, &pstate->pipe[i], enable); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.h index 007f044499b99ac9c2e4b58e98e6add013a986de..1ef5a041b8acae270826f20ea95= 53cbfa35a9f82 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -31,8 +31,8 @@ */ struct dpu_plane_state { struct drm_plane_state base; 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Mon, 18 Aug 2025 18:31:53 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.31.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:31:53 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:03 +0800 Subject: [PATCH v15 09/13] drm/msm/dpu: Use dedicated WB number definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-9-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The case of 4 channels per encoder is to be added. To avoid breaking current WB usage case, use dedicated WB definition before 4 WB usage case is supported in future. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 2d88d9129ec787df6dac70e6f4488ab77c6aeeed..4616b360812491afbe63f8ffd4a= 57bc9604382e7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -56,6 +56,7 @@ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 #define MAX_CHANNELS_PER_ENC 2 +#define MAX_CWB_PER_ENC 2 =20 #define IDLE_SHORT_TIMEOUT 1 =20 @@ -182,7 +183,7 @@ struct dpu_encoder_virt { struct dpu_encoder_phys *cur_master; struct dpu_encoder_phys *cur_slave; struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC]; struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; =20 unsigned int dsc_mask; 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Mon, 18 Aug 2025 18:31:59 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.31.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:31:58 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:04 +0800 Subject: [PATCH v15 10/13] drm/msm/dpu: blend pipes per mixer pairs config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-10-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=5682; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=CF4TPmOyKCuR1vONvBUPDXaEUNdePxwbzP99ZGSmrmQ=; b=jKyLYb95TCPGlUadXL4PbylqmJLTLCu78NFY2cQoAD+xKmhwDKWqC0oq1VHOuz4fmV3pGXzK6 i/+2b9o2NPxDuu4tfIGjpVCgmQw0qYReY8ApquDVJi6dQl8mrfxl1Cf X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, only 2 pipes are used at most for a plane. A stage structure describes the configuration for a mixer pair. So only one stage is needed for current usage cases. The quad-pipe case will be added in future and 2 stages are used in the case. So extend the stage to an array with array size STAGES_PER_PLANE and blend pipes per mixer pair with configuration in the stage structure. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 49 ++++++++++++++++++-------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 3 +- 2 files changed, 33 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 30fbd7565b82c6b6b13dc3ec0f4c91328a8e94c9..c7dc5b47ae18ebd78de30d2a060= 5caa7dd547850 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -400,7 +400,7 @@ static void _dpu_crtc_program_lm_output_roi(struct drm_= crtc *crtc) static void _dpu_crtc_blend_setup_pipe(struct drm_crtc *crtc, struct drm_plane *plane, struct dpu_crtc_mixer *mixer, - u32 num_mixers, + u32 lms_in_pair, enum dpu_stage stage, const struct msm_format *format, uint64_t modifier, @@ -434,7 +434,7 @@ static void _dpu_crtc_blend_setup_pipe(struct drm_crtc = *crtc, stage_cfg->multirect_index[stage][stage_idx] =3D pipe->multirect_index; =20 /* blend config update */ - for (lm_idx =3D 0; lm_idx < num_mixers; lm_idx++) + for (lm_idx =3D 0; lm_idx < lms_in_pair; lm_idx++) mixer[lm_idx].lm_ctl->ops.update_pending_flush_sspp(mixer[lm_idx].lm_ctl= , sspp_idx); } =20 @@ -449,7 +449,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, struct dpu_plane_state *pstate =3D NULL; const struct msm_format *format; struct dpu_hw_ctl *ctl =3D mixer->lm_ctl; - u32 lm_idx, i; + u32 lm_idx, stage, i, pipe_idx, head_pipe_in_stage, lms_in_pair; bool bg_alpha_enable =3D false; DECLARE_BITMAP(active_fetch, SSPP_MAX); DECLARE_BITMAP(active_pipes, SSPP_MAX); @@ -472,16 +472,25 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_cr= tc *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - for (i =3D 0; i < PIPES_PER_PLANE; i++) { - if (!pstate->pipe[i].sspp) - continue; - set_bit(pstate->pipe[i].sspp->idx, active_fetch); - set_bit(pstate->pipe[i].sspp->idx, active_pipes); - _dpu_crtc_blend_setup_pipe(crtc, plane, - mixer, cstate->num_mixers, - pstate->stage, - format, fb ? fb->modifier : 0, - &pstate->pipe[i], i, stage_cfg); + /* loop pipe per mixer pair with config in stage structure */ + for (stage =3D 0; stage < STAGES_PER_PLANE; stage++) { + head_pipe_in_stage =3D stage * PIPES_PER_STAGE; + for (i =3D 0; i < PIPES_PER_STAGE; i++) { + pipe_idx =3D i + head_pipe_in_stage; + if (!pstate->pipe[pipe_idx].sspp) + continue; + lms_in_pair =3D min(cstate->num_mixers - (stage * PIPES_PER_STAGE), + PIPES_PER_STAGE); + set_bit(pstate->pipe[pipe_idx].sspp->idx, active_fetch); + set_bit(pstate->pipe[pipe_idx].sspp->idx, active_pipes); + _dpu_crtc_blend_setup_pipe(crtc, plane, + &mixer[head_pipe_in_stage], + lms_in_pair, + pstate->stage, + format, fb ? fb->modifier : 0, + &pstate->pipe[pipe_idx], i, + &stage_cfg[stage]); + } } =20 /* blend config update */ @@ -517,7 +526,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_crtc_mixer *mixer =3D cstate->mixers; struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; - struct dpu_hw_stage_cfg stage_cfg; + struct dpu_hw_stage_cfg stage_cfg[STAGES_PER_PLANE]; DECLARE_BITMAP(active_lms, LM_MAX); int i; =20 @@ -538,10 +547,10 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *cr= tc) } =20 /* initialize stage cfg */ - memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(&stage_cfg, 0, sizeof(stage_cfg)); memset(active_lms, 0, sizeof(active_lms)); =20 - _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); + _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, stage_cfg); =20 for (i =3D 0; i < cstate->num_mixers; i++) { ctl =3D mixer[i].lm_ctl; @@ -562,13 +571,17 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *cr= tc) mixer[i].mixer_op_mode, ctl->idx - CTL_0); =20 + /* + * call dpu_hw_ctl_setup_blendstage() to blend layers per stage cfg. + * stage data is shared between PIPES_PER_STAGE pipes. + */ if (ctl->ops.setup_blendstage) ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + &stage_cfg[i / PIPES_PER_STAGE]); =20 if (lm->ops.setup_blendstage) lm->ops.setup_blendstage(lm, mixer[i].hw_lm->idx, - &stage_cfg); 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Mon, 18 Aug 2025 18:32:05 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.32.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:32:04 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:05 +0800 Subject: [PATCH v15 11/13] drm/msm/dpu: support SSPP assignment for quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-11-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=9398; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=OhDnd2gXdAgyPEg+bHKAqPslfN0Sae4YKz05SBVvkhk=; b=chrqfPGrTpPopdrqnD2cPasAzn9ufhKPlKgKwlF6nAA++oPnKy1o3ut1nIIkP0TRjdBUeAi5y CmFWimeCk6cCA9CLv2j6kMyUv36dJh6KYla/f/QctSkqtdcQGwlCwH6 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, SSPPs are assigned to a maximum of two pipes. However, quad-pipe usage scenarios require four pipes and involve configuring two stages. In quad-pipe case, the first two pipes share a set of mixer configurations and enable multi-rect mode when certain conditions are met. The same applies to the subsequent two pipes. Assign SSPPs to the pipes in each stage using a unified method and to loop the stages accordingly. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 150 ++++++++++++++++++--------= ---- 1 file changed, 89 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index d3db843d324efcda5477a7eac73a8872a55e95e5..99c902dfa7e0256028d294113a3= e9bad0e1a0069 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -957,6 +957,23 @@ static int dpu_plane_is_multirect_parallel_capable(str= uct dpu_hw_sspp *sspp, dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth); } =20 +static bool dpu_plane_get_single_pipe_in_stage(struct dpu_plane_state *pst= ate, + struct dpu_sw_pipe **single_pipe, + struct dpu_sw_pipe_cfg **single_pipe_cfg, + int stage_index) +{ + int pipe_idx; + + pipe_idx =3D stage_index * PIPES_PER_STAGE; + if (drm_rect_width(&pstate->pipe_cfg[pipe_idx].src_rect) !=3D 0 && + drm_rect_width(&pstate->pipe_cfg[pipe_idx + 1].src_rect) =3D=3D 0) { + *single_pipe =3D &pstate->pipe[pipe_idx]; + *single_pipe_cfg =3D &pstate->pipe_cfg[pipe_idx]; + return true; + } + + return false; +} =20 static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, struct drm_atomic_state *state, @@ -1022,17 +1039,20 @@ static bool dpu_plane_try_multirect_parallel(struct= dpu_sw_pipe *pipe, struct dp static int dpu_plane_try_multirect_shared(struct dpu_plane_state *pstate, struct dpu_plane_state *prev_adjacent_pstate, const struct msm_format *fmt, - uint32_t max_linewidth) + uint32_t max_linewidth, int stage_index) { - struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; - struct dpu_sw_pipe *prev_pipe =3D &prev_adjacent_pstate->pipe[0]; - struct dpu_sw_pipe_cfg *prev_pipe_cfg =3D &prev_adjacent_pstate->pipe_cfg= [0]; + struct dpu_sw_pipe *pipe, *prev_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg, *prev_pipe_cfg; const struct msm_format *prev_fmt =3D msm_framebuffer_format(prev_adjacen= t_pstate->base.fb); u16 max_tile_height =3D 1; =20 - if (prev_adjacent_pstate->pipe[1].sspp !=3D NULL || + if (!dpu_plane_get_single_pipe_in_stage(pstate, &pipe, + &pipe_cfg, stage_index)) + return false; + + if (!dpu_plane_get_single_pipe_in_stage(prev_adjacent_pstate, + &prev_pipe, &prev_pipe_cfg, + stage_index) || prev_pipe->multirect_mode !=3D DPU_SSPP_MULTIRECT_NONE) return false; =20 @@ -1047,11 +1067,6 @@ static int dpu_plane_try_multirect_shared(struct dpu= _plane_state *pstate, if (MSM_FORMAT_IS_UBWC(prev_fmt)) max_tile_height =3D max(max_tile_height, prev_fmt->tile_height); =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->sspp =3D NULL; - if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) && dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth)= && (pipe_cfg->dst_rect.x1 >=3D prev_pipe_cfg->dst_rect.x2 || @@ -1180,36 +1195,69 @@ static int dpu_plane_virtual_atomic_check(struct dr= m_plane *plane, return 0; } =20 +static int dpu_plane_assign_resource_in_stage(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + struct drm_plane_state *plane_state, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs) +{ + struct drm_plane *plane =3D plane_state->plane; + struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + struct dpu_sw_pipe *r_pipe =3D pipe + 1; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D pipe_cfg + 1; + + if (drm_rect_width(&pipe_cfg->src_rect) =3D=3D 0) + return 0; + + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, reqs= ); + if (!pipe->sspp) + return -ENODEV; + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + if (drm_rect_width(&r_pipe_cfg->src_rect) =3D=3D 0) + return 0; + + if (dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, + pipe->sspp, + msm_framebuffer_format(plane_state->fb), + dpu_kms->catalog->caps->max_linewidth)) + return 0; + + r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, re= qs); + if (!r_pipe->sspp) + return -ENODEV; + r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + + return 0; +} + static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_global_state *global_state, struct drm_atomic_state *state, struct drm_plane_state *plane_state, - struct drm_plane_state *prev_adjacent_plane_state) + struct drm_plane_state **prev_adjacent_plane_state) { const struct drm_crtc_state *crtc_state =3D NULL; struct drm_plane *plane =3D plane_state->plane; struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); struct dpu_rm_sspp_requirements reqs; - struct dpu_plane_state *pstate, *prev_adjacent_pstate; + struct dpu_plane_state *pstate, *prev_adjacent_pstate[STAGES_PER_PLANE]; struct dpu_sw_pipe *pipe; - struct dpu_sw_pipe *r_pipe; struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; - int i; + int i, ret; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, plane_state->crtc); =20 pstate =3D to_dpu_plane_state(plane_state); - prev_adjacent_pstate =3D prev_adjacent_plane_state ? - to_dpu_plane_state(prev_adjacent_plane_state) : NULL; - - pipe =3D &pstate->pipe[0]; - r_pipe =3D &pstate->pipe[1]; - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; + for (i =3D 0; i < STAGES_PER_PLANE; i++) + prev_adjacent_pstate[i] =3D prev_adjacent_plane_state[i] ? + to_dpu_plane_state(prev_adjacent_plane_state[i]) : NULL; =20 for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; @@ -1224,42 +1272,24 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 reqs.rot90 =3D drm_rotation_90_or_270(plane_state->rotation); =20 - if (drm_rect_width(&r_pipe_cfg->src_rect) =3D=3D 0) { - if (!prev_adjacent_pstate || - !dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt, - dpu_kms->catalog->caps->max_linewidth)) { - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &r= eqs); - if (!pipe->sspp) - return -ENODEV; - - r_pipe->sspp =3D NULL; + for (i =3D 0; i < STAGES_PER_PLANE; i++) { + if (prev_adjacent_pstate[i] && + dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate[i], fmt, + dpu_kms->catalog->caps->max_linewidth, + i)) + continue; =20 - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + if (dpu_plane_get_single_pipe_in_stage(pstate, &pipe, &pipe_cfg, i)) + prev_adjacent_plane_state[i] =3D plane_state; =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - } - } else { - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &re= qs); - if (!pipe->sspp) - return -ENODEV; - - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, - pipe->sspp, - msm_framebuffer_format(plane_state->fb), - dpu_kms->catalog->caps->max_linewidth)) { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, = &reqs); - if (!r_pipe->sspp) - return -ENODEV; - - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - } + pipe =3D &pstate->pipe[i * PIPES_PER_STAGE]; + pipe_cfg =3D &pstate->pipe_cfg[i * PIPES_PER_STAGE]; + ret =3D dpu_plane_assign_resource_in_stage(pipe, pipe_cfg, + plane_state, + global_state, + crtc, &reqs); + if (ret) + return ret; } =20 return dpu_plane_atomic_check_sspp(plane, state, crtc_state); @@ -1272,7 +1302,7 @@ int dpu_assign_plane_resources(struct dpu_global_stat= e *global_state, unsigned int num_planes) { unsigned int i; - struct drm_plane_state *prev_adjacent_plane_state =3D NULL; + struct drm_plane_state *prev_adjacent_plane_state[STAGES_PER_PLANE] =3D {= NULL }; =20 for (i =3D 0; i < num_planes; i++) { struct drm_plane_state *plane_state =3D states[i]; @@ -1286,8 +1316,6 @@ int dpu_assign_plane_resources(struct dpu_global_stat= e *global_state, prev_adjacent_plane_state); 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Mon, 18 Aug 2025 18:32:09 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:06 +0800 Subject: [PATCH v15 12/13] drm/msm/dpu: support plane splitting in quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-12-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=9601; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=s/K2v8KckiDyZ7Nd3zMDwmTmNSSntkMNWhxQtwzHn3c=; b=WqjG0YQrLVimyFfGbmNllkThGInZTK92FRgqUWdLgD/Tb2lGGhte6ij99cOlERisWVuPBKvBK c531/pdlrfgB7PZVO/NWfh5IPxsfH6fWC/1KXtXKULLgZlFPlGLUYD0 X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= The content of every half of screen is sent out via one interface in dual-DSI case. The content for every interface is blended by a LM pair in quad-pipe case, thus a LM pair should not blend any content that cross the half of screen in this case. Clip plane into pipes per left and right half screen ROI if topology is quad pipe case. The clipped rectangle on every half of screen is futher handled by two pipes if its width exceeds a limit for a single pipe. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 11 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 + drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 137 +++++++++++++++++++++-----= ---- 3 files changed, 110 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index c7dc5b47ae18ebd78de30d2a0605caa7dd547850..1c7a5e545745320018c3e9a2d16= 3cbfd3dceaf7b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -1592,6 +1592,17 @@ int dpu_crtc_vblank(struct drm_crtc *crtc, bool en) return 0; } =20 +/** + * dpu_crtc_get_num_lm - Get mixer number in this CRTC pipeline + * @state: Pointer to drm crtc state object + */ +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state) +{ + struct dpu_crtc_state *cstate =3D to_dpu_crtc_state(state); + + return cstate->num_mixers; +} + #ifdef CONFIG_DEBUG_FS static int _dpu_debugfs_status_show(struct seq_file *s, void *data) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index 94392b9b924546f96e738ae20920cf9afd568e6b..6eaba5696e8e6bd1246a9895c4c= 8714ca6589b10 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -267,4 +267,6 @@ static inline enum dpu_crtc_client_type dpu_crtc_get_cl= ient_type( =20 void dpu_crtc_frame_event_cb(struct drm_crtc *crtc, u32 event); =20 +unsigned int dpu_crtc_get_num_lm(const struct drm_crtc_state *state); + #endif /* _DPU_CRTC_H_ */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 99c902dfa7e0256028d294113a3e9bad0e1a0069..634d9354edf2c4ec28cdef32de1= 18ae49a0ec7a8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -824,8 +824,12 @@ static int dpu_plane_atomic_check_nosspp(struct drm_pl= ane *plane, struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); struct dpu_sw_pipe_cfg *pipe_cfg; struct dpu_sw_pipe_cfg *r_pipe_cfg; + struct dpu_sw_pipe_cfg init_pipe_cfg; struct drm_rect fb_rect =3D { 0 }; + const struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; uint32_t max_linewidth; + u32 num_lm; + int stage_id, num_stages; =20 min_scale =3D FRAC_16_16(1, MAX_UPSCALE_RATIO); max_scale =3D MAX_DOWNSCALE_RATIO << 16; @@ -848,13 +852,10 @@ static int dpu_plane_atomic_check_nosspp(struct drm_p= lane *plane, return -EINVAL; } =20 - /* move the assignment here, to ease handling to another pairs later */ - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - /* state->src is 16.16, src_rect is not */ - drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + num_lm =3D dpu_crtc_get_num_lm(crtc_state); =20 - pipe_cfg->dst_rect =3D new_plane_state->dst; + /* state->src is 16.16, src_rect is not */ + drm_rect_fp_to_int(&init_pipe_cfg.src_rect, &new_plane_state->src); =20 fb_rect.x2 =3D new_plane_state->fb->width; fb_rect.y2 =3D new_plane_state->fb->height; @@ -879,35 +880,94 @@ static int dpu_plane_atomic_check_nosspp(struct drm_p= lane *plane, =20 max_linewidth =3D pdpu->catalog->caps->max_linewidth; =20 - drm_rect_rotate(&pipe_cfg->src_rect, + drm_rect_rotate(&init_pipe_cfg.src_rect, new_plane_state->fb->width, new_plane_state->fb->height, new_plane_state->rotation); =20 - if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || - _dpu_plane_calc_clk(&crtc_state->adjusted_mode, pipe_cfg) > max_mdp_= clk_rate) { - if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { - DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", - DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); - return -E2BIG; + /* + * We have 1 mixer pair cfg for 1:1:1 and 2:2:1 topology, 2 mixer pair + * configs for left and right half screen in case of 4:4:2 topology. + * But we may have 2 rect to split wide plane that exceeds limit with 1 + * config for 2:2:1. So need to handle both wide plane splitting, and + * two halves of screen splitting for quad-pipe case. Check dest + * rectangle left/right clipping first, then check wide rectangle + * splitting in every half next. + */ + num_stages =3D (num_lm + 1) / 2; + /* iterate mixer configs for this plane, to separate left/right with the = id */ + for (stage_id =3D 0; stage_id < num_stages; stage_id++) { + struct drm_rect mixer_rect =3D { + .x1 =3D stage_id * mode->hdisplay / num_stages, + .y1 =3D 0, + .x2 =3D (stage_id + 1) * mode->hdisplay / num_stages, + .y2 =3D mode->vdisplay + }; + int cfg_idx =3D stage_id * PIPES_PER_STAGE; + + pipe_cfg =3D &pstate->pipe_cfg[cfg_idx]; + r_pipe_cfg =3D &pstate->pipe_cfg[cfg_idx + 1]; + + drm_rect_fp_to_int(&pipe_cfg->src_rect, &new_plane_state->src); + pipe_cfg->dst_rect =3D new_plane_state->dst; + + DPU_DEBUG_PLANE(pdpu, "checking src " DRM_RECT_FMT + " vs clip window " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&mixer_rect)); + + /* + * If this plane does not fall into mixer rect, check next + * mixer rect. + */ + if (!drm_rect_clip_scaled(&pipe_cfg->src_rect, + &pipe_cfg->dst_rect, + &mixer_rect)) { + memset(pipe_cfg, 0, 2 * sizeof(struct dpu_sw_pipe_cfg)); + + continue; } =20 - *r_pipe_cfg =3D *pipe_cfg; - pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x2= ) >> 1; - pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x2= ) >> 1; - r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; - r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; - } else { - memset(r_pipe_cfg, 0, sizeof(*r_pipe_cfg)); - } + pipe_cfg->dst_rect.x1 -=3D mixer_rect.x1; + pipe_cfg->dst_rect.x2 -=3D mixer_rect.x1; + + DPU_DEBUG_PLANE(pdpu, "Got clip src:" DRM_RECT_FMT " dst: " DRM_RECT_FMT= "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), DRM_RECT_ARG(&pipe_cfg->dst_rect)); + + /* Split wide rect into 2 rect */ + if ((drm_rect_width(&pipe_cfg->src_rect) > max_linewidth) || + _dpu_plane_calc_clk(mode, pipe_cfg) > max_mdp_clk_rate) { + + if (drm_rect_width(&pipe_cfg->src_rect) > 2 * max_linewidth) { + DPU_DEBUG_PLANE(pdpu, "invalid src " DRM_RECT_FMT " line:%u\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), max_linewidth); + return -E2BIG; + } + + memcpy(r_pipe_cfg, pipe_cfg, sizeof(struct dpu_sw_pipe_cfg)); + pipe_cfg->src_rect.x2 =3D (pipe_cfg->src_rect.x1 + pipe_cfg->src_rect.x= 2) >> 1; + pipe_cfg->dst_rect.x2 =3D (pipe_cfg->dst_rect.x1 + pipe_cfg->dst_rect.x= 2) >> 1; + r_pipe_cfg->src_rect.x1 =3D pipe_cfg->src_rect.x2; + r_pipe_cfg->dst_rect.x1 =3D pipe_cfg->dst_rect.x2; + DPU_DEBUG_PLANE(pdpu, "Split wide plane into:" + DRM_RECT_FMT " and " DRM_RECT_FMT "\n", + DRM_RECT_ARG(&pipe_cfg->src_rect), + DRM_RECT_ARG(&r_pipe_cfg->src_rect)); + } else { + memset(r_pipe_cfg, 0, sizeof(struct dpu_sw_pipe_cfg)); + } =20 - drm_rect_rotate_inv(&pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, - new_plane_state->rotation); - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) - drm_rect_rotate_inv(&r_pipe_cfg->src_rect, - new_plane_state->fb->width, new_plane_state->fb->height, + drm_rect_rotate_inv(&pipe_cfg->src_rect, + new_plane_state->fb->width, + new_plane_state->fb->height, new_plane_state->rotation); =20 + if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) + drm_rect_rotate_inv(&r_pipe_cfg->src_rect, + new_plane_state->fb->width, + new_plane_state->fb->height, + new_plane_state->rotation); + } + pstate->needs_qos_remap =3D drm_atomic_crtc_needs_modeset(crtc_state); =20 return 0; @@ -983,20 +1043,17 @@ static int dpu_plane_atomic_check_sspp(struct drm_pl= ane *plane, drm_atomic_get_new_plane_state(state, plane); struct dpu_plane *pdpu =3D to_dpu_plane(plane); struct dpu_plane_state *pstate =3D to_dpu_plane_state(new_plane_state); - struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; - struct dpu_sw_pipe_cfg *r_pipe_cfg =3D &pstate->pipe_cfg[1]; - int ret =3D 0; - - ret =3D dpu_plane_atomic_check_pipe(pdpu, pipe, pipe_cfg, - &crtc_state->adjusted_mode, - new_plane_state); - if (ret) - return ret; + struct dpu_sw_pipe *pipe; + struct dpu_sw_pipe_cfg *pipe_cfg; + int ret =3D 0, i; =20 - if (drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0) { - ret =3D dpu_plane_atomic_check_pipe(pdpu, r_pipe, r_pipe_cfg, + for (i =3D 0; i < PIPES_PER_PLANE; i++) { + pipe =3D &pstate->pipe[i]; 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Mon, 18 Aug 2025 18:32:15 -0700 (PDT) Received: from [127.0.1.1] ([112.64.60.64]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3245e4faf80sm248637a91.5.2025.08.18.18.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 Aug 2025 18:32:14 -0700 (PDT) From: Jun Nie Date: Tue, 19 Aug 2025 09:31:07 +0800 Subject: [PATCH v15 13/13] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-v6-16-rc2-quad-pipe-upstream-v15-13-2c7a85089db8@linaro.org> References: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> In-Reply-To: <20250819-v6-16-rc2-quad-pipe-upstream-v15-0-2c7a85089db8@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755567061; l=8147; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=L0RJjmTLlYkHLbKt8l66Y1ANmmW3YDpsTiGU9UI7WH8=; b=ZcJ6S3WHQXRsMtgbOv482z83OBDYeGPM5nwtD0j76evpw/yvxjqIIAO2RxVIUUq8RJGq/nIgR GYZAkyzZd6tCRN2BIpz1aUStpKb+sw1/+d0rbEzRHK4hvdyliOc3kUr X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= To support high-resolution cases that exceed the width limitation of a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate, additional pipes are necessary to enable parallel data processing within the SSPP width constraints and MDP clock rate. Request 4 mixers and 4 DSCs for high-resolution cases where both DSC and dual interfaces are enabled. More use cases can be incorporated later if quad-pipe capabilities are required. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 27 +++++++++++++++++---= --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 28 ++++++++------------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +- 6 files changed, 35 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 1c7a5e545745320018c3e9a2d163cbfd3dceaf7b..2625ad777e477d2d5a6a746989b= b9e10493e19ad 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, struct dpu_crtc_state *crtc_state) { struct dpu_crtc_mixer *m; - u32 crcs[CRTC_DUAL_MIXERS]; + u32 crcs[CRTC_QUAD_MIXERS]; =20 int rc =3D 0; int i; @@ -1328,6 +1328,7 @@ static struct msm_display_topology dpu_crtc_get_topol= ogy( struct drm_display_mode *mode =3D &crtc_state->adjusted_mode; struct msm_display_topology topology =3D {0}; struct drm_encoder *drm_enc; + u32 num_rt_intf; =20 drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask) dpu_encoder_update_topology(drm_enc, &topology, crtc_state->state, @@ -1341,11 +1342,14 @@ static struct msm_display_topology dpu_crtc_get_top= ology( * Dual display * 2 LM, 2 INTF ( Split display using 2 interfaces) * + * If DSC is enabled, try to use 4:4:2 topology if there is enough + * resource. Otherwise, use 2:2:2 topology. + * * Single display * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) * - * If DSC is enabled, use 2 LMs for 2:2:1 topology + * If DSC is enabled, use 2:2:1 topology * * Add dspps to the reservation requirements if ctm is requested * @@ -1357,14 +1361,23 @@ static struct msm_display_topology dpu_crtc_get_top= ology( * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check. */ =20 - if (topology.num_intf =3D=3D 2 && !topology.cwb_enabled) - topology.num_lm =3D 2; - else if (topology.num_dsc =3D=3D 2) + num_rt_intf =3D topology.num_intf; + if (topology.cwb_enabled) + num_rt_intf--; + + if (topology.num_dsc) { + if (dpu_kms->catalog->dsc_count >=3D num_rt_intf * 2) + topology.num_dsc =3D num_rt_intf * 2; + else + topology.num_dsc =3D num_rt_intf; + topology.num_lm =3D topology.num_dsc; + } else if (num_rt_intf =3D=3D 2) { topology.num_lm =3D 2; - else if (dpu_kms->catalog->caps->has_3d_merge) + } else if (dpu_kms->catalog->caps->has_3d_merge) { topology.num_lm =3D (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1; - else + } else { topology.num_lm =3D 1; + } =20 if (crtc_state->ctm) topology.num_dspp =3D topology.num_lm; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index 6eaba5696e8e6bd1246a9895c4c8714ca6589b10..455073c7025b0bcb970d8817f19= 7d9bcacc6dca5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -210,7 +210,7 @@ struct dpu_crtc_state { =20 bool bw_control; bool bw_split_vote; - struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; + struct drm_rect lm_bounds[CRTC_QUAD_MIXERS]; =20 uint64_t input_fence_timeout_ns; =20 @@ -218,10 +218,10 @@ struct dpu_crtc_state { =20 /* HW Resources reserved for the crtc */ u32 num_mixers; - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; + struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS]; =20 u32 num_ctls; - struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; + struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS]; =20 enum dpu_crtc_crc_source crc_source; int crc_frame_skip_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 4616b360812491afbe63f8ffd4a57bc9604382e7..d13eeb3a707e186faec67ec02a6= 34c14414d9048 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -55,7 +55,7 @@ #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 -#define MAX_CHANNELS_PER_ENC 2 +#define MAX_CHANNELS_PER_ENC 4 #define MAX_CWB_PER_ENC 2 =20 #define IDLE_SHORT_TIMEOUT 1 @@ -675,22 +675,12 @@ void dpu_encoder_update_topology(struct drm_encoder *= drm_enc, =20 dsc =3D dpu_encoder_get_dsc_config(drm_enc); =20 - /* We only support 2 DSC mode (with 2 LM and 1 INTF) */ - if (dsc) { - /* - * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces - * when Display Stream Compression (DSC) is enabled, - * and when enough DSC blocks are available. - * This is power-optimal and can drive up to (including) 4k - * screens. - */ - WARN(topology->num_intf > 2, - "DSC topology cannot support more than 2 interfaces\n"); - if (topology->num_intf >=3D 2 || dpu_kms->catalog->dsc_count >=3D 2) - topology->num_dsc =3D 2; - else - topology->num_dsc =3D 1; - } + /* + * Set DSC number as 1 to mark the enabled status, will be adjusted + * in dpu_crtc_get_topology() + */ + if (dsc) + topology->num_dsc =3D 1; =20 connector =3D drm_atomic_get_new_connector_for_encoder(state, drm_enc); if (!connector) @@ -2179,8 +2169,8 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) struct dpu_hw_mixer_cfg mixer; int i, num_lm; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_lm[2]; - struct dpu_hw_mixer *hw_mixer[2]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC]; struct dpu_hw_ctl *ctl =3D phys_enc->hw_ctl; =20 memset(&mixer, 0, sizeof(mixer)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_encoder_phys.h index 61b22d9494546885db609efa156222792af73d2a..09395d7910ac87c035b65cf4763= 50bf6c9619612 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper= _get_3d_blend_mode( =20 /* Use merge_3d unless DSC MERGE topology is used */ if (phys_enc->split_role =3D=3D ENC_ROLE_SOLO && - dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS && + (dpu_cstate->num_mixers !=3D 1) && !dpu_encoder_use_dsc_merge(phys_enc->parent)) return BLEND_3D_H_ROW_INT; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index a78bb2c334e30bc86554bde45355808b790c6235..ce0265c13e050fbd48ac5c3202e= 8fa23edd1220d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -24,7 +24,7 @@ #define DPU_MAX_IMG_WIDTH 0x3fff #define DPU_MAX_IMG_HEIGHT 0x3fff =20 -#define CRTC_DUAL_MIXERS 2 +#define CRTC_QUAD_MIXERS 4 =20 #define MAX_XIN_COUNT 16 =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index e4875a1f638db6f1983d9c51cb399319d27675e9..5cedcda285273a46cd6e11da63c= de92cab94b9f4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,7 +34,7 @@ #define DPU_MAX_PLANES 4 #endif =20 -#define STAGES_PER_PLANE 1 +#define STAGES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE) #ifndef DPU_MAX_DE_CURVES --=20 2.34.1