From nobody Sat Oct 4 09:34:57 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2582A156678; Tue, 19 Aug 2025 07:14:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755587700; cv=none; b=dSIYPr7EVZGrfRPsO39jDeKVonLZBtTA7Y+4hygAR89Lp+1TwGJFhY9PA0YtSjUJhR1RlqwOGZDbR7aCdmF7M/RWVL0VsXi60A4kd16HdACLjVdU4w7Er110cBzm6Yzjg7Q0NIcrqg5BYm9XNcZxHn+274bBLXJhTJhR1L+pfBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755587700; c=relaxed/simple; bh=4ynEP/LZdmDMVF5wOF01p56ypGM5aDpiB2c+7/2LclI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GhLHzqRjc6lr+8ROZaQIlE0Gz8OU/cYBAgUvv92+ZpL32N36+udxCpragOE8GCea/3hxP/cg7wPpADetaoB+QSrw5fp2PmXPkinN6hx45fLKYhw53P5VSVL35Rqc/I8qZljErua4zYdzj6dbB1RbXvdxnigcfiTCTHFciyfvjlQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f0ZvuWHD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f0ZvuWHD" Received: by smtp.kernel.org (Postfix) with ESMTPS id C44DAC116B1; Tue, 19 Aug 2025 07:14:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755587699; bh=4ynEP/LZdmDMVF5wOF01p56ypGM5aDpiB2c+7/2LclI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=f0ZvuWHDF8KN89qEVd0d0pCjLnTqYcyrDAJPrBuG6N8SyaBlMHQrLWqDAQEohy90q 5lMFEX3VxaySwHms/K38AuUGjbucnGTtn59EyAZ41Yngk6dR42Ss1M/U0C8a0u4r+p IU3Ax276LZrJGTjwj0wM+J4A5lYlhgIpTyw6SDj8jD4au9Ge9zPXWOv1ri4YaOat4s xwUWLLj0nE7LH3MAV/uRqS7FScTJuj1THolArtMZBKuOSkhwQMwFwhiRgbn/jbHJm9 sovwksgP6hH7+yUQrIj35enU66Bk8QXtJw2dQfsSs5Vv1JptEDOEacQOWjO2/M6790 VXLKtfXP7MMuA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5768CA0EE6; Tue, 19 Aug 2025 07:14:59 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 19 Aug 2025 12:44:50 +0530 Subject: [PATCH 1/6] PCI: qcom: Wait for PCIE_RESET_CONFIG_WAIT_MS after PERST# deassert Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-pci-pwrctrl-perst-v1-1-4b74978d2007@oss.qualcomm.com> References: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> In-Reply-To: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Saravana Kannan Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krishna Chaitanya Chundru , Brian Norris , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2012; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=nLv3p5NCWxDbWHE2Z9fkpVFUk3/5sd3FgmEvC3XmSR8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBopCRwHaNQlIGTz2WlNHiLQk/TU/lg6dlcKu/OW 2+SQDBN8C2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaKQkcAAKCRBVnxHm/pHO 9RC3B/9InRKjynqx2jgZo/S6kWGMeiLWVsr5SMXAngTM1r+pslxKagLJ3vLPV74z4Q9fP0cOi/7 8lSM5rQJe0z0UprD2GqemPsIHmN80aXWjyKwX0ZW5CZcadJWzx8idNe46VfjJ55oP7dPM46YLhI MHOu2mjeiId5VtRwKGZKzuy/b+Qn6mDWl5fepDjolPffoeGbqwvhg4qk+c95ZxM0l5kcw7Cf5Xg PFGM/Y9Z9VoFVN6sRitO3h+5gZZ7WAKOPlMYH23Ihfr9WEKx7kErnWt/rAIyGCQWpy9ylazRZbC HmkLHmVAfJu/+r/ZfgC+Ojn1qg1QlAI4klip3lNgIhGW4WVm X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam PCIe spec r6.0, sec 6.6.1 mandates waiting for 100ms before deasserting PERST# if the downstream port does not support Link speeds greater than 5.0 GT/s. But in practice, this delay seem to be required irrespective of the supported link speed as it gives the endpoints enough time to initialize. Hence, add the delay by reusing the PCIE_RESET_CONFIG_WAIT_MS definition if the linkup_irq is not supported. If the linkup_irq is supported, the driver already waits for 100ms in the IRQ handler post link up. Also, remove the redundant comment for PCIE_T_PVPERL_MS. Finally, the PERST_DELAY_US sleep can be moved to PERST# assert where it should be. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 294babe1816e4d0c2b2343fe22d89af72afcd6cd..bcd080315d70e64eafdefd85274= 0fe07df3dbe75 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -302,20 +302,22 @@ static void qcom_perst_assert(struct qcom_pcie *pcie,= bool assert) else list_for_each_entry(port, &pcie->ports, list) gpiod_set_value_cansleep(port->reset, val); - - usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { qcom_perst_assert(pcie, true); + usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) { - /* Ensure that PERST has been asserted for at least 100 ms */ + struct dw_pcie_rp *pp =3D &pcie->pci->pp; + msleep(PCIE_T_PVPERL_MS); qcom_perst_assert(pcie, false); + if (!pp->use_linkup_irq) + msleep(PCIE_RESET_CONFIG_WAIT_MS); } =20 static int qcom_pcie_start_link(struct dw_pcie *pci) --=20 2.45.2