From nobody Sat Oct 4 08:08:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2582A156678; Tue, 19 Aug 2025 07:14:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755587700; cv=none; b=dSIYPr7EVZGrfRPsO39jDeKVonLZBtTA7Y+4hygAR89Lp+1TwGJFhY9PA0YtSjUJhR1RlqwOGZDbR7aCdmF7M/RWVL0VsXi60A4kd16HdACLjVdU4w7Er110cBzm6Yzjg7Q0NIcrqg5BYm9XNcZxHn+274bBLXJhTJhR1L+pfBA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755587700; c=relaxed/simple; bh=4ynEP/LZdmDMVF5wOF01p56ypGM5aDpiB2c+7/2LclI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GhLHzqRjc6lr+8ROZaQIlE0Gz8OU/cYBAgUvv92+ZpL32N36+udxCpragOE8GCea/3hxP/cg7wPpADetaoB+QSrw5fp2PmXPkinN6hx45fLKYhw53P5VSVL35Rqc/I8qZljErua4zYdzj6dbB1RbXvdxnigcfiTCTHFciyfvjlQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=f0ZvuWHD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="f0ZvuWHD" Received: by smtp.kernel.org (Postfix) with ESMTPS id C44DAC116B1; Tue, 19 Aug 2025 07:14:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1755587699; bh=4ynEP/LZdmDMVF5wOF01p56ypGM5aDpiB2c+7/2LclI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=f0ZvuWHDF8KN89qEVd0d0pCjLnTqYcyrDAJPrBuG6N8SyaBlMHQrLWqDAQEohy90q 5lMFEX3VxaySwHms/K38AuUGjbucnGTtn59EyAZ41Yngk6dR42Ss1M/U0C8a0u4r+p IU3Ax276LZrJGTjwj0wM+J4A5lYlhgIpTyw6SDj8jD4au9Ge9zPXWOv1ri4YaOat4s xwUWLLj0nE7LH3MAV/uRqS7FScTJuj1THolArtMZBKuOSkhwQMwFwhiRgbn/jbHJm9 sovwksgP6hH7+yUQrIj35enU66Bk8QXtJw2dQfsSs5Vv1JptEDOEacQOWjO2/M6790 VXLKtfXP7MMuA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5768CA0EE6; Tue, 19 Aug 2025 07:14:59 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 19 Aug 2025 12:44:50 +0530 Subject: [PATCH 1/6] PCI: qcom: Wait for PCIE_RESET_CONFIG_WAIT_MS after PERST# deassert Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-pci-pwrctrl-perst-v1-1-4b74978d2007@oss.qualcomm.com> References: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> In-Reply-To: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Saravana Kannan Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krishna Chaitanya Chundru , Brian Norris , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2012; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=nLv3p5NCWxDbWHE2Z9fkpVFUk3/5sd3FgmEvC3XmSR8=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBopCRwHaNQlIGTz2WlNHiLQk/TU/lg6dlcKu/OW 2+SQDBN8C2JATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaKQkcAAKCRBVnxHm/pHO 9RC3B/9InRKjynqx2jgZo/S6kWGMeiLWVsr5SMXAngTM1r+pslxKagLJ3vLPV74z4Q9fP0cOi/7 8lSM5rQJe0z0UprD2GqemPsIHmN80aXWjyKwX0ZW5CZcadJWzx8idNe46VfjJ55oP7dPM46YLhI MHOu2mjeiId5VtRwKGZKzuy/b+Qn6mDWl5fepDjolPffoeGbqwvhg4qk+c95ZxM0l5kcw7Cf5Xg PFGM/Y9Z9VoFVN6sRitO3h+5gZZ7WAKOPlMYH23Ihfr9WEKx7kErnWt/rAIyGCQWpy9ylazRZbC HmkLHmVAfJu/+r/ZfgC+Ojn1qg1QlAI4klip3lNgIhGW4WVm X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam PCIe spec r6.0, sec 6.6.1 mandates waiting for 100ms before deasserting PERST# if the downstream port does not support Link speeds greater than 5.0 GT/s. But in practice, this delay seem to be required irrespective of the supported link speed as it gives the endpoints enough time to initialize. Hence, add the delay by reusing the PCIE_RESET_CONFIG_WAIT_MS definition if the linkup_irq is not supported. If the linkup_irq is supported, the driver already waits for 100ms in the IRQ handler post link up. Also, remove the redundant comment for PCIE_T_PVPERL_MS. Finally, the PERST_DELAY_US sleep can be moved to PERST# assert where it should be. Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 294babe1816e4d0c2b2343fe22d89af72afcd6cd..bcd080315d70e64eafdefd85274= 0fe07df3dbe75 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -302,20 +302,22 @@ static void qcom_perst_assert(struct qcom_pcie *pcie,= bool assert) else list_for_each_entry(port, &pcie->ports, list) gpiod_set_value_cansleep(port->reset, val); - - usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) { qcom_perst_assert(pcie, true); + usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) { - /* Ensure that PERST has been asserted for at least 100 ms */ + struct dw_pcie_rp *pp =3D &pcie->pci->pp; + msleep(PCIE_T_PVPERL_MS); qcom_perst_assert(pcie, false); + if (!pp->use_linkup_irq) + msleep(PCIE_RESET_CONFIG_WAIT_MS); } =20 static int qcom_pcie_start_link(struct dw_pcie *pci) --=20 2.45.2 From nobody Sat Oct 4 08:08:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 31CAD26CE12; Tue, 19 Aug 2025 07:14:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755587700; cv=none; b=e2QgZsVU9s0xwv6au4BoesNIJy0UgzE/WAO8Ty+N8Ca7O5Oxo7atazMhLbLKSnNKaYT/cz6yc/H+nXoaqdxXcDmvrJ78ndv27ItPGKbd6nZny1GK+s2xg6FnlKbPvS24kPgokUmP75t7Iu7jdXuwIsK7CWXWhFHZepH4xlPiOgw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755587700; c=relaxed/simple; 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Tue, 19 Aug 2025 07:14:59 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 19 Aug 2025 12:44:51 +0530 Subject: [PATCH 2/6] PCI/pwrctrl: Move pci_pwrctrl_init() before turning ON the supplies Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-pci-pwrctrl-perst-v1-2-4b74978d2007@oss.qualcomm.com> References: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> In-Reply-To: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Saravana Kannan Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krishna Chaitanya Chundru , Brian Norris , Manivannan Sadhasivam , Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2110; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=R+1x069ihDCZtvKq09JWHM41uYbGfvNk9pQz/Px8wHE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBopCRwWISsLEKBCJ//ZxObCZSQPRynr8EU/ahBG ZI3wrnYgNSJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaKQkcAAKCRBVnxHm/pHO 9Uu/CACOo+9U0xKUKbd/DVRPzA8CPx7kVN2ETJZoSPycSzIiwn8AyUSaB/qvCNuC8VcXLm+eIik kDtSfeqY4a1C5kJCdFy2kfb+KbZwAEYjrTT6u1JZAndVIU6H/sPKT4dFiVDBu/aNfXq8YAdOynq F5RFG7R5KRCoBJeLuKdoZJ8gSHiqYD8QYP5ofRE4LGtE2lnvT19sZcA7XC9KsioDPlpYyD/znfF CwAqZ/OciBf7Ebq32/BnL+riknmV4xmE2emeC92GvU4QYbnwr/yhgjjeFgnKK41+iEhME6BEBwG VfBV0gwZ/wyJNsYo8zKMMTxy1tKMyjHuXW06fF688/ztq8Qg X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam To allow pwrctrl core to parse the generic resources such as PERST# GPIO before turning on the supplies. Reviewed-by: Bartosz Golaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c | 4 ++-- drivers/pci/pwrctrl/slot.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c b/drivers/pci/pwrctrl= /pci-pwrctrl-pwrseq.c index 4e664e7b8dd23f592c0392efbf6728fc5bf9093f..b65955adc7bd44030593e8c49d6= 0db0f39b03d03 100644 --- a/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c +++ b/drivers/pci/pwrctrl/pci-pwrctrl-pwrseq.c @@ -80,6 +80,8 @@ static int pci_pwrctrl_pwrseq_probe(struct platform_devic= e *pdev) if (!data) return -ENOMEM; =20 + pci_pwrctrl_init(&data->ctx, dev); + data->pwrseq =3D devm_pwrseq_get(dev, pdata->target); if (IS_ERR(data->pwrseq)) return dev_err_probe(dev, PTR_ERR(data->pwrseq), @@ -95,8 +97,6 @@ static int pci_pwrctrl_pwrseq_probe(struct platform_devic= e *pdev) if (ret) return ret; =20 - pci_pwrctrl_init(&data->ctx, dev); - ret =3D devm_pci_pwrctrl_device_set_ready(dev, &data->ctx); if (ret) return dev_err_probe(dev, ret, diff --git a/drivers/pci/pwrctrl/slot.c b/drivers/pci/pwrctrl/slot.c index 6e138310b45b9f7e930b6814e0a24f7111d25fee..b68406a6b027e4d9f853e86d434= 0e0ab267b6126 100644 --- a/drivers/pci/pwrctrl/slot.c +++ b/drivers/pci/pwrctrl/slot.c @@ -38,6 +38,8 @@ static int pci_pwrctrl_slot_probe(struct platform_device = *pdev) if (!slot) return -ENOMEM; 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b=Oej8+q7Q7upCxk6MKa1fOteSmMwQ3M/vCG51CRjcNPQgDvo1Z4DHhBcagO/1XmI1a EUEDA+xdR7kT0sqJn5ZNMjhmHpznMbfNC6HWMQV9dS/67gsVw0jCJeVNGVJpUVqcDs 5d/lhbon7zeONpG8JUg1BjD4rSYfz6hRtIUPP4CL0FCyFvh4oJTmFNgw5AO2q/8bkz 0GtVYGqDUVrKvU7SFN4RUyZQjUOC4m5Maayi0GC2aVeHe2Ig5ZyKp9moNFqn5ZQ4UA 4CzF6mXXt/eS4En0Nuj7qtT9EkjRc3/+oD8Ub05o0FT1kk82S3bAHcGJAFxruYnD0w ngSxjVLdU1LBg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id D431ECA0EE9; Tue, 19 Aug 2025 07:14:59 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 19 Aug 2025 12:44:52 +0530 Subject: [PATCH 3/6] PCI/pwrctrl: Add support for toggling PERST# Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-pci-pwrctrl-perst-v1-3-4b74978d2007@oss.qualcomm.com> References: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> In-Reply-To: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Saravana Kannan Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krishna Chaitanya Chundru , Brian Norris , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4162; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=Wl5F/VP41j+Wmr7pvHDX4DYYUQnHnskIua9yaeDLHHk=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBopCRwnUvKL5HtXBIOusGiiiGgtA+7zzQqxPXeO X+c98wnPJGJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaKQkcAAKCRBVnxHm/pHO 9UO0B/9lsxc/zKK0A+23UPDwqBeUsj4J1XE8hhyQ7TAOH5CHfY4SCDEpfZZJsPwNL/xfEWAXjVm z0Ulm0Zr+16hIqZcOmtDY1S367/5z8S8ZhvrLzS7cPrFXK6NBuTgD1gKqDANIf0RU/erGkLNeDt M/g/D3eU6mI3swFsZUz0tPUXmwkfmnPHG9hHM09ta0z15yyIVBd2357WDB13qJV68Sg9MIsBTGN avhjScUy5fKW5f3vVSiuNd9N1qrAFeKwcusbqrynGYWsLJ76MuEuuzeB5woOfqok0+ACPcCLeYi JZeKv+mF+lheYsZpXRJVtVmAfOlYs/a3nAdfgkLLeMfUEkmn X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam As per PCIe spec r6.0, sec 6.6.1, PERST# is an auxiliary signal provided by the system to a component as a Fundamental Reset. This signal if available, should conform to the rules defined by the electromechanical form factor specifications like PCIe CEM spec r4.0, sec 2.2. Since pwrctrl driver is meant to control the power supplies, it should also control the PERST# signal if available. But traditionally, the host bridge (controller) drivers are the ones parsing and controlling the PERST# signal. They also sometimes need to assert PERST# during their own hardware initialization. So it is not possible to move the PERST# control away from the controller drivers and it must be shared logically. Hence, add a new callback 'pci_host_bridge::toggle_perst', that allows the pwrctrl core to toggle PERST# with the help of the controller drivers. But care must be taken care by the controller drivers to not deassert the PERST# signal if this callback is populated. This callback if available, will be called by the pwrctrl core during the device power up and power down scenarios. Controller drivers should identify the device using the 'struct device_node' passed during the callback and toggle PERST# accordingly. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/pwrctrl/core.c | 27 +++++++++++++++++++++++++++ include/linux/pci.h | 1 + 2 files changed, 28 insertions(+) diff --git a/drivers/pci/pwrctrl/core.c b/drivers/pci/pwrctrl/core.c index 6bdbfed584d6d79ce28ba9e384a596b065ca69a4..8a26f432436d064acb7ebbbc9ce= 8fc339909fbe9 100644 --- a/drivers/pci/pwrctrl/core.c +++ b/drivers/pci/pwrctrl/core.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -61,6 +62,28 @@ void pci_pwrctrl_init(struct pci_pwrctrl *pwrctrl, struc= t device *dev) } EXPORT_SYMBOL_GPL(pci_pwrctrl_init); =20 +static void pci_pwrctrl_perst_deassert(struct pci_pwrctrl *pwrctrl) +{ + struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(pwrctrl->dev->= parent); + struct device_node *np =3D dev_of_node(pwrctrl->dev); + + if (!host_bridge->toggle_perst) + return; + + host_bridge->toggle_perst(host_bridge, np, false); +} + +static void pci_pwrctrl_perst_assert(struct pci_pwrctrl *pwrctrl) +{ + struct pci_host_bridge *host_bridge =3D to_pci_host_bridge(pwrctrl->dev->= parent); + struct device_node *np =3D dev_of_node(pwrctrl->dev); + + if (!host_bridge->toggle_perst) + return; + + host_bridge->toggle_perst(host_bridge, np, true); +} + /** * pci_pwrctrl_device_set_ready() - Notify the pwrctrl subsystem that the = PCI * device is powered-up and ready to be detected. @@ -82,6 +105,8 @@ int pci_pwrctrl_device_set_ready(struct pci_pwrctrl *pwr= ctrl) if (!pwrctrl->dev) return -ENODEV; =20 + pci_pwrctrl_perst_deassert(pwrctrl); + pwrctrl->nb.notifier_call =3D pci_pwrctrl_notify; ret =3D bus_register_notifier(&pci_bus_type, &pwrctrl->nb); if (ret) @@ -103,6 +128,8 @@ void pci_pwrctrl_device_unset_ready(struct pci_pwrctrl = *pwrctrl) { cancel_work_sync(&pwrctrl->work); =20 + pci_pwrctrl_perst_assert(pwrctrl); + /* * We don't have to delete the link here. Typically, this function * is only called when the power control device is being detached. If diff --git a/include/linux/pci.h b/include/linux/pci.h index 59876de13860dbe50ee6c207cd57e54f51a11079..9eeee84d550bb9f15a90b5db9da= 03fccef8097ee 100644 --- a/include/linux/pci.h +++ b/include/linux/pci.h @@ -605,6 +605,7 @@ struct pci_host_bridge { void (*release_fn)(struct pci_host_bridge *); int (*enable_device)(struct pci_host_bridge *bridge, struct pci_dev *dev); void (*disable_device)(struct pci_host_bridge *bridge, struct pci_dev *de= v); + void (*toggle_perst)(struct pci_host_bridge *bridge, struct device_node *= np, bool assert); void *release_data; unsigned int ignore_reset_delay:1; /* For entire hierarchy */ unsigned int no_ext_tags:1; /* No Extended Tags */ --=20 2.45.2 From nobody Sat Oct 4 08:08:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7515928489D; Tue, 19 Aug 2025 07:15:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-pci-pwrctrl-perst-v1-4-4b74978d2007@oss.qualcomm.com> References: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> In-Reply-To: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Saravana Kannan Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krishna Chaitanya Chundru , Brian Norris , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2221; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=lJHwEOfLqtgwNWXWNyx+rOwSYNWAA15NNEAf91PmREE=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBopCRwaIMwBz8tCj4PzD3876H5Bz2hSyktqZcTT IfMJNmljQWJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaKQkcAAKCRBVnxHm/pHO 9XL3B/9vn8nh6ovIeTV39DChlRj/smMt2t3vYSwSv23YtOBzrhXKOHIKcIUaLOzwPEn11ePfjgG r788CJqL9Jw+sSbutI6itc2N859DqFT+RPUqliN2Ow6KBwRugmPoujFXrhv2MTpY6aE1Dd8oVa3 BBTDCGHjzjRwts2w9yJ4LdI2X/y+7LkgjwMNBckqo7VvBRoG5voujF+htZRIuxLtt6G96BhQ9Xp dbFlf/iUa3rqps5klEP9mSdzBMv/0fDjjCp3hG90cJefsSOw1bfkuXlwbL3rJ8bLe38cetXvPHW 658yQDDTdMwKK99rGyWpZZBIghuVReZyVguWi85+uBBVRKt7 X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Bus:Device:Function (BDF) numbers are used to uniquely identify a device/function on a PCI bus. Hence, add an API to get the BDF from the devicetree node of a device. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/of.c | 21 +++++++++++++++++++++ include/linux/of_pci.h | 6 ++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/pci/of.c b/drivers/pci/of.c index 3579265f119845637e163d9051437c89662762f8..5e584d25434291430145e510b1d= 49a371dce9165 100644 --- a/drivers/pci/of.c +++ b/drivers/pci/of.c @@ -183,6 +183,27 @@ int of_pci_get_devfn(struct device_node *np) } EXPORT_SYMBOL_GPL(of_pci_get_devfn); =20 +/** + * of_pci_get_bdf() - Get Bus:Device:Function (BDF) numbers for a device n= ode + * @np: device node + * + * Parses a standard 5-cell PCI resource and returns an 16-bit value that + * corresponds to the BDF of the node. On error, a negative error code is + * returned. + */ +int of_pci_get_bdf(struct device_node *np) +{ + u32 reg[5]; + int error; + + error =3D of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); + if (error) + return error; + + return (reg[0] >> 8) & 0xffff; +} +EXPORT_SYMBOL_GPL(of_pci_get_bdf); + /** * of_pci_parse_bus_range() - parse the bus-range property of a PCI device * @node: device node diff --git a/include/linux/of_pci.h b/include/linux/of_pci.h index 29658c0ee71ff10122760214d04ee2bab01709fd..b36ac10653c82f4efdbb57cea56= d2ec9d581212f 100644 --- a/include/linux/of_pci.h +++ b/include/linux/of_pci.h @@ -12,6 +12,7 @@ struct device_node; struct device_node *of_pci_find_child_device(struct device_node *parent, unsigned int devfn); int of_pci_get_devfn(struct device_node *np); +int of_pci_get_bdf(struct device_node *np); void of_pci_check_probe_only(void); #else static inline struct device_node *of_pci_find_child_device(struct device_n= ode *parent, @@ -25,6 +26,11 @@ static inline int of_pci_get_devfn(struct device_node *n= p) return -EINVAL; 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Tue, 19 Aug 2025 07:14:59 +0000 (UTC) From: Manivannan Sadhasivam via B4 Relay Date: Tue, 19 Aug 2025 12:44:54 +0530 Subject: [PATCH 5/6] PCI: qcom: Parse PERST# from all PCIe bridge nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-pci-pwrctrl-perst-v1-5-4b74978d2007@oss.qualcomm.com> References: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> In-Reply-To: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Saravana Kannan Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krishna Chaitanya Chundru , Brian Norris , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6648; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=X45KjujaSGuGwn7RVLO1grKV6I/nnsAGXa9LOjUKNK4=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBopCRwLr8Oh28sKmgyljsdBYZmg4skpyMXWLtb3 +0eOsAjP/uJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaKQkcAAKCRBVnxHm/pHO 9XrnB/wNIrrhtB3mQhhPCfbhWa5mX/OB6jbAP3QteBZLDrFarfJHo/vFdgNSUXeNcFZ4ZBMB5iG ynWnDPTpxL3usiXZ8BUorQCP7JbrPSibpUxx+cabjNJA2wD3z1wmyEbVT+8G57WmQLjJc4pzlP8 c5U16newpwHiUiY5lpvX+2Wke/VUHs04ZZaNFhPTr1P5RD1mBW9Xd+wePdPgW1PXiWz+dKK3zTw BzDOqiSHYIct4LR3TuMh+Q26nmClTnDGLq/mLZ2MrE+9kBXs/r5AYbeZv+HrM0ImszlZ4II37vL WCNsgirBgNszImpwm4KQyFLuHN/ogtp+tdCdfhPwXBhh7x4V X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam Devicetree schema allows the PERST# GPIO to be present in all PCIe bridge nodes, not just in Root Port node. But the current logic parses PERST# only from the Root Port node. Though it is not causing any issue on the current platforms, the upcoming platforms will have PERST# in PCIe switch downstream ports also. So this requires parsing all the PCIe bridge nodes for the PERST# GPIO. Hence, rework the parsing logic to extend to all PCIe bridge nodes starting from Root Port node. If the 'reset-gpios' property is found for a node, the GPIO descriptor will be stored in IDR structure with node BDF as the ID. It should be noted that if more than one bridge node has the same GPIO for PERST# (shared PERST#), the driver will error out. This is due to the limitation in the GPIOLIB subsystem that allows only exclusive (non-shared) access to GPIOs from consumers. But this is soon going to get fixed. Once that happens, it will get incorporated in this driver. So for now, PERST# sharing is not supported. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 90 +++++++++++++++++++++++++++---= ---- 1 file changed, 73 insertions(+), 17 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index bcd080315d70e64eafdefd852740fe07df3dbe75..5d73c46095af3219687ff77e592= 2f08bb41e43a9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -286,6 +287,7 @@ struct qcom_pcie { const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; struct list_head ports; + struct idr perst; bool suspended; bool use_pm_opp; }; @@ -294,14 +296,15 @@ struct qcom_pcie { =20 static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert) { - struct qcom_pcie_port *port; int val =3D assert ? 1 : 0; + struct gpio_desc *perst; + int bdf; =20 - if (list_empty(&pcie->ports)) + if (idr_is_empty(&pcie->perst)) gpiod_set_value_cansleep(pcie->reset, val); - else - list_for_each_entry(port, &pcie->ports, list) - gpiod_set_value_cansleep(port->reset, val); + + idr_for_each_entry(&pcie->perst, perst, bdf) + gpiod_set_value_cansleep(perst, val); } =20 static void qcom_ep_reset_assert(struct qcom_pcie *pcie) @@ -1702,20 +1705,58 @@ static const struct pci_ecam_ops pci_qcom_ecam_ops = =3D { } }; =20 -static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node= *node) +/* Parse PERST# from all nodes in depth first manner starting from @np */ +static int qcom_pcie_parse_perst(struct qcom_pcie *pcie, + struct device_node *np) { struct device *dev =3D pcie->pci->dev; - struct qcom_pcie_port *port; struct gpio_desc *reset; - struct phy *phy; int ret; =20 - reset =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(node), - "reset", GPIOD_OUT_HIGH, "PERST#"); - if (IS_ERR(reset)) + if (!of_find_property(np, "reset-gpios", NULL)) + goto parse_child_node; + + ret =3D of_pci_get_bdf(np); + if (ret < 0) + return ret; + + reset =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(np), "reset", + GPIOD_OUT_HIGH, "PERST#"); + if (IS_ERR(reset)) { + /* + * FIXME: GPIOLIB currently supports exclusive GPIO access only. + * Non exclusive access is broken. But shared PERST# requires + * non-exclusive access. So once GPIOLIB properly supports it, + * implement it here. + */ + if (PTR_ERR(reset) =3D=3D -EBUSY) + dev_err(dev, "Shared PERST# is not supported\n"); + return PTR_ERR(reset); + } + + ret =3D idr_alloc(&pcie->perst, reset, ret, 0, GFP_KERNEL); + if (ret < 0) + return ret; + +parse_child_node: + for_each_available_child_of_node_scoped(np, child) { + ret =3D qcom_pcie_parse_perst(pcie, child); + if (ret) + return ret; + } + + return 0; +} =20 - phy =3D devm_of_phy_get(dev, node, NULL); +static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node= *np) +{ + struct device *dev =3D pcie->pci->dev; + struct qcom_pcie_port *port; + struct phy *phy; + int ret; + + phy =3D devm_of_phy_get(dev, np, NULL); if (IS_ERR(phy)) return PTR_ERR(phy); =20 @@ -1727,7 +1768,10 @@ static int qcom_pcie_parse_port(struct qcom_pcie *pc= ie, struct device_node *node if (ret) return ret; =20 - port->reset =3D reset; + ret =3D qcom_pcie_parse_perst(pcie, np); + if (ret) + return ret; + port->phy =3D phy; INIT_LIST_HEAD(&port->list); list_add_tail(&port->list, &pcie->ports); @@ -1739,7 +1783,11 @@ static int qcom_pcie_parse_ports(struct qcom_pcie *p= cie) { struct device *dev =3D pcie->pci->dev; struct qcom_pcie_port *port, *tmp; - int ret =3D -ENOENT; + struct gpio_desc *perst; + int ret =3D -ENODEV; + int bdf; + + idr_init(&pcie->perst); =20 for_each_available_child_of_node_scoped(dev->of_node, of_port) { ret =3D qcom_pcie_parse_port(pcie, of_port); @@ -1750,8 +1798,13 @@ static int qcom_pcie_parse_ports(struct qcom_pcie *p= cie) return ret; =20 err_port_del: - list_for_each_entry_safe(port, tmp, &pcie->ports, list) + list_for_each_entry_safe(port, tmp, &pcie->ports, list) { + phy_exit(port->phy); list_del(&port->list); + } + + idr_for_each_entry(&pcie->perst, perst, bdf) + idr_remove(&pcie->perst, bdf); =20 return ret; } @@ -1782,12 +1835,13 @@ static int qcom_pcie_probe(struct platform_device *= pdev) unsigned long max_freq =3D ULONG_MAX; struct qcom_pcie_port *port, *tmp; struct device *dev =3D &pdev->dev; + struct gpio_desc *perst; struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; struct resource *res; struct dw_pcie *pci; - int ret, irq; + int ret, irq, bdf; char *name; =20 pcie_cfg =3D of_device_get_match_data(dev); @@ -1927,7 +1981,7 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) =20 ret =3D qcom_pcie_parse_ports(pcie); if (ret) { - if (ret !=3D -ENOENT) { + if (ret !=3D -ENODEV) { dev_err_probe(pci->dev, ret, "Failed to parse Root Port: %d\n", ret); goto err_pm_runtime_put; @@ -1989,6 +2043,8 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) qcom_pcie_phy_exit(pcie); list_for_each_entry_safe(port, tmp, &pcie->ports, list) list_del(&port->list); + idr_for_each_entry(&pcie->perst, perst, bdf) + idr_remove(&pcie->perst, bdf); err_pm_runtime_put: pm_runtime_put(dev); pm_runtime_disable(dev); --=20 2.45.2 From nobody Sat Oct 4 08:08:45 2025 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B504728BABE; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-pci-pwrctrl-perst-v1-6-4b74978d2007@oss.qualcomm.com> References: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> In-Reply-To: <20250819-pci-pwrctrl-perst-v1-0-4b74978d2007@oss.qualcomm.com> To: Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Bartosz Golaszewski , Saravana Kannan Cc: linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krishna Chaitanya Chundru , Brian Norris , Manivannan Sadhasivam X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5088; i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id; bh=JjlBWjx38dz2g5JlkdI4+4PuduQxkQpEG3znVmGrG2Y=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBopCRxDdWesNZA/yxN84cNf1qOXfKBORwCjOlct gQI/o+3K7CJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCaKQkcQAKCRBVnxHm/pHO 9QTXB/90jcr2+9W9VPSUmZAkfoRdCixK6wAhuBmIuLVCG2afAJFoxmwpVPTxgCd0pjv7Nr2kDxZ tMbFPGRgyc42NKBVxyelgytlLzh9JgqJzRyy3pEv33CLb1h4Q8Px5Onbt8vj3GAVjHCb2r+DkcV BF84gbkwRwtmlHqiKEd9gZCpilIESTYOyaTNNxwTVzSu79jKm/ESPp2Npa1YtrNQUQyKH3hDEVl IqTXYYZMTXxWRG6OIjHvy26vWa7GPcINvMzeHvWSf5y2a2EyceQabRPu4asCw72X56ZbHPM1y1H 115eWkr454kW7fYuVJmDUh1ZijPu/2o7ERx40NrVzq5Wel0K X-Developer-Key: i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Endpoint-Received: by B4 Relay for manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461 X-Original-From: Manivannan Sadhasivam Reply-To: manivannan.sadhasivam@oss.qualcomm.com From: Manivannan Sadhasivam If the platform is using the new DT binding, let the pwrctrl core toggle PERST# for the device. This is achieved by populating the 'pci_host_bridge::toggle_perst' callback with qcom_pcie_toggle_perst(). qcom_pcie_toggle_perst() will find the PERST# GPIO descriptor associated with the supplied 'device_node' and toggle PERST#. If PERST# is not found in the supplied node, the function will look for PERST# in the parent node as a fallback. This is needed since PERST# won't be available in the endpoint node as per the DT binding. Note that the driver still asserts PERST# during the controller initialization as it is needed as per the hardware documentation. Apart from that, the driver wouldn't touch PERST# for the new binding. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 70 +++++++++++++++++++++++++++++-= ---- 1 file changed, 61 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 5d73c46095af3219687ff77e5922f08bb41e43a9..fd07cd493f9fb974acfc924778c= 7a5e980630ae6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -294,12 +294,44 @@ struct qcom_pcie { =20 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) =20 -static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert) +static void qcom_toggle_perst_per_device(struct qcom_pcie *pcie, + struct device_node *np, int val) +{ + struct gpio_desc *perst; + int bdf; + + bdf =3D of_pci_get_bdf(np); + if (bdf < 0) + return; + + perst =3D idr_find(&pcie->perst, bdf); + if (perst) + goto toggle_perst; + + /* + * If PERST# is not available in the current node, try the parent. This + * fallback is needed if the current node belongs to an endpoint. + */ + bdf =3D of_pci_get_bdf(np->parent); + if (bdf < 0) + return; + + perst =3D idr_find(&pcie->perst, bdf); +toggle_perst: + /* gpiod* APIs handle NULL gpio_desc gracefully. So no need to check. */ + gpiod_set_value_cansleep(perst, val); +} + +static void qcom_perst_assert(struct qcom_pcie *pcie, struct device_node *= np, + bool assert) { int val =3D assert ? 1 : 0; struct gpio_desc *perst; int bdf; =20 + if (np) + return qcom_toggle_perst_per_device(pcie, np, val); + if (idr_is_empty(&pcie->perst)) gpiod_set_value_cansleep(pcie->reset, val); =20 @@ -307,22 +339,34 @@ static void qcom_perst_assert(struct qcom_pcie *pcie,= bool assert) gpiod_set_value_cansleep(perst, val); } =20 -static void qcom_ep_reset_assert(struct qcom_pcie *pcie) +static void qcom_ep_reset_assert(struct qcom_pcie *pcie, struct device_nod= e *np) { - qcom_perst_assert(pcie, true); + qcom_perst_assert(pcie, np, true); usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 -static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) +static void qcom_ep_reset_deassert(struct qcom_pcie *pcie, + struct device_node *np) { struct dw_pcie_rp *pp =3D &pcie->pci->pp; =20 msleep(PCIE_T_PVPERL_MS); - qcom_perst_assert(pcie, false); + qcom_perst_assert(pcie, np, false); if (!pp->use_linkup_irq) msleep(PCIE_RESET_CONFIG_WAIT_MS); } =20 +static void qcom_pcie_toggle_perst(struct pci_host_bridge *bridge, + struct device_node *np, bool assert) +{ + struct qcom_pcie *pcie =3D dev_get_drvdata(bridge->dev.parent); + + if (assert) + qcom_ep_reset_assert(pcie, np); + else + qcom_ep_reset_deassert(pcie, np); +} + static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie =3D to_qcom_pcie(pci); @@ -1317,7 +1361,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) struct qcom_pcie *pcie =3D to_qcom_pcie(pci); int ret; =20 - qcom_ep_reset_assert(pcie); + qcom_ep_reset_assert(pcie, NULL); =20 ret =3D pcie->cfg->ops->init(pcie); if (ret) @@ -1333,7 +1377,13 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) goto err_disable_phy; } =20 - qcom_ep_reset_deassert(pcie); + /* + * Only deassert PERST# for all devices here if legacy binding is used. + * For the new binding, pwrctrl driver is expected to toggle PERST# for + * individual devices. + */ + if (idr_is_empty(&pcie->perst)) + qcom_ep_reset_deassert(pcie, NULL); =20 if (pcie->cfg->ops->config_sid) { ret =3D pcie->cfg->ops->config_sid(pcie); @@ -1341,10 +1391,12 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *p= p) goto err_assert_reset; } =20 + pci->pp.bridge->toggle_perst =3D qcom_pcie_toggle_perst; + return 0; =20 err_assert_reset: - qcom_ep_reset_assert(pcie); + qcom_ep_reset_assert(pcie, NULL); err_disable_phy: qcom_pcie_phy_power_off(pcie); err_deinit: @@ -1358,7 +1410,7 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *= pp) struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct qcom_pcie *pcie =3D to_qcom_pcie(pci); =20 - qcom_ep_reset_assert(pcie); + qcom_ep_reset_assert(pcie, NULL); qcom_pcie_phy_power_off(pcie); pcie->cfg->ops->deinit(pcie); } --=20 2.45.2