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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3237e3eef8fsm2499643a91.18.2025.08.19.03.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 19 Aug 2025 03:27:54 -0700 (PDT) From: Yuanfang Zhang Date: Tue, 19 Aug 2025 03:27:44 -0700 Subject: [PATCH v2 2/3] coresight-tnoc: add platform driver to support Interconnect TNOC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250819-itnoc-v2-2-2d0e6be44e2f@oss.qualcomm.com> References: <20250819-itnoc-v2-0-2d0e6be44e2f@oss.qualcomm.com> In-Reply-To: <20250819-itnoc-v2-0-2d0e6be44e2f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alexander Shishkin Cc: kernel@oss.qualcomm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Yuanfang Zhang X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1755599271; l=7467; i=yuanfang.zhang@oss.qualcomm.com; s=20250814; h=from:subject:message-id; bh=XO9D6AwhUNAnacAZyuMr3vcbzQlze7wwXSgBjm1UkaA=; b=ZlUiRoSRBBukIvPcZLBxJbhHLQf6Cy8WzWkVJGbcJBK/MhJvZpBxH4ihhyf9kUzrx3zgA7Nj/ NV/v1ngkFWWApBZBipPi8XEIi33vZmbmYYirK25LZdBVXVv4eJQZjU0 X-Developer-Key: i=yuanfang.zhang@oss.qualcomm.com; a=ed25519; pk=9oS/FoPW5k0CsqSDDrPlnV+kVIOUaAe0O5pr4M1wHgY= X-Proofpoint-ORIG-GUID: 5cbJovMzPtCPWRS86pMFdinTMGmg6JJl X-Proofpoint-GUID: 5cbJovMzPtCPWRS86pMFdinTMGmg6JJl X-Authority-Analysis: v=2.4 cv=IvQecK/g c=1 sm=1 tr=0 ts=68a451ac cx=c_pps a=oF/VQ+ItUULfLr/lQ2/icg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=vZzgk5nmo-DiXalhxAsA:9 a=QEXdDO2ut3YA:10 a=3WC7DwWrALyhR5TkjVHa:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODE4MDE0NyBTYWx0ZWRfX+UGUuKJ2em9x Buu8zPJqgLAgFI8ESk4D+yxjQikBl3DxyRtwx0M1bqYzSFs1oBhthT/N9izO2fMIo8z2ZjnFwpw PNbyM++txngCbVsTIpDwhc8pcIsjgELJDcmqh5aBisMbarhObfNIkTFW6rmhoSo0o2bBEOiMmNL mqmHwafhU4OoR9tBLumsOMyK9lvIfkQ1nhVzHfNC38U0YleMPc5+gnINedr9TdPkT3OYHSlU/LE gbCffE6TZNpySruWfzX/Q8WotTYaOgTsh0BBOWkvhko+JFS9Ftr5Gx26qn93TbBPKCU3wRRn4qc /ddkwDEpQOOQwnCbx29iPDStrXiZSBnzzCYuaVUCahLCT2AGJIRb/7NxYBn5EXnbPh/MF5QvWaS JrK2H4vz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 phishscore=0 bulkscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508180147 This patch adds platform driver support for the CoreSight Interconnect TNOC, Interconnect TNOC is a CoreSight link that forwards trace data from a subsystem to the Aggregator TNOC. Compared to Aggregator TNOC, it does not have aggregation and ATID functionality. Key changes: - Add platform driver `coresight-itnoc` with device tree match support. - Refactor probe logic into a common `_tnoc_probe()` function. - Conditionally initialize ATID only for AMBA-based TNOC blocks. Signed-off-by: Yuanfang Zhang --- drivers/hwtracing/coresight/coresight-tnoc.c | 124 +++++++++++++++++++++++= ---- 1 file changed, 107 insertions(+), 17 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-tnoc.c b/drivers/hwtraci= ng/coresight/coresight-tnoc.c index d542df46ea39314605290311f683010337bfd4bd..407595e893096d8011dfcefd74c= ca742d9b96695 100644 --- a/drivers/hwtracing/coresight/coresight-tnoc.c +++ b/drivers/hwtracing/coresight/coresight-tnoc.c @@ -34,6 +34,7 @@ * @base: memory mapped base address for this component. * @dev: device node for trace_noc_drvdata. * @csdev: component vitals needed by the framework. + * @pclk: APB clock if present, otherwise NULL * @spinlock: serialize enable/disable operation. * @atid: id for the trace packet. */ @@ -41,8 +42,9 @@ struct trace_noc_drvdata { void __iomem *base; struct device *dev; struct coresight_device *csdev; + struct clk *pclk; spinlock_t spinlock; - u32 atid; + int atid; }; =20 DEFINE_CORESIGHT_DEVLIST(trace_noc_devs, "traceNoc"); @@ -51,25 +53,30 @@ static void trace_noc_enable_hw(struct trace_noc_drvdat= a *drvdata) { u32 val; =20 + /* No valid ATID, simply enable the unit */ + if (drvdata->atid =3D=3D -EOPNOTSUPP) { + writel(TRACE_NOC_CTRL_PORTEN, drvdata->base + TRACE_NOC_CTRL); + return; + } + /* Set ATID */ writel_relaxed(drvdata->atid, drvdata->base + TRACE_NOC_XLD); =20 /* Set the data word count between 'SYNC' packets */ writel_relaxed(TRACE_NOC_SYNC_INTERVAL, drvdata->base + TRACE_NOC_SYNCR); - /* Set the Control register: - * - Set the FLAG packets to 'FLAG' packets - * - Set the FREQ packets to 'FREQ_TS' packets - * - Enable generation of output ATB traffic - */ + * - Set the FLAG packets to 'FLAG' packets + * - Set the FREQ packets to 'FREQ_TS' packets + * - Enable generation of output ATB traffic + */ =20 val =3D readl_relaxed(drvdata->base + TRACE_NOC_CTRL); =20 val &=3D ~TRACE_NOC_CTRL_FLAGTYPE; val |=3D TRACE_NOC_CTRL_FREQTYPE; val |=3D TRACE_NOC_CTRL_PORTEN; - writel(val, drvdata->base + TRACE_NOC_CTRL); + } =20 static int trace_noc_enable(struct coresight_device *csdev, struct coresig= ht_connection *inport, @@ -124,6 +131,11 @@ static int trace_noc_init_default_data(struct trace_no= c_drvdata *drvdata) { int atid; =20 + if (!dev_is_amba(drvdata->dev)) { + drvdata->atid =3D -EOPNOTSUPP; + return 0; + } + atid =3D coresight_trace_id_get_system_id(); if (atid < 0) return atid; @@ -149,8 +161,21 @@ static struct attribute *coresight_tnoc_attrs[] =3D { NULL, }; =20 +static umode_t trace_id_is_visible(struct kobject *kobj, + struct attribute *attr, int idx) +{ + struct device *dev =3D kobj_to_dev(kobj); + struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(dev->parent); + + if (attr =3D=3D &dev_attr_traceid.attr && drvdata->atid < 0) + return 0; + + return attr->mode; +} + static const struct attribute_group coresight_tnoc_group =3D { .attrs =3D coresight_tnoc_attrs, + .is_visible =3D trace_id_is_visible, }; =20 static const struct attribute_group *coresight_tnoc_groups[] =3D { @@ -158,9 +183,8 @@ static const struct attribute_group *coresight_tnoc_gro= ups[] =3D { NULL, }; =20 -static int trace_noc_probe(struct amba_device *adev, const struct amba_id = *id) +static int _tnoc_probe(struct device *dev, struct resource *res) { - struct device *dev =3D &adev->dev; struct coresight_platform_data *pdata; struct trace_noc_drvdata *drvdata; struct coresight_desc desc =3D { 0 }; @@ -173,16 +197,20 @@ static int trace_noc_probe(struct amba_device *adev, = const struct amba_id *id) pdata =3D coresight_get_platform_data(dev); if (IS_ERR(pdata)) return PTR_ERR(pdata); - adev->dev.platform_data =3D pdata; + dev->platform_data =3D pdata; =20 drvdata =3D devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; =20 - drvdata->dev =3D &adev->dev; + drvdata->dev =3D dev; dev_set_drvdata(dev, drvdata); =20 - drvdata->base =3D devm_ioremap_resource(dev, &adev->res); + ret =3D coresight_get_enable_clocks(dev, &drvdata->pclk, NULL); + if (ret) + return ret; + + drvdata->base =3D devm_ioremap_resource(dev, res); if (IS_ERR(drvdata->base)) return PTR_ERR(drvdata->base); =20 @@ -195,20 +223,31 @@ static int trace_noc_probe(struct amba_device *adev, = const struct amba_id *id) desc.ops =3D &trace_noc_cs_ops; desc.type =3D CORESIGHT_DEV_TYPE_LINK; desc.subtype.link_subtype =3D CORESIGHT_DEV_SUBTYPE_LINK_MERG; - desc.pdata =3D adev->dev.platform_data; - desc.dev =3D &adev->dev; + desc.pdata =3D pdata; + desc.dev =3D dev; desc.access =3D CSDEV_ACCESS_IOMEM(drvdata->base); desc.groups =3D coresight_tnoc_groups; drvdata->csdev =3D coresight_register(&desc); if (IS_ERR(drvdata->csdev)) { - coresight_trace_id_put_system_id(drvdata->atid); + if (drvdata->atid > 0) + coresight_trace_id_put_system_id(drvdata->atid); return PTR_ERR(drvdata->csdev); } - pm_runtime_put(&adev->dev); =20 return 0; } =20 +static int trace_noc_probe(struct amba_device *adev, const struct amba_id = *id) +{ + int ret; + + ret =3D _tnoc_probe(&adev->dev, &adev->res); + if (!ret) + pm_runtime_put(&adev->dev); + + return ret; +} + static void trace_noc_remove(struct amba_device *adev) { struct trace_noc_drvdata *drvdata =3D dev_get_drvdata(&adev->dev); @@ -236,7 +275,58 @@ static struct amba_driver trace_noc_driver =3D { .id_table =3D trace_noc_ids, }; =20 -module_amba_driver(trace_noc_driver); +static int itnoc_probe(struct platform_device *pdev) +{ + struct resource *res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + int ret; + + pm_runtime_get_noresume(&pdev->dev); + pm_runtime_set_active(&pdev->dev); + pm_runtime_enable(&pdev->dev); + + ret =3D _tnoc_probe(&pdev->dev, res); + pm_runtime_put(&pdev->dev); + if (ret) + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static void itnoc_remove(struct platform_device *pdev) +{ + struct trace_noc_drvdata *drvdata =3D platform_get_drvdata(pdev); + + coresight_unregister(drvdata->csdev); + pm_runtime_disable(&pdev->dev); +} + +static const struct of_device_id itnoc_of_match[] =3D { + { .compatible =3D "qcom,coresight-itnoc" }, + {} +}; +MODULE_DEVICE_TABLE(of, itnoc_of_match); + +static struct platform_driver itnoc_driver =3D { + .probe =3D itnoc_probe, + .remove =3D itnoc_remove, + .driver =3D { + .name =3D "coresight-itnoc", + .of_match_table =3D itnoc_of_match, + .suppress_bind_attrs =3D true, + }, +}; + +static int __init tnoc_init(void) +{ + return coresight_init_driver("tnoc", &trace_noc_driver, &itnoc_driver, TH= IS_MODULE); +} + +static void __exit tnoc_exit(void) +{ + coresight_remove_driver(&trace_noc_driver, &itnoc_driver); +} +module_init(tnoc_init); +module_exit(tnoc_exit); =20 MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("Trace NOC driver"); --=20 2.34.1