From nobody Sat Oct 4 09:37:59 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F2DF3218AA; Tue, 19 Aug 2025 09:18:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755595140; cv=none; b=SSi61z4wSW//oBB92cm9rpAzLWCXgSuaIUO3G13jAXdTQ8I3GM7U1N3XjSGxgyxJAJvj9wru9hEqyBmzs7QGDP/u7EFBqQMks2Bu0Y7Brob3zzJ2HvuqJvNvl6+u5QVIdPu40fYo0xj4BUNATC9VMWjGXG6uvbRLQDaN6hNFO9I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755595140; c=relaxed/simple; bh=lELGDk8zkI3p8IQ+7F0qgEF9S/W0PW8aUey1Z3i8lVg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=Bahp1nB6YJEWo8PFeC5AbJ48nVLdMIKA9BufaLwJkuZ/PC1yHU31QD9AcxdKbx92j+hqhsR0ESHe6vKXYRx2RrFULZMXYefVSpb4NJbC5Px76O0DmAn4rbGHdDpA6ShqkvnX30akn6u3LrgrhnVYJ0coaf5AOaEo+aAb6mvxIjo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=AzJiCTMS; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="AzJiCTMS" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J8v5JQ021413; Tue, 19 Aug 2025 11:18:30 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= bsmf5bLEhDcMHd8HjlloeMrrkwwKS55Kw0bi6W7zyHI=; b=AzJiCTMS8u4qIiBq hF3AIkT4qualZwLrP7MXbRhbq/spspDkEVS5XnHdNHQxPsLFtWRMGnIwmrHAMNnX WuPW9H2+xolEuZowgEaZYzQDkrc6bQV2ksE88Tdgc17h8aCTYwaKvN0OtC5+bAbw /CvFCDw3JmTJGyxYOIlhdNAnIWa/P1/hawUR8JTtqLfECllOVKzYugJ9sJkigKMx B5XZu0qjXMJVAH7S4vJoy9DwSTubxWKGJwHLvn+LrA1/9tU/q/jaN7EPmd8a5cl4 BJZy1fjpwQ4w961I+Ro6/yGXC0G6yr7jVgCgBKSpnaTt/p0AiplWaDsh62YDxGU1 grsKkA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48jfdkahpr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Aug 2025 11:18:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EFB6740052; Tue, 19 Aug 2025 11:16:57 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3CA8A71CDAB; Tue, 19 Aug 2025 11:16:01 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:16:00 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:16:00 +0200 Subject: [PATCH v3 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-7-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 From: Yannick Fertre STM32MP25 SoC features a new version of the LTDC IP. Add its compatible to the list of device to probe and implement its quirks. This hardware supports a pad frequency of 150MHz and a peripheral bus clock. Signed-off-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/drv.c | 11 ++++++++++- drivers/gpu/drm/stm/ltdc.c | 37 ++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/stm/ltdc.h | 5 +++++ 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c index 8ebcaf953782d806a738d5a41ff1f428b0ccff78..8bfdeb486862a95df77427d25ce= 373e69e886c01 100644 --- a/drivers/gpu/drm/stm/drv.c +++ b/drivers/gpu/drm/stm/drv.c @@ -236,8 +236,17 @@ static void stm_drm_platform_shutdown(struct platform_= device *pdev) drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); } =20 +static struct ltdc_plat_data stm_drm_plat_data =3D { + .pad_max_freq_hz =3D 90000000, +}; + +static struct ltdc_plat_data stm_drm_plat_data_mp25 =3D { + .pad_max_freq_hz =3D 150000000, +}; + static const struct of_device_id drv_dt_ids[] =3D { - { .compatible =3D "st,stm32-ltdc"}, + { .compatible =3D "st,stm32-ltdc", .data =3D &stm_drm_plat_data, }, + { .compatible =3D "st,stm32mp251-ltdc", .data =3D &stm_drm_plat_data_mp25= , }, { /* end node */ }, }; MODULE_DEVICE_TABLE(of, drv_dt_ids); diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index ba315c66a04d72758b9d3cfcd842432877f66d3a..74e93f076b62a46e7835985d9d3= 30ba66d990e58 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,7 @@ #define HWVER_10300 0x010300 #define HWVER_20101 0x020101 #define HWVER_40100 0x040100 +#define HWVER_40101 0x040101 =20 /* * The address of some registers depends on the HW version: such registers= have @@ -1779,6 +1781,7 @@ static int ltdc_get_caps(struct drm_device *ddev) { struct ltdc_device *ldev =3D ddev->dev_private; u32 bus_width_log2, lcr, gc2r; + const struct ltdc_plat_data *pdata =3D of_device_get_match_data(ddev->dev= ); =20 /* * at least 1 layer must be managed & the number of layers @@ -1794,6 +1797,8 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.bus_width =3D 8 << bus_width_log2; regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); =20 + ldev->caps.pad_max_freq_hz =3D pdata->pad_max_freq_hz; + switch (ldev->caps.hw_version) { case HWVER_10200: case HWVER_10300: @@ -1811,7 +1816,6 @@ static int ltdc_get_caps(struct drm_device *ddev) * does not work on 2nd layer. */ ldev->caps.non_alpha_only_l1 =3D true; - ldev->caps.pad_max_freq_hz =3D 90000000; if (ldev->caps.hw_version =3D=3D HWVER_10200) ldev->caps.pad_max_freq_hz =3D 65000000; ldev->caps.nb_irq =3D 2; @@ -1842,6 +1846,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.fifo_threshold =3D false; break; case HWVER_40100: + case HWVER_40101: ldev->caps.layer_ofs =3D LAY_OFS_1; ldev->caps.layer_regs =3D ltdc_layer_regs_a2; ldev->caps.pix_fmt_hw =3D ltdc_pix_fmt_a2; @@ -1849,7 +1854,6 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.pix_fmt_nb =3D ARRAY_SIZE(ltdc_drm_fmt_a2); ldev->caps.pix_fmt_flex =3D true; ldev->caps.non_alpha_only_l1 =3D false; - ldev->caps.pad_max_freq_hz =3D 90000000; ldev->caps.nb_irq =3D 2; ldev->caps.ycbcr_input =3D true; ldev->caps.ycbcr_output =3D true; @@ -1872,6 +1876,8 @@ void ltdc_suspend(struct drm_device *ddev) =20 DRM_DEBUG_DRIVER("\n"); clk_disable_unprepare(ldev->pixel_clk); + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1887,7 +1893,13 @@ int ltdc_resume(struct drm_device *ddev) return ret; } =20 - return 0; + if (ldev->bus_clk) { + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) + drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + } + + return ret; } =20 int ltdc_load(struct drm_device *ddev) @@ -1922,6 +1934,19 @@ int ltdc_load(struct drm_device *ddev) return -ENODEV; } =20 + if (of_device_is_compatible(np, "st,stm32mp251-ltdc")) { + ldev->bus_clk =3D devm_clk_get(dev, "bus"); + if (IS_ERR(ldev->bus_clk)) + return dev_err_probe(dev, PTR_ERR(ldev->bus_clk), + "Unable to get bus clock\n"); + + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) { + drm_err(ddev, "Unable to prepare bus clock\n"); + return ret; + } + } + /* Get endpoints if any */ for (i =3D 0; i < nb_endpoints; i++) { ret =3D drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); @@ -2034,6 +2059,9 @@ int ltdc_load(struct drm_device *ddev) =20 clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + pinctrl_pm_select_sleep_state(ddev->dev); =20 pm_runtime_enable(ddev->dev); @@ -2042,6 +2070,9 @@ int ltdc_load(struct drm_device *ddev) err: clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + return ret; } =20 diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 9d488043ffdbc652deeede71c9d57d45fb89d3c6..ddfa8ae61a7ba5dc446fae64756= 2d0ec8e6953e1 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -40,10 +40,15 @@ struct fps_info { ktime_t last_timestamp; }; =20 +struct ltdc_plat_data { + int pad_max_freq_hz; /* max frequency supported by pad */ +}; + struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; /* lcd pixel clock */ + struct clk *bus_clk; /* bus clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps; u32 irq_status; --=20 2.25.1