From nobody Sat Oct 4 08:03:01 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C590930FF3C; Tue, 19 Aug 2025 09:18:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755595117; cv=none; b=ibc3ZQ9T1/vy8YbPQEddyAAhb4tGOOCMGzrdJz86C/r1YEU9rndVLN7qnm+cxPihDV9t+CNDcKbLBBHuNvBMdKKyXxCRdPMQ5SBph9JbK51+DlgnK0C1zAZcbTJosLdU5cX0nRQf1wBrIw3teMOWXtGABLyz2grKJ1NcShMndbU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755595117; c=relaxed/simple; bh=erShA+dZ5Jjs2GnR1PbSrWlzg0dzUsLPa7yJEGCgZHg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=GGzVIh3cet87cmkC3cQ5+BHNZjXa8Mo3movSFHqFL+V6NWi0hvRyPJzgPAUousUN6ukBgBp1mJXmYhtG1z9z2NuKL2QGzWHoMkv9aeAZRB/E5VKc9W4Ici5jVzEwArmf3Q9v7UC4J1Ep/Bf3+erdE1jxnVjW/H5i6O0Cb5bjsH0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=BtphlpWT; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="BtphlpWT" Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57J8EMBC028895; Tue, 19 Aug 2025 11:18:16 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= wTq02ZA/awCyjRcLAWcCoPCehHYtltr818J8SinY8Pc=; b=BtphlpWTIqurFYuE r/HQPKUMyhv+IafnaMiFfH1aPL8oqtnYvx/GJJI2QbdgE1ZjMaeNy0huX6cvH2pk 5W9F6Px7Mlj7u4aDevfQvSzf5udOMCzAwzoJ66msHP/ZKW18wfqy3iwHgp4RrMIG mNXBBkiEda+J3adORCDED5xEdUHzRq8DbYzX5l8Lzh7DJHLN393/IiTXts7fdu8X NA2KcT7MGbIeDWV1bJ2y4gVCmT2jX1Ymf6y/TmVQgRwUhU+aglt0jHZPur7X+W+q RpNtNT5DkLjdz+onEK7mnDDMu/Y2Bq2Hdeb1WgbkTQCLza5d38R2F62TLX3Uw7Vs Vl08AA== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 48jf47t0d5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 19 Aug 2025 11:18:16 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6B9E64004F; Tue, 19 Aug 2025 11:16:54 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 6BD9571764B; Tue, 19 Aug 2025 11:15:57 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:15:57 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:15:54 +0200 Subject: [PATCH v3 01/13] dt-bindings: display: st: add new compatible to LTDC device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-1-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 The new STMicroelectronics SoC features a display controller similar to the one used in previous SoCs. Because there is additional registers, it is incompatible with existing IPs. Add the new name to the list of compatible string. Signed-off-by: Raphael Gallais-Pou Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/display/st,stm32-ltdc.yaml | 30 ++++++++++++++++++= ++-- 1 file changed, 28 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b= /Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index d6ea4d62a2cfae26353c9f20a326a4329fed3a2f..4a227799717637df882170ec08c= 0a8e88ac430ab 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -12,7 +12,9 @@ maintainers: =20 properties: compatible: - const: st,stm32-ltdc + enum: + - st,stm32-ltdc + - st,stm32mp251-ltdc =20 reg: maxItems: 1 @@ -24,11 +26,16 @@ properties: minItems: 1 =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 =20 clock-names: items: - const: lcd + - const: bus + - const: ref + - const: lvds + minItems: 1 =20 resets: maxItems: 1 @@ -51,6 +58,25 @@ required: - resets - port =20 +if: + properties: + compatible: + contains: + enum: + - st,stm32-ltdc +then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 +else: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + additionalProperties: false =20 examples: --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E83A031B135; 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Tue, 19 Aug 2025 11:18:15 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6B8544004D; Tue, 19 Aug 2025 11:16:54 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 0EC1F71764D; Tue, 19 Aug 2025 11:15:58 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:15:57 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:15:55 +0200 Subject: [PATCH v3 02/13] dt-bindings: display: st,stm32-ltdc: add access-controllers property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-2-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b= /Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index 4a227799717637df882170ec08c0a8e88ac430ab..d432983a8b20b6e482b411ad025= 4884d92848d8c 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -40,6 +40,9 @@ properties: resets: maxItems: 1 =20 + access-controllers: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port description: | --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DECCA31984A; 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Tue, 19 Aug 2025 11:18:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 61FEF40054; Tue, 19 Aug 2025 11:16:58 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id A78BB717636; Tue, 19 Aug 2025 11:15:58 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:15:58 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:15:56 +0200 Subject: [PATCH v3 03/13] dt-bindings: display: st: add new compatible to LVDS device Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-3-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , , Krzysztof Kozlowski X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 Update the compatible to accept both "st,stm32mp255-lvds" and st,stm32mp25-lvds" respectively. Default will fall back to "st,stm32mp25-lvds". Acked-by: Krzysztof Kozlowski Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 7 +++++= +- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 6736f93256b5cebb558cda5250369ec4b1b3033c..74e61d95370c299130410cdaae8= 33514324c3e8f 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -31,7 +31,12 @@ description: | =20 properties: compatible: - const: st,stm32mp25-lvds + oneOf: + - items: + - enum: + - st,stm32mp255-lvds + - const: st,stm32mp25-lvds + - const: st,stm32mp25-lvds =20 "#clock-cells": const: 0 --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C589126D4EF; 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Tue, 19 Aug 2025 11:18:16 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 6B7CD4004C; Tue, 19 Aug 2025 11:16:54 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5869D71765C; Tue, 19 Aug 2025 11:15:59 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:15:59 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:15:57 +0200 Subject: [PATCH v3 04/13] dt-bindings: display: st,stm32mp25-lvds: add access-controllers property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-4-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 access-controllers is an optional property that allows a peripheral to refer to one or more domain access controller(s). This property is added when the peripheral is under the STM32 firewall controller. It allows an accurate representation of the hardware, where the peripheral is connected to a firewall bus. The firewall can then check the peripheral accesses before allowing its device to probe. Acked-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 74e61d95370c299130410cdaae833514324c3e8f..05a73bbc246a8994b6aabf7c2cd= 9dca773232be4 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -59,6 +59,9 @@ properties: resets: maxItems: 1 =20 + access-controllers: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A0C9C321455; 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Tue, 19 Aug 2025 11:18:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id AC42540051; Tue, 19 Aug 2025 11:16:57 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EF1CC717657; Tue, 19 Aug 2025 11:15:59 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:15:59 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:15:58 +0200 Subject: [PATCH v3 05/13] dt-bindings: display: st,stm32mp25-lvds: add power-domains property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-5-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 STM32 LVDS peripheral may be in a power domain. Allow an optional single 'power-domains' entry for STM32 LVDS devices. Acked-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.ya= ml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 05a73bbc246a8994b6aabf7c2cd9dca773232be4..14e042156179cb2f2d906422eaf= f6840da3c91ea 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -62,6 +62,9 @@ properties: access-controllers: maxItems: 1 =20 + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports =20 --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F24B31A061; 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Tue, 19 Aug 2025 11:18:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 5584F40053; Tue, 19 Aug 2025 11:16:58 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 98F3371763B; Tue, 19 Aug 2025 11:16:00 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:16:00 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:15:59 +0200 Subject: [PATCH v3 06/13] dt-bindings: arm: stm32: add required #clock-cells property Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-6-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 On STM32MP25 SoC, the syscfg peripheral provides a clock to the display subsystem through a multiplexer. Since it only provides a single clock, the cell value is 0. Doing so allows the clock consumers to reach the peripheral and gate the clock accordingly. Reviewed-by: Rob Herring (Arm) Signed-off-by: Raphael Gallais-Pou --- .../bindings/arm/stm32/st,stm32-syscon.yaml | 31 +++++++++++++++---= ---- 1 file changed, 21 insertions(+), 10 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.ya= ml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c84922813e94b1818c07fe8714891c089..95d2319afe235fa86974d80f89c= 9deeae2275232 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 =20 + "#clock-cells": + const: 0 + required: - compatible - reg =20 -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" =20 additionalProperties: false =20 --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F2DF3218AA; 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Tue, 19 Aug 2025 11:18:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id EFB6740052; Tue, 19 Aug 2025 11:16:57 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 3CA8A71CDAB; Tue, 19 Aug 2025 11:16:01 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:16:00 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:16:00 +0200 Subject: [PATCH v3 07/13] drm/stm: ltdc: support new hardware version for STM32MP25 SoC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-7-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 From: Yannick Fertre STM32MP25 SoC features a new version of the LTDC IP. Add its compatible to the list of device to probe and implement its quirks. This hardware supports a pad frequency of 150MHz and a peripheral bus clock. Signed-off-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/drv.c | 11 ++++++++++- drivers/gpu/drm/stm/ltdc.c | 37 ++++++++++++++++++++++++++++++++++--- drivers/gpu/drm/stm/ltdc.h | 5 +++++ 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c index 8ebcaf953782d806a738d5a41ff1f428b0ccff78..8bfdeb486862a95df77427d25ce= 373e69e886c01 100644 --- a/drivers/gpu/drm/stm/drv.c +++ b/drivers/gpu/drm/stm/drv.c @@ -236,8 +236,17 @@ static void stm_drm_platform_shutdown(struct platform_= device *pdev) drm_atomic_helper_shutdown(platform_get_drvdata(pdev)); } =20 +static struct ltdc_plat_data stm_drm_plat_data =3D { + .pad_max_freq_hz =3D 90000000, +}; + +static struct ltdc_plat_data stm_drm_plat_data_mp25 =3D { + .pad_max_freq_hz =3D 150000000, +}; + static const struct of_device_id drv_dt_ids[] =3D { - { .compatible =3D "st,stm32-ltdc"}, + { .compatible =3D "st,stm32-ltdc", .data =3D &stm_drm_plat_data, }, + { .compatible =3D "st,stm32mp251-ltdc", .data =3D &stm_drm_plat_data_mp25= , }, { /* end node */ }, }; MODULE_DEVICE_TABLE(of, drv_dt_ids); diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index ba315c66a04d72758b9d3cfcd842432877f66d3a..74e93f076b62a46e7835985d9d3= 30ba66d990e58 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -51,6 +52,7 @@ #define HWVER_10300 0x010300 #define HWVER_20101 0x020101 #define HWVER_40100 0x040100 +#define HWVER_40101 0x040101 =20 /* * The address of some registers depends on the HW version: such registers= have @@ -1779,6 +1781,7 @@ static int ltdc_get_caps(struct drm_device *ddev) { struct ltdc_device *ldev =3D ddev->dev_private; u32 bus_width_log2, lcr, gc2r; + const struct ltdc_plat_data *pdata =3D of_device_get_match_data(ddev->dev= ); =20 /* * at least 1 layer must be managed & the number of layers @@ -1794,6 +1797,8 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.bus_width =3D 8 << bus_width_log2; regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); =20 + ldev->caps.pad_max_freq_hz =3D pdata->pad_max_freq_hz; + switch (ldev->caps.hw_version) { case HWVER_10200: case HWVER_10300: @@ -1811,7 +1816,6 @@ static int ltdc_get_caps(struct drm_device *ddev) * does not work on 2nd layer. */ ldev->caps.non_alpha_only_l1 =3D true; - ldev->caps.pad_max_freq_hz =3D 90000000; if (ldev->caps.hw_version =3D=3D HWVER_10200) ldev->caps.pad_max_freq_hz =3D 65000000; ldev->caps.nb_irq =3D 2; @@ -1842,6 +1846,7 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.fifo_threshold =3D false; break; case HWVER_40100: + case HWVER_40101: ldev->caps.layer_ofs =3D LAY_OFS_1; ldev->caps.layer_regs =3D ltdc_layer_regs_a2; ldev->caps.pix_fmt_hw =3D ltdc_pix_fmt_a2; @@ -1849,7 +1854,6 @@ static int ltdc_get_caps(struct drm_device *ddev) ldev->caps.pix_fmt_nb =3D ARRAY_SIZE(ltdc_drm_fmt_a2); ldev->caps.pix_fmt_flex =3D true; ldev->caps.non_alpha_only_l1 =3D false; - ldev->caps.pad_max_freq_hz =3D 90000000; ldev->caps.nb_irq =3D 2; ldev->caps.ycbcr_input =3D true; ldev->caps.ycbcr_output =3D true; @@ -1872,6 +1876,8 @@ void ltdc_suspend(struct drm_device *ddev) =20 DRM_DEBUG_DRIVER("\n"); clk_disable_unprepare(ldev->pixel_clk); + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1887,7 +1893,13 @@ int ltdc_resume(struct drm_device *ddev) return ret; } =20 - return 0; + if (ldev->bus_clk) { + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) + drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + } + + return ret; } =20 int ltdc_load(struct drm_device *ddev) @@ -1922,6 +1934,19 @@ int ltdc_load(struct drm_device *ddev) return -ENODEV; } =20 + if (of_device_is_compatible(np, "st,stm32mp251-ltdc")) { + ldev->bus_clk =3D devm_clk_get(dev, "bus"); + if (IS_ERR(ldev->bus_clk)) + return dev_err_probe(dev, PTR_ERR(ldev->bus_clk), + "Unable to get bus clock\n"); + + ret =3D clk_prepare_enable(ldev->bus_clk); + if (ret) { + drm_err(ddev, "Unable to prepare bus clock\n"); + return ret; + } + } + /* Get endpoints if any */ for (i =3D 0; i < nb_endpoints; i++) { ret =3D drm_of_find_panel_or_bridge(np, 0, i, &panel, &bridge); @@ -2034,6 +2059,9 @@ int ltdc_load(struct drm_device *ddev) =20 clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + pinctrl_pm_select_sleep_state(ddev->dev); =20 pm_runtime_enable(ddev->dev); @@ -2042,6 +2070,9 @@ int ltdc_load(struct drm_device *ddev) err: clk_disable_unprepare(ldev->pixel_clk); =20 + if (ldev->bus_clk) + clk_disable_unprepare(ldev->bus_clk); + return ret; } =20 diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index 9d488043ffdbc652deeede71c9d57d45fb89d3c6..ddfa8ae61a7ba5dc446fae64756= 2d0ec8e6953e1 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -40,10 +40,15 @@ struct fps_info { ktime_t last_timestamp; }; =20 +struct ltdc_plat_data { + int pad_max_freq_hz; /* max frequency supported by pad */ +}; + struct ltdc_device { void __iomem *regs; struct regmap *regmap; struct clk *pixel_clk; /* lcd pixel clock */ + struct clk *bus_clk; /* bus clock */ struct mutex err_lock; /* protecting error_status */ struct ltdc_caps caps; u32 irq_status; --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 863F33218A7; Tue, 19 Aug 2025 09:18:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755595140; cv=none; b=Y4LB5v7mqkUdoKyQSS4HLLB7yXEZaSksAIbNPOgkgKnpUveyxAnazsoNR/8SS7eierj2tB3S4n7p8nfLB3Yzi29Gh7W4ig2CTlTXHMAWHovVkOGNENef4b+d8ujQdaxrtlJzMBnbPvtpj0jSnrQgXhIwlnBIOfQDBsp3SDGwQuA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1755595140; c=relaxed/simple; bh=M1epPi1z75So7wCDT7hunVpp0NtGO9StJqs3OghkwYI=; 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Tue, 19 Aug 2025 11:16:58 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D50B371CDA4; Tue, 19 Aug 2025 11:16:01 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:16:01 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:16:01 +0200 Subject: [PATCH v3 08/13] drm/stm: ltdc: handle lvds pixel clock Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-8-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 From: Yannick Fertre Handle LVDS pixel clock. The LTDC operates with multiple clock domains for register access, requiring all clocks to be provided during read/write operations. This imposes a dependency between the LVDS and LTDC to access correctly all LTDC registers. And because both IPs' pixel rates must be synchronized, the LTDC has to handle the LVDS clock. Signed-off-by: Yannick Fertre Signed-off-by: Raphael Gallais-Pou --- drivers/gpu/drm/stm/ltdc.c | 22 +++++++++++++++++++++- drivers/gpu/drm/stm/ltdc.h | 1 + 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 74e93f076b62a46e7835985d9d330ba66d990e58..a4c2a1e960fbe426bf5dd2b3f0a= 88ccff927d041 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -837,6 +837,12 @@ ltdc_crtc_mode_valid(struct drm_crtc *crtc, int target_max =3D target + CLK_TOLERANCE_HZ; int result; =20 + if (ldev->lvds_clk) { + result =3D clk_round_rate(ldev->lvds_clk, target); + drm_dbg_driver(crtc->dev, "lvds pixclk rate target %d, available %d\n", + target, result); + } + result =3D clk_round_rate(ldev->pixel_clk, target); =20 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); @@ -1878,6 +1884,8 @@ void ltdc_suspend(struct drm_device *ddev) clk_disable_unprepare(ldev->pixel_clk); if (ldev->bus_clk) clk_disable_unprepare(ldev->bus_clk); + if (ldev->lvds_clk) + clk_disable_unprepare(ldev->lvds_clk); } =20 int ltdc_resume(struct drm_device *ddev) @@ -1895,8 +1903,16 @@ int ltdc_resume(struct drm_device *ddev) =20 if (ldev->bus_clk) { ret =3D clk_prepare_enable(ldev->bus_clk); - if (ret) + if (ret) { drm_err(ddev, "failed to enable bus clock (%d)\n", ret); + return ret; + } + } + + if (ldev->lvds_clk) { + ret =3D clk_prepare_enable(ldev->lvds_clk); + if (ret) + drm_err(ddev, "failed to prepare lvds clock\n"); } =20 return ret; @@ -1980,6 +1996,10 @@ int ltdc_load(struct drm_device *ddev) } } =20 + ldev->lvds_clk =3D devm_clk_get(dev, "lvds"); + if (IS_ERR(ldev->lvds_clk)) + ldev->lvds_clk =3D NULL; + rstc =3D devm_reset_control_get_exclusive(dev, NULL); =20 mutex_init(&ldev->err_lock); diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h index ddfa8ae61a7ba5dc446fae647562d0ec8e6953e1..17b51a7ce28eee5de6d24ca943c= a3b1f48695dfd 100644 --- a/drivers/gpu/drm/stm/ltdc.h +++ b/drivers/gpu/drm/stm/ltdc.h @@ -48,6 +48,7 @@ struct ltdc_device { void __iomem *regs; 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It provides a parallel digital RGB flow to be used by display interfaces. Add the LTDC node. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 303abf915b8e489671b51a8c832041c14a42ecb8..372a99d9cc5c3730e8fbeddeb61= 34a3b18d938b6 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1576,6 +1576,18 @@ dcmipp: dcmipp@48030000 { status =3D "disabled"; }; =20 + ltdc: display-controller@48010000 { + compatible =3D "st,stm32mp251-ltdc"; + reg =3D <0x48010000 0x400>; + interrupts =3D , + ; + clocks =3D <&rcc CK_KER_LTDC>, <&rcc CK_BUS_LTDC>; + clock-names =3D "lcd", "bus"; + resets =3D <&rcc LTDC_R>; + access-controllers =3D <&rifsc 80>; + status =3D "disabled"; + }; + combophy: phy@480c0000 { compatible =3D "st,stm32mp25-combophy"; reg =3D <0x480c0000 0x1000>; --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7157C31E10E; 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Add the LVDS node. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp255.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index f689b47c5010033120146cf1954d6624c0270045..a3b5ae25d28c83ade12c2ff69b8= 2c9cccfd29b00 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -6,6 +6,18 @@ #include "stm32mp253.dtsi" =20 &rifsc { + lvds: lvds@48060000 { + compatible =3D "st,stm32mp255-lvds", "st,stm32mp25-lvds"; + #clock-cells =3D <0>; + reg =3D <0x48060000 0x2000>; + clocks =3D <&rcc CK_BUS_LVDS>, <&rcc CK_KER_LVDSPHY>; + clock-names =3D "pclk", "ref"; + resets =3D <&rcc LVDS_R>; + access-controllers =3D <&rifsc 84>; + power-domains =3D <&CLUSTER_PD>; + status =3D "disabled"; + }; + vdec: vdec@480d0000 { compatible =3D "st,stm32mp25-vdec"; reg =3D <0x480d0000 0x3c8>; @@ -22,4 +34,4 @@ venc: venc@480e0000 { clocks =3D <&rcc CK_BUS_VENC>; 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Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 372a99d9cc5c3730e8fbeddeb6134a3b18d938b6..6d9c0a430a8cc82542029f18b8a= 1a954a7c4fddb 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -1868,6 +1868,7 @@ exti1: interrupt-controller@44220000 { syscfg: syscon@44230000 { compatible =3D "st,stm32mp25-syscfg", "syscon"; reg =3D <0x44230000 0x10000>; + #clock-cells =3D <0>; }; =20 pinctrl: pinctrl@44240000 { --=20 2.25.1 From nobody Sat Oct 4 08:03:01 2025 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5818257AC6; Tue, 19 Aug 2025 09:18:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 19 Aug 2025 11:18:16 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4FB9740044; Tue, 19 Aug 2025 11:17:02 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 66A1871763A; Tue, 19 Aug 2025 11:16:04 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:16:04 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:16:05 +0200 Subject: [PATCH v3 12/13] arm64: dts: st: enable display support on stm32mp257f-ev1 board Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-12-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 Enable the following IPs on stm32mp257f-ev1 in order to get display: * LTDC * LVDS * WSVGA LVDS panel (1024x600) * Panel LVDS backlight as GPIO backlight * ILI2511 i2c touchscreen Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 79 ++++++++++++++++++++++++++= ++++ 1 file changed, 79 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 836b1958ce65fb72c99d634a92af3efaf9844d76..2958ad413b0675575d84942e193= a16f80197b88e 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -86,6 +86,43 @@ mm_ospi1: mm-ospi@60000000 { no-map; }; }; + + panel_lvds: display { + compatible =3D "edt,etml0700z9ndha", "panel-lvds"; + enable-gpios =3D <&gpiog 15 GPIO_ACTIVE_HIGH>; + backlight =3D <&panel_lvds_backlight>; + power-supply =3D <&scmi_v3v3>; + status =3D "okay"; + + width-mm =3D <156>; + height-mm =3D <92>; + data-mapping =3D "vesa-24"; + + panel-timing { + clock-frequency =3D <54000000>; + hactive =3D <1024>; + vactive =3D <600>; + hfront-porch =3D <150>; + hback-porch =3D <150>; + hsync-len =3D <21>; + vfront-porch =3D <24>; + vback-porch =3D <24>; + vsync-len =3D <21>; + }; + + port { + lvds_panel_in: endpoint { + remote-endpoint =3D <&lvds_out0>; + }; + }; + }; + + panel_lvds_backlight: backlight { + compatible =3D "gpio-backlight"; + gpios =3D <&gpioi 5 GPIO_ACTIVE_HIGH>; + default-on; + status =3D "okay"; + }; }; =20 &arm_wdt { @@ -183,6 +220,15 @@ imx335_ep: endpoint { }; }; }; + + ili2511: ili2511@41 { + compatible =3D "ilitek,ili251x"; + reg =3D <0x41>; + interrupt-parent =3D <&gpioi>; + interrupts =3D <13 IRQ_TYPE_EDGE_FALLING>; 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Tue, 19 Aug 2025 11:18:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id B19184005C; Tue, 19 Aug 2025 11:17:02 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node2.st.com [10.75.129.70]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id F32FE71CDB4; Tue, 19 Aug 2025 11:16:04 +0200 (CEST) Received: from localhost (10.130.74.180) by SHFDAG1NODE2.st.com (10.75.129.70) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 19 Aug 2025 11:16:04 +0200 From: Raphael Gallais-Pou Date: Tue, 19 Aug 2025 11:16:06 +0200 Subject: [PATCH v3 13/13] arm64: dts: st: add loopback clocks on LTDC node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250819-drm-misc-next-v3-13-04153978ebdb@foss.st.com> References: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> In-Reply-To: <20250819-drm-misc-next-v3-0-04153978ebdb@foss.st.com> To: Yannick Fertre , Philippe Cornu , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Maxime Coquelin" , Alexandre Torgue , Catalin Marinas , Will Deacon , Christophe Roullier CC: , , , , X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE2.st.com (10.75.129.70) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-19_01,2025-08-14_01,2025-03-28_01 ck_ker_ltdc has the CLK_SET_RATE_PARENT flag. While having this flag is semantically correct, it for now leads to an improper setting of the clock rate. The ck_ker_ltdc parent clock is the flexgen 27, which does not support changing rates yet. To overcome this issue, a fixed clock can be used for the kernel clock. Add the clocks needed for the LTDC to work. Signed-off-by: Raphael Gallais-Pou --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 6 ++++++ arch/arm64/boot/dts/st/stm32mp255.dtsi | 5 +++++ 2 files changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index 6d9c0a430a8cc82542029f18b8a1a954a7c4fddb..24823bbfee31f15e813573ad1a0= c4f67a125ce51 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -52,6 +52,12 @@ clk_rcbsec: clk-rcbsec { compatible =3D "fixed-clock"; clock-frequency =3D <64000000>; }; + + clk_flexgen_27_fixed: clk-54000000 { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <54000000>; + }; }; =20 firmware { diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/s= t/stm32mp255.dtsi index a3b5ae25d28c83ade12c2ff69b82c9cccfd29b00..07c200470b2cedde771ae987f22= 67d6097ea78f0 100644 --- a/arch/arm64/boot/dts/st/stm32mp255.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi @@ -5,6 +5,11 @@ */ #include "stm32mp253.dtsi" =20 +<dc { + clocks =3D <&clk_flexgen_27_fixed>, <&rcc CK_BUS_LTDC>, <&syscfg>, <&lvds= >; + clock-names =3D "lcd", "bus", "ref", "lvds"; +}; + &rifsc { lvds: lvds@48060000 { compatible =3D "st,stm32mp255-lvds", "st,stm32mp25-lvds"; --=20 2.25.1